Electronics Guide

When an Interconnect Becomes a Transmission Line

Signals travel at a finite speed set by the surrounding dielectric. On ordinary FR-4 laminate, a surface microstrip propagates at roughly 150 picoseconds per inch, while a buried stripline is closer to 170 to 180 picoseconds per inch because it is fully embedded in resin and glass and therefore sees a higher effective permittivity. A conductor behaves as a simple connection only while its round-trip delay remains short compared with the signal transition time. Once the round trip approaches the rise time, the reflection from the far end returns while the driver is still switching, and the trace must be treated as a transmission line with a defined characteristic impedance and a deliberate termination strategy. A widely used conservative rule of thumb flags any FR-4 interconnect longer than about 2 inches per nanosecond of rise time as electrically long.

The frequency content that matters follows from the same reasoning. The spectrum of a digital edge falls away above a knee frequency of approximately 0.5 divided by the rise time, so a 100 picosecond transition carries significant energy to roughly 5 GHz regardless of how slowly the signal repeats. Interconnect must therefore be engineered across that entire band. Single-ended traces are most often built to a nominal 50 ohms; differential pairs follow the standard they serve, commonly 100 ohms for Ethernet and LVDS, 90 ohms for USB, and 85 ohms for PCI Express. Holding those targets across manufacturing tolerance requires coordinated choices of trace width, dielectric thickness, copper weight, and laminate.

Reflections and Termination

Wherever the impedance a signal encounters changes, part of the wave reflects. The reflection coefficient equals the difference between the load and line impedances divided by their sum, so a 25 percent impedance step returns about 11 percent of the incident amplitude. Real channels contain many such steps: connector transitions, via barrels and antipads, package leads and bond wires, layer changes, unterminated branches, and the receiver input itself. The resulting ringing, overshoot, and settling delay erode voltage and timing margin, and in severe cases produce false switching at a logic input.

Termination suppresses reflections by presenting a matched impedance. Series, or source, termination places a resistor at the driver so that the driver output impedance and the resistor together equal the line impedance; it suits point-to-point nets, dissipates no static power, and delivers full swing at the far end after one round trip. Parallel termination places the matching resistance at the receiver, either to a reference rail or as a Thevenin pair, and preserves signal shape along the whole line at the cost of continuous current. Alternating-current termination adds a series capacitor to block that direct current, and on-die termination integrates the resistor into the receiver, where it eliminates the stub between package and die that a discrete resistor would introduce.

Crosstalk and Coupling

Adjacent conductors couple through mutual capacitance and mutual inductance, injecting noise from a switching aggressor net into a quiet victim. Coupling toward the driver end of the victim is called near-end crosstalk, and coupling toward the far end is called far-end crosstalk. Near-end crosstalk saturates once the coupled length exceeds roughly half the physical extent of the rising edge, so beyond that length it grows no further. Far-end crosstalk instead accumulates with coupled length and is proportional to the rate of change of the edge, which makes it the dominant concern on long parallel runs. In a homogeneous dielectric such as stripline, the capacitive and inductive contributions largely cancel and far-end crosstalk nearly vanishes; microstrip, with air above and laminate below, offers no such cancellation.

Mitigation follows directly from the coupling mechanism. Increasing separation reduces both terms, and a common guideline holds spacing between neighboring traces to at least three line widths. Bringing the trace closer to its reference plane is often more effective still, because the field then concentrates between conductor and plane rather than spreading toward neighbors. Routing adjacent layers orthogonally, placing ground fills only where they can be stitched thoroughly to the reference plane, and shortening parallel runs all reduce coupling. Because crosstalk arrives asynchronously and shifts switching thresholds, it consumes both voltage margin and timing margin, and it must be budgeted alongside reflections and loss rather than treated separately.

Loss, Dispersion, and Equalization

Above a few hundred megahertz, real interconnect attenuates high frequencies more than low ones. Conductor loss rises with the square root of frequency because current crowds into a shrinking skin depth—about 2 micrometers in copper at 1 GHz and well under 1 micrometer at 10 GHz. Copper foil roughness, deliberately created to bond the conductor to the resin, becomes comparable to that skin depth and adds further loss, which is why low-profile and very-low-profile foils appear in demanding stackups. Dielectric loss rises roughly in proportion to frequency and to the laminate loss tangent, which is near 0.02 for conventional FR-4 but falls to a few thousandths for low-loss laminates. Because attenuation varies with frequency, edges spread in time, one symbol smears into the next, and the resulting inter-symbol interference closes the eye.

Equalization restores what the channel removed. Transmitters apply feed-forward equalization, often described as de-emphasis or pre-shoot, to boost the high-frequency content of transitions. Receivers add a continuous-time linear equalizer that tilts the channel response upward and a decision feedback equalizer that subtracts the trailing influence of symbols already resolved without amplifying noise. The longest channels use analog-to-digital converters followed by digital signal processing, which permits far more taps and adaptive tuning. Higher rates also change the modulation: four-level pulse amplitude modulation (PAM4) carries two bits per symbol and halves the symbol rate for a given throughput, but its three stacked eyes cost roughly 9.5 dB of signal-to-noise ratio relative to two-level signaling, so forward error correction becomes mandatory. PCI Express adopted this combination at 64 GT/s, and the PCI Express 7.0 specification, released to members in June 2025, extends the approach to 128 GT/s. Ethernet is following a parallel path toward roughly 200 Gb/s per electrical lane in the IEEE P802.3dj project.

Jitter, Noise, and Timing Margin

Jitter analysis separates timing uncertainty into random and deterministic components. Random jitter arises from thermal and shot noise, is well modeled as Gaussian, and is unbounded, so it is characterized by a standard deviation rather than a peak value. Deterministic jitter is bounded and traceable to specific causes: data-dependent jitter from inter-symbol interference, duty-cycle distortion from asymmetric switching thresholds, periodic jitter from power-supply ripple or coupled clocks, and bounded uncorrelated jitter from crosstalk. Because the random part has no worst case, total jitter is quoted at a target bit error ratio; at a bit error ratio of 10^-12 the random standard deviation is multiplied by roughly 14 to obtain the peak-to-peak contribution added to the deterministic terms.

The bathtub curve makes this concrete by plotting bit error ratio against sampling position within the unit interval, with the flat floor showing the horizontal eye opening available to the receiver. Modern links complicate the picture in two directions. Power-supply-induced jitter converts noise on a supply rail into phase modulation inside the transmitter and the clocking circuits, tying timing margin directly to power integrity. At the same time, clock and data recovery tracks low-frequency wander and effectively removes it, so only jitter above the loop bandwidth of the recovery circuit consumes margin. Meaningful budgets therefore account for the reference clock phase noise, the jitter transfer of every phase-locked loop in the path, and the response of the receiver, rather than summing raw measured numbers.

Modeling, Simulation, and Measurement

Engineers predict signal integrity before hardware exists, then confirm it once boards arrive. Two-dimensional field solvers extract impedance, coupling, and loss from a cross section, while three-dimensional full-wave solvers handle the geometry that a cross section cannot describe: vias, connectors, breakout regions, and packages. Their results are exchanged as scattering parameters in Touchstone files, which should be checked for passivity, causality, and reciprocity before use, since a nonphysical model produces confident and wrong answers. Device behavior comes from IBIS models for buffer edges and impedance, and from IBIS-AMI models, which encapsulate transmitter and receiver equalization algorithms so that a serial link may be simulated statistically to error rates far below what bit-by-bit simulation could reach. Channel operating margin, defined in the IEEE 802.3 standard, condenses such an analysis into a single figure of merit for a complete channel.

Measurement closes the loop. Time-domain reflectometry locates impedance discontinuities along a channel and resolves features in proportion to its own rise time. Vector network analyzers characterize insertion loss, return loss, and crosstalk across frequency with high dynamic range. Real-time and equivalent-time sampling oscilloscopes capture eye diagrams and decompose jitter, and bit error ratio testers measure the margin that actually matters. At multi-gigabit rates the fixture becomes part of the measurement, so calibration and de-embedding of probes, cables, and launch structures are as important as the instrument itself. Correlating measured results against the pre-layout simulation is the step that turns a model into a trustworthy design tool.

Design Practice and System Interactions

The stackup and the return path decide most signal integrity outcomes. Current returns through the path of least impedance, which above roughly 100 kHz lies directly beneath the trace, so every high-speed signal needs a continuous reference plane. A gap, a split, or a routing channel crossed by a fast edge forces the return current to detour, adding loop inductance, generating common-mode current, and radiating efficiently. Layer transitions demand the same discipline: ground vias adjacent to signal vias give the return current a nearby path, and stitching capacitors serve that role when a signal must change between planes at different potentials. Unused via barrels form quarter-wave stubs that create deep nulls in the channel response, which is why back-drilling is routine on high-speed backplanes. Woven glass reinforcement introduces another subtlety, since resin-rich and glass-rich regions differ in permittivity and can skew the two halves of a differential pair; routing at a slight angle to the weave or specifying spread-glass fabrics reduces the effect.

Signal integrity, power integrity, and electromagnetic compatibility are three views of the same electromagnetic problem. Every switching output draws its charge from the power distribution network, and the resulting simultaneous switching noise and ground bounce shift reference levels, corrupt quiet signals, and modulate timing. A power distribution network is therefore designed to a target impedance derived from the tolerable ripple and the expected transient current, using a hierarchy of bulk, ceramic, and on-die capacitance to hold that impedance low across frequency. The same return-path discontinuities that degrade a waveform are also the structures that radiate and that couple external energy inward, so a layout that respects return current usually satisfies emissions requirements with far less remedial shielding and filtering. Treating the three disciplines together, early in the architecture, costs far less than correcting any of them after fabrication.

Subcategories

This section organizes signal integrity into focused topics, progressing from the underlying physics of transmission lines and reflections to the system-level disciplines of high-speed PCB design, SerDes links, power and ground architecture, measurement, and emerging interconnect technologies. The following topics explore each area in depth.