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Why a Via Is Not a Wire

A via is a three-dimensional structure embedded in a stack of copper planes. The plated barrel carries the signal. Surface and internal pads anchor it. An antipad—the clearance opening etched in each plane the barrel passes through—keeps the barrel from shorting to that plane. Barrel, antipad, and plane together resemble a short and badly terminated coaxial line whose dielectric is the board laminate.

Three distinct mechanisms make that structure visible to a fast signal. The first is reactive loading: the pads and antipads add capacitance, and the barrel adds inductance, producing a local impedance discontinuity that reflects energy. The second is the stub, the portion of a plated through hole that the signal does not use; it hangs off the through path as an open-circuited transmission line and resonates. The third is return path disruption: the signal changes reference layers at the via, and the return current must find its own way across, often through a longer and more inductive route than the designer intended.

Whether these mechanisms matter depends on the signal, not on the frequency alone. Propagation through common laminate with a relative permittivity near 4 takes roughly 6.7 picoseconds per millimeter, or about 170 picoseconds per inch. A via through a 1.6 mm board therefore represents about 11 picoseconds of one-way delay. When edge rates were measured in nanoseconds, that delay was invisible. When a serial link presents transition times of a few tens of picoseconds, the via is an appreciable fraction of an edge and must be treated as a distributed structure.

Via Types and Construction

The choice of via construction is the single largest determinant of both electrical performance and board cost. It should be made with the stackup, not after routing has begun.

Plated Through Holes

The plated through hole is drilled mechanically after the full stack is laminated and plated through its entire length. It is the cheapest via to build and the only one available on a conventionally laminated board. Its weakness is that it always spans the whole stack, so any layer transition that does not use the full thickness leaves a stub.

Blind and Buried Vias

A blind via connects an outer layer to one or more inner layers without passing through the board. A buried via connects inner layers only and is invisible from either surface. Both require sequential lamination: sub-assemblies are drilled and plated, then bonded together and drilled again. Each additional lamination cycle adds cost and lead time, but the reward is a via whose length matches the transition it serves, which removes the stub problem at its source and reduces both capacitance and inductance.

Microvias

A microvia is a small laser-drilled blind structure, normally spanning a single dielectric layer. IPC-T-50 defines it as a blind structure with a maximum aspect ratio of 1:1 and a total depth of no more than 0.25 mm measured from the capture land to the target land. Microvias are the enabling element of high-density interconnect construction. They can be staggered from layer to layer or stacked directly on top of one another to form a continuous vertical path, and any-layer HDI boards build every transition from stacked or staggered microvias. Electrically they are close to ideal: the barrels are short, the parasitics are small, and there is no stub.

Backdrilled Vias

Backdrilling, also called controlled-depth drilling, removes the plating from the unused end of a plated through hole after fabrication. It buys most of the electrical benefit of a blind via at a fraction of the cost of sequential lamination, which is why it dominates in thick backplanes and large line cards.

Parasitic Capacitance, Inductance, and Impedance

First-order estimates of via parasitics are useful for early trade studies. The classic closed-form expressions from high-speed digital design practice give the pad-to-plane capacitance as approximately 1.41 × ε_r × T × D1 ÷ (D2 − D1) picofarads, where T is the board thickness, D1 the pad diameter, and D2 the antipad diameter, all in inches, and the barrel inductance as approximately 5.08 × h × [ln(4h ÷ d) + 1] nanohenries, where h is the barrel length and d the drill diameter in inches. For a via through a 1.6 mm board of permittivity 4, with a 0.7 mm pad, a 1.4 mm antipad, and a 0.35 mm drill, those expressions predict roughly 0.4 pF and roughly 1.2 nH.

Both formulas are approximations that ignore the cavity behavior of the plane pair and the frequency dependence of the fields. They are adequate for ranking design options below a gigahertz or two. Above that, the via must be extracted with a three-dimensional field solver, because the barrel, the antipads, and the surrounding plane cavity interact in ways no lumped model captures.

The net effect of a typical through via is capacitive: the pad and antipad capacitance dominates, and a time-domain reflectometer sees a dip in impedance at the via. The design levers follow directly from the parasitic expressions.

• Enlarge the antipad. Increasing the plane clearance reduces capacitance and raises the local impedance. The limit is set by plane integrity: overlapping antipads in a dense field carve slots in the reference plane and damage the return path.
• Remove non-functional pads. Internal pads on layers the via does not connect to contribute capacitance and nothing else. Most fabricators will suppress them on request.
• Shrink the pad and the drill. Smaller lands reduce capacitance; smaller drills raise inductance slightly but shorten the antipad needed for a given clearance.
• Shorten the barrel. Every parasitic scales with length, so blind, buried, and micro construction improve all of them at once.

Because capacitance and inductance move in opposite directions, a well-designed via is one whose parasitics are balanced so that the structure approximates the characteristic impedance of the traces it joins, rather than one whose parasitics are individually minimized.

Stub Resonance and Backdrilling

The stub is the portion of a plated through hole beyond the layer where the signal exits. It behaves as an open-circuited transmission line. At the frequency where the stub is a quarter wavelength long, it presents a short circuit at the through path and produces a deep notch in insertion loss. The resonant frequency is approximately

f ≈ c ÷ (4 × L × √D_k)

where c is the speed of light, L is the stub length, and D_k is the effective relative permittivity of the laminate. A 2.5 mm (100 mil) stub in material with a permittivity of 4 resonates near 15 GHz. That notch sits squarely inside the spectrum of a 25 Gbps non-return-to-zero link or a PAM4 link of comparable rate, and no amount of equalization recovers the lost band.

The remedies form a natural cost ladder. Layer assignment comes first and is free: routing a critical net on the layer that leaves the shortest stub often solves the problem outright. Backdrilling comes next. Blind, buried, or micro construction comes last, and a thinner board reduces the worst-case stub for every net at once.

Backdrilling is performed with a drill oversized relative to the primary hole—commonly by about 0.2 to 0.25 mm—so that all barrel plating is removed without cutting into the annular rings of the layers below. Depth is controlled to a tolerance on the order of a tenth of a millimeter, and a deliberate allowance is left so that the drill never reaches the last connected layer. The practical result is a residual stub of roughly 0.13 to 0.25 mm (5 to 10 mils). A 10 mil residual stub places the quarter-wave resonance near 150 GHz in permittivity-4 material, far beyond the bandwidth of any current digital interface. Designers should confirm achievable stub length with the fabricator early, because volume production capability is often looser than the best coupon results.

The Return Path Through a Via

Every via that changes a signal's reference layer also forces the return current to change layers. Managing that transition is at least as important as managing the parasitics of the signal barrel, and it is more often neglected.

When the two reference planes sit at the same potential—for example, a transition between two layers that both reference ground—the fix is a stitching via that ties the planes together close to the signal via. Proximity matters because the loop enclosed by the signal via and its return via sets the transition inductance. Common practice keeps return vias within a few tens of mils of the signal via, tightening that distance as the operating frequency rises, and places them symmetrically around a differential pair so that the two halves see identical return structures. Asymmetric return via placement is a leading cause of differential-to-common mode conversion in via transitions.

When the reference planes sit at different potentials—a ground plane on one side of the transition and a power plane on the other—no stitching via is possible. The return current must cross through the interplane capacitance of the stackup or through a discrete stitching capacitor placed nearby. Both paths add inductance, and the equivalent series inductance of the capacitor plus its own mounting vias frequently dominates. The better answer is to avoid the situation: assign layers so that critical nets keep the same reference throughout, and reserve reference changes for slower signals.

Return current that cannot find a tight path spreads into the plane pair and excites parallel-plate cavity modes. Those modes radiate, couple energy into every other via that shares the cavity, and turn what looked like a local problem into a board-level electromagnetic compatibility problem. Plane stitching around board edges and around dense via fields suppresses them.

Via Fields, Pitch, and Crosstalk

Vias rarely appear alone. Beneath a ball grid array the escape pattern inherits the ball pitch—commonly 1.0 mm, 0.8 mm, or 0.65 mm—and hundreds of vias are packed into a few square centimeters. Connector footprints and press-fit backplane fields are similarly dense.

Density creates two coupled problems. Antipads that overlap merge into slots and voids that remove the reference plane exactly where the return current needs it, so the individual via that looked well designed in isolation performs poorly in the array. Vias that share a plane cavity also couple to one another through it. Via-to-via crosstalk grows with barrel length and often exceeds trace crosstalk in thick backplanes, where barrels of several millimeters run parallel through the same cavity.

Effective countermeasures include increasing separation between aggressor and victim signal vias, interleaving ground vias so that each signal via or differential pair has a nearby return, arranging ground vias as a fence around sensitive transitions, staggering rather than aligning breakout vias to break up regular coupling, and shortening barrels through backdrilling or blind construction. In the densest fields the antipad size becomes a compromise: large enough to control capacitance, small enough to preserve continuous copper between neighbors.

Fabrication, Thermal, and Reliability Limits

Electrical optimization is bounded by what a fabricator can build and by what will survive assembly and service life.

The governing manufacturing constraint for plated through holes is the aspect ratio, defined as board thickness divided by drilled hole diameter. An aspect ratio near 8:1 is routine, 10:1 is widely achievable with process validation, and ratios beyond 12:1 are specialty work. As the ratio climbs, plating solution exchange inside the barrel becomes difficult, copper thickness grows uneven, and the risk of voids and barrel cracks rises. Because thickness is usually fixed by mechanical and stackup requirements, the aspect ratio effectively sets the minimum drill diameter, which in turn sets the pad and antipad geometry available for tuning.

Microvias carry their own reliability caveat. IPC published white paper IPC-WP-023 in 2018 to warn the industry about a weak interface between a copper-filled stacked microvia and its target pad. Under the thermal stress of reflow soldering the interface can fracture, and because the defect often does not appear in electrical testing at room temperature, it can escape into service as an intermittent failure. The warning was carried forward into IPC-6012E. Staggering microvias rather than stacking them, limiting stack height, and specifying thermal-cycle or reflow-based via chain continuity testing all reduce exposure.

Via-in-pad construction—placing a via inside a surface-mount land—saves enormous space in fine-pitch escapes, but it demands that the via be filled and planarized so that solder does not wick down the barrel. IPC-4761 catalogs the available treatments, from simple tenting under solder mask (Type I) through plugging and filling to the filled-and-capped copper treatment (Type VII) required for reliable via-in-pad.

Vias also serve as thermal paths. Arrays of small vias under power devices conduct heat from the component land to internal and bottom-side copper. Thermal via design interacts with signal integrity because those arrays perforate the same reference planes that carry return current, so thermal and electrical requirements should be reconciled during floorplanning rather than afterward.

Cost tracks complexity closely. Each sequential lamination cycle, each laser drill pass, each backdrill operation, and each additional via fill step adds process time and yield risk. A design that specifies blind and buried vias everywhere, when backdrilled through holes would have met the budget, spends money for no measurable benefit.

A Practical Optimization Workflow

1. Allocate a budget. Determine from the channel budget how much insertion loss, return loss, and mode conversion the via transitions may contribute, and where in frequency any resonance must not fall.
2. Fix the stackup and layer assignment first. Most via problems are stackup problems. Choose reference planes so that critical nets keep the same reference across every transition, and assign layers so that stubs are short by construction.
3. Select via construction to match the budget. Escalate from plated through hole, to backdrilled through hole, to blind, buried, or micro construction only as the budget requires.
4. Parameterize and simulate. Build a three-dimensional model of the transition, including pads, antipads, return vias, and adjacent traces. Sweep antipad diameter, pad diameter, return via placement, and stub length, and extract scattering parameters over the full band of interest.
5. Cascade into a channel simulation. A via that looks acceptable alone may be unacceptable when two, four, or eight of them appear in the same link. Evaluate the eye or the bit error ratio contour with all transitions in place.
6. Correlate to measurement. Fabricate coupons with the chosen geometry, measure them with a vector network analyzer or a time-domain reflectometer, and reconcile the results with the model before committing to production.
7. Review with the fabricator. Confirm drill sizes, aspect ratios, backdrill depth tolerance, residual stub capability, fill type, and registration tolerance against the shop that will actually build the board.

Bringing It Together

Vias are unavoidable, and at modern data rates they are frequently the limiting element of an otherwise well-designed channel. The three failure mechanisms—reactive discontinuity, stub resonance, and return path disruption—are all geometric in origin, which means they are all controllable through stackup planning, layer assignment, and construction choice. The most effective work happens early: a stackup that keeps references consistent and stubs short eliminates problems that no amount of later tuning can fully repair. Simulation and coupon correlation then confirm the design and quantify the margin, and an early conversation with the fabricator keeps the chosen geometry inside what can be manufactured repeatably and affordably.

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