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Why Serialize

A wide parallel bus seems like the straightforward way to move many bits, but it does not scale to high speed. Every parallel wire must arrive at the receiver aligned in time, and the unavoidable differences in trace length, via count, and coupling spread those arrivals apart. The margin available for that spread shrinks as rates climb: at 32 GT/s the unit interval is only 31.25 picoseconds, so a few picoseconds of skew consumes a large share of the timing budget. Add the crosstalk and simultaneous-switching noise that a dense bundle of parallel signals generates, and the practical ceiling on a synchronous parallel bus arrives well below the rates a single well-designed lane can reach.

SerDes sidesteps the problem. It sends the data as one high-rate stream over a single differential pair, so there is no inter-wire skew to manage, and it recovers the clock from the data itself rather than carrying it on a separate line that drifts with respect to the data. The payoff is fewer pins, fewer board traces, smaller and cheaper connectors, and lower electromagnetic emissions, all while the per-lane rate climbs into the tens or hundreds of gigabits per second. Bandwidth then scales by adding lanes in parallel, each with its own independent clock recovery, rather than by clocking a wide bus faster. Lanes still need coarse alignment, but a deskew step at the protocol layer handles differences of many bit periods, which is a far easier problem than holding picosecond skew across a bus.

The SerDes Datapath

A SerDes link is organized as a transmit chain and a receive chain joined by a channel of package traces, board traces, vias, connectors, and cables. Each stage exists to launch a clean signal, survive the channel, and reconstruct the original bits.

Transmit Path

A phase-locked loop multiplies a low-frequency reference clock, commonly 100 MHz in PCI Express systems, up to the symbol rate. Parallel data from the core logic passes through the physical coding sublayer, where it is scrambled and encoded for the line, and the serializer, typically a tree of two-to-one multiplexers, shifts the bits out one at a time at full rate. A differential output driver launches the stream into the channel. Current-mode drivers offer good output impedance control and headroom, while voltage-mode or source-series-terminated drivers deliver the same swing at a fraction of the supply current, which is why they dominate at high lane counts. A feed-forward equalizer with pre-cursor and post-cursor taps pre-distorts the waveform, emphasizing edges and de-emphasizing steady levels so that the signal arrives with a flatter response after the channel attenuates its high-frequency content.

Receive Path

At the far end, the signal arrives attenuated and smeared by intersymbol interference. The receiver terminates the line, usually to a 100-ohm differential impedance, to suppress reflections, and series capacitors AC-couple the pair so that each end can set its own common-mode voltage. A continuous-time linear equalizer (CTLE) restores high-frequency gain, and a decision-feedback equalizer (DFE) cancels residual trailing interference using the receiver's own past decisions, a structure that removes intersymbol interference without amplifying noise the way a purely linear boost does. Slicers then decide each symbol against one or more thresholds, and a deserializer reassembles the recovered bits into a parallel word. Because the DFE must resolve a decision and feed it back within one unit interval, high-rate designs unroll the first tap through speculative slicers and process several symbols in parallel.

Clock and Data Recovery

Because SerDes sends no separate clock alongside the data, the receiver extracts its sampling clock from the transitions in the stream. The clock and data recovery (CDR) circuit locks onto those edges and positions the sampling instant where the eye is most open. Most modern designs use a bang-bang phase detector driving a phase interpolator that steps a clock derived from a shared PLL, which avoids a per-lane oscillator and keeps area and power in check. Loop bandwidth is a deliberate compromise: a wide loop tracks more transmitter jitter and spread-spectrum modulation, while a narrow loop rejects more high-frequency noise. Reliable recovery depends on frequent transitions in the data, which is one reason line coding matters, since long runs of identical symbols starve the loop of the edges it needs.

Coding Sublayer and Elastic Buffering

Above the analog front end sits the logic that makes a lane usable. It aligns the recovered bit stream to symbol and block boundaries, deskews the lanes of a multi-lane link so that the aggregate data emerges in order, and hands words to the core clock domain. Because the two ends of a link often run from independent references, an elastic buffer absorbs the small frequency offset between them, adding or deleting the filler symbols that the protocol reserves for this purpose, such as the SKP ordered sets of PCI Express. The protocol implementation topic develops this layer in detail.

Line Coding and Modulation

Raw data is rarely sent unmodified. Line coding conditions the bit stream so that it carries enough transitions for clock recovery, maintains the balanced average voltage that AC-coupled channels require, and often embeds control and alignment information. Early SerDes links used 8b/10b coding, which guarantees transitions and DC balance at the cost of 25 percent overhead. Higher-rate links favor lower-overhead schemes: 64b/66b, used in 10 Gigabit Ethernet, adds about 3 percent, and the 128b/130b coding of PCI Express generations 3 through 5 adds about 1.5 percent. Both rely on a scrambler rather than a lookup table to supply transition density, accepting a small probability of a long run in exchange for efficiency. The newest standards drop fixed line coding altogether in favor of scrambling plus a forward-error-correction layer, since raw bit-error rates at these speeds are no longer low enough to leave uncorrected.

Beyond coding, the modulation sets how many bits each symbol carries. Traditional links use two-level non-return-to-zero (NRZ) signaling, one bit per symbol. To push past the bandwidth limits of a channel, the fastest links adopt four-level pulse-amplitude modulation (PAM4), which encodes two bits per symbol and so doubles the data rate at a given baud rate. PCI Express 6.0 illustrates the benefit precisely: it doubles the lane rate from 32 to 64 GT/s while holding the symbol rate at 32 gigabaud, so the channel sees no new high-frequency demand. PAM4 buys that bandwidth at the price of signal integrity. Its three stacked eyes are each about one third the height of an NRZ eye, an intrinsic penalty of roughly 9.5 decibels in signal-to-noise ratio, so PAM4 demands stronger equalization, tighter noise and linearity control, careful management of level mismatch, and forward error correction as a mandatory part of the link rather than an option. Other level counts appear where they fit a specific channel: USB4 Version 2.0 reaches 80 Gb/s in each direction by adopting three-level PAM3 signaling on existing cables.

Mixed-Signal and DSP Receiver Architectures

Two receiver styles compete at the highest rates, and the choice shapes the entire transceiver. The mixed-signal receiver keeps equalization in the analog domain: a CTLE, sometimes a variable-gain amplifier, and a DFE feeding slicers that make the decisions directly. It is compact and power-efficient, and it remains the preferred choice for short, well-behaved channels and for links where energy per bit dominates the specification.

The alternative digitizes the waveform first. An analog-to-digital converter of roughly six to eight bits samples every symbol, and a digital signal processor applies feed-forward and decision-feedback equalization, and sometimes maximum-likelihood sequence estimation, in the digital domain. This architecture handles long, reflective, crosstalk-limited channels far better, adapts under software control, and gains directly from each new process node, which is why it became standard for 100 Gb/s per lane and beyond. It costs more power and area, and the converter itself must meet demanding linearity and timing requirements. Many product families now offer both, pairing a low-power analog receiver for short reaches with a DSP receiver for backplanes and cables. The receiver design topic compares these structures in depth.

Reach Classes and Channel Budgets

SerDes specifications are written against reach classes, because a transceiver that must cross a backplane is a different circuit from one that travels ten millimeters inside a package. The Optical Internetworking Forum (OIF) codifies this in its Common Electrical I/O (CEI) family, which defines classes from ultra-short and extra-short reach, used for die-to-die and die-to-optical-engine connections, through very short reach for chip-to-module hops, medium reach for chip-to-chip paths across a board, and long reach for backplanes and copper cables.

Insertion loss at the Nyquist frequency is the usual shorthand for where a link falls. A very short reach path may lose on the order of ten decibels, while a long-reach backplane or cable channel can exceed thirty. That difference decides almost everything downstream: the number of equalizer taps, whether the receiver is analog or DSP-based, the strength of the forward error correction, and the power the link consumes. At the shortest extreme, die-to-die interfaces such as the Universal Chiplet Interconnect Express standard abandon heavy equalization entirely, running many parallel, single-ended wires over a few millimeters of substrate, because within a package the parallel bus regains the advantage that SerDes took from it on a printed circuit board.

Link Training and Adaptation

No fixed set of equalizer settings suits every channel a product will meet, so modern links tune themselves. During bring-up, the two ends run a training sequence over a back channel: the receiver evaluates the waveform it is getting and asks the far transmitter to increase or decrease specific pre-cursor and post-cursor tap weights, while the transmitter acknowledges each change. PCI Express performs this as a multi-phase equalization procedure inside its link training state machine, negotiating each direction in turn before the link may operate at the higher rate. IEEE 802.3 backplane and copper-cable interfaces exchange dedicated training frames carrying coefficient update requests and status reports, preceded by auto-negotiation that settles on a common speed and feature set.

Adaptation does not stop when training ends. The receiver continues to adjust CTLE peaking, DFE tap weights, slicer offsets, and sampling phase in the background, usually with a least-mean-squares update driven by the error between the sampled voltage and the decided level. This tracking absorbs temperature and supply drift over hours of operation. When conditions change too far, or when the protocol requests a new speed, the link retrains. Instrumentation built into the receiver, such as an on-die eye monitor or the lane margining feature of PCI Express, lets software measure the remaining horizontal and vertical margin on a live link without disconnecting anything.

Data Rates and Protocols

SerDes underpins the dominant high-speed interfaces, and their roadmaps trace the rising rates that SerDes design must support. PCI Express illustrates the progression: 2.5 gigatransfers per second per lane in its first generation, then 5, 8, 16, and 32 GT/s through generation 5, all on NRZ signaling. Generation 6, published in 2022, reached 64 GT/s by switching to PAM4 and replacing 128b/130b coding with fixed-size flow control units protected by forward error correction and a cyclic redundancy check with retry. Generation 7, finalized in 2025, doubles again to 128 GT/s per lane, and PCI-SIG has announced work toward 256 GT/s.

Ethernet followed a parallel path on its electrical lanes. Lanes of 10.3125 Gb/s carrying 64b/66b blocks gave way to 25.78125 Gb/s NRZ lanes, then to 53.125 gigabaud PAM4 lanes carrying 106.25 Gb/s each, the generation the industry markets as 100G per lane and the OIF calls CEI-112G. The IEEE P802.3dj project, which defines 200 Gb/s, 400 Gb/s, 800 Gb/s, and 1.6 Tb/s Ethernet and is scheduled to complete in 2026, doubles the electrical lane again to 200 Gb/s of payload using PAM4 at about 106 gigabaud with 256b/257b transcoding and Reed-Solomon forward error correction. The OIF CEI-224G project extends the same approach to roughly 112 gigabaud, or 224 Gb/s per lane. Other interfaces occupy the rungs below: SATA settled at 6 Gb/s with 8b/10b coding, USB moved from 5 and 10 Gb/s lanes to 20 Gb/s per lane in USB4 and 80 Gb/s in each direction with PAM3 in USB4 Version 2.0, and the fabrics inside switches, routers, and processors use the same building blocks under proprietary framing.

These protocols differ in framing, training, and error handling, but they rest on a common SerDes foundation. The protocol layer scrambles and codes the data, negotiates equalizer settings during training, aligns lanes so that a multi-lane link presents data in order, applies the error-correction structure the standard requires, and manages low-power states. Treating the physical transceiver and the protocol logic as one design is what allows a link to reach its rated speed with margin.

Design Trade-offs

SerDes design balances speed, power, area, reach, and latency. More aggressive equalization and higher-order modulation extend the rate a given channel can support, but they add circuitry, raise power, and demand tighter control of jitter and noise. Higher baud rates shrink the unit interval, so timing budgets tighten while the channel's frequency-dependent loss grows, pushing more effort onto equalization and clean clock recovery. Energy per bit is the figure of merit that captures the tension, and it spans roughly an order of magnitude between the shortest die-to-die links and long-reach backplane links, which matters enormously in a switch chip carrying hundreds of lanes.

Forward error correction illustrates the same tension from another direction. It buys several decibels of effective margin for a modest area cost, but it adds latency and cannot be switched off once a standard assumes it, which is why latency-sensitive fabrics prefer the lightest code that meets the target error rate. Choosing NRZ or PAM4, allocating gain between transmitter and receiver equalizers, selecting an analog or DSP receiver, and deciding how much coding to spend are decisions made together through link budget analysis and statistical eye simulation, which weigh loss, reflections, crosstalk, and jitter as a single system rather than as separate specifications.

Verification and Compliance

Two error-rate conventions coexist. Links without forward error correction specify a raw bit-error ratio, classically one error in ten to the twelfth bits, which is already too rare to observe directly in a short test. Links with error correction instead specify a pre-correction error ratio, on the order of one error in ten thousand bits for Reed-Solomon-protected Ethernet lanes, and rely on the code to deliver a far lower rate to the protocol layer. Either way, verification depends on extrapolation rather than exhaustive measurement, which is why statistical methods dominate. Standards bodies encode this in figures of merit such as the channel operating margin used by IEEE 802.3 to qualify a channel without simulating every bit.

On the bench, a pattern generator drives calibrated stress, a high-bandwidth oscilloscope or error detector captures the result, and software applies the reference receiver equalization the standard specifies before the eye is measured. Pseudo-random patterns exercise worst-case run lengths and transition density, and jitter decomposition separates random from deterministic contributions so that a measured eye can be projected to the target error rate. Loopback modes, built-in self-test, and on-die eye monitors extend the same checks into systems where no probe can reach the signal. Compliance testing covers the procedures each standard prescribes.

Conclusion

SerDes architecture is the discipline of getting a single differential pair to carry what once required a bus, and then getting it to do so again at twice the rate. Every generation resolves the same tension between what the channel destroys and what the transceiver can rebuild, and each answer has been a shift in where the intelligence sits: from raw drive strength to transmitter pre-emphasis, then to receiver equalization, then to digital signal processing and coding. The topics in this category develop each part of the link in depth, from the transmitter that launches the signal and the receiver that recovers it, through the clock and data recovery that times every decision, to the protocol implementation that turns a stream of symbols into a working interface.

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