Electronics Guide

Subcategories

Why Serialize

A wide parallel bus seems like the straightforward way to move many bits, but it does not scale to high speed. Each parallel wire must arrive at the receiver aligned in time, and at multi-gigabit rates the unavoidable differences in trace length, via count, and coupling spread those arrivals apart. This skew, together with the crosstalk and simultaneous-switching noise that a bundle of parallel signals generates, sets a practical ceiling on how fast a parallel bus can run. SerDes sidesteps the problem by sending the data as a single high-rate stream over one differential pair, so there is no inter-wire skew to manage and the clock can be recovered from the data itself rather than carried on a separate, ever-drifting line.

The payoff is fewer pins, fewer board traces, smaller and cheaper connectors, and lower electromagnetic emissions, all while the per-lane data rate climbs into the tens of gigabits per second. A link that once needed dozens of synchronized parallel wires now needs one or a few differential lanes, and bandwidth is scaled by adding lanes in parallel rather than by clocking a wide bus faster. This is why nearly every modern high-speed interface, from PCI Express and USB to SATA and Ethernet, is built on SerDes lanes.

The SerDes Datapath

A SerDes link is organized as a transmit chain and a receive chain joined by a channel of board traces, connectors, vias, and cables. Each stage exists to launch a clean signal, survive the channel, and reconstruct the original bits.

Transmit Path

On the transmit side, a phase-locked loop multiplies a low-frequency reference clock up to the bit rate. Parallel data from the core logic is encoded for the line, then the serializer, typically a tree of multiplexers, shifts those bits out one at a time at full rate. A differential output driver launches the stream into the channel, and a feed-forward equalizer pre-distorts the waveform, emphasizing the fast edges and de-emphasizing the steady levels so that the signal arrives with a flatter response after the channel attenuates its high-frequency content.

Receive Path

At the far end, the signal arrives attenuated and smeared by intersymbol interference. The receiver terminates the line to its characteristic impedance to suppress reflections, then equalizes the waveform to reopen the eye. A continuous-time linear equalizer (CTLE) restores high-frequency gain, and a decision-feedback equalizer (DFE) cancels the residual trailing interference using the receiver's own past decisions, a structure that removes ISI without amplifying noise. A slicer then decides each symbol against a threshold, and a deserializer reassembles the recovered bits into a parallel word for the core logic.

Clock and Data Recovery

Because SerDes sends no separate clock alongside the data, the receiver must extract its sampling clock from the transitions in the stream itself. The clock and data recovery (CDR) circuit, usually a phase-locked or phase-interpolator loop, locks onto those edges and positions the sampling instant at the center of each symbol, where the eye is most open. Reliable CDR depends on the data containing frequent transitions, which is one reason line coding matters: long runs of identical bits would starve the loop of the edges it needs to stay locked.

Line Coding and Modulation

Raw data is rarely sent unmodified. Line coding conditions the bit stream so that it carries enough transitions for clock recovery, maintains a balanced average voltage (DC balance) that suits AC-coupled channels, and often embeds control and alignment information. Early SerDes links used 8b/10b coding, which guarantees transitions and DC balance at the cost of 25 percent overhead. Higher-rate links favor lower-overhead schemes such as 64b/66b, used in 10 Gigabit Ethernet at roughly 3 percent overhead, and the 128b/130b coding of PCI Express generations 3 through 5 at about 1.5 percent. The newest standards replace fixed line coding with scrambling plus a forward-error-correction layer that protects the link as raw bit-error rates rise.

Beyond coding, the choice of modulation sets how many bits each symbol carries. Traditional links use two-level non-return-to-zero (NRZ) signaling, one bit per symbol. To push past the bandwidth limits of the channel, the fastest links adopt four-level pulse-amplitude modulation (PAM4), which encodes two bits per symbol and so doubles the data rate at a given baud rate. PAM4 buys bandwidth at the price of signal integrity: its three eyes are each only about a third the height of an NRZ eye, so it demands stronger equalization, lower noise, and mandatory forward error correction.

Data Rates and Protocols

SerDes underpins the dominant high-speed interfaces, and their roadmaps trace the rising data rates that SerDes design must support. PCI Express illustrates the progression: 2.5 gigatransfers per second per lane in its first generation, doubling through 8, 16, and 32 GT/s in generations 3 through 5 on NRZ signaling, then 64 GT/s in generation 6 by switching to PAM4. Ethernet electrical lanes followed a parallel path, moving from 28 Gbaud NRZ to 56 Gbaud PAM4 for 112 Gb/s per lane, with 112 Gbaud PAM4 carrying 224 Gb/s per lane in the most recent optical-interface forum specifications. USB, SATA, and the SerDes links inside switches, routers, and processor fabrics share the same building blocks.

These protocols differ in framing, link training, and error handling, but they rest on a common SerDes foundation. The protocol layer scrambles and codes the data, negotiates equalizer settings during link training, aligns lanes so that a multi-lane link presents data in order, and inserts the framing and error-correction structure the standard requires. Treating the physical SerDes and the protocol logic as one design is what allows a link to reach its rated speed with margin.

Design Trade-offs

SerDes design is a balance among speed, power, area, and reach. More aggressive equalization and higher-order modulation extend the data rate a given channel can support, but they add circuitry, raise power consumption, and demand tighter control of jitter and noise. Higher baud rates shrink the unit interval, so timing budgets tighten and the channel's frequency-dependent loss grows, pushing more of the design effort onto equalization and clean clock recovery. Choosing NRZ or PAM4, allocating gain between transmitter and receiver equalizers, and deciding how much forward error correction to spend are decisions made together through link-budget analysis and statistical eye simulation, which weigh loss, reflections, crosstalk, and jitter as a single system.

The topics in this category develop each part of the link in depth, from the transmitter that launches the signal and the receiver that recovers it, through the clock and data recovery that times every decision, to the protocol implementation that turns a stream of bits into a working interface.