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When a Wire Becomes a Transmission Line

At low frequencies an interconnect can be treated as an ideal node: the voltage is effectively the same everywhere along it at any instant, and a lumped resistor, capacitor, or inductor captures its behavior. This approximation holds only while the physical length of the conductor is short compared with the wavelength of the signal, or equivalently while the time for a signal to travel from one end to the other is short compared with the signal's rise time. As edge rates sharpen, that condition eventually fails, the voltage along the conductor varies from point to point, and the interconnect must be analyzed as a distributed structure carrying a traveling wave. Power lines sit at the other extreme: a 60 Hz wave on an overhead line has a wavelength of nearly 5,000 km, and Transmission and Distribution Lines applies the same distributed equations to lines hundreds of kilometers long.

A widely used screening rule treats an interconnect as a transmission line once its one-way propagation delay exceeds a small fraction of the signal's rise or fall time. One-sixth is the most commonly cited threshold, though published values range from roughly one-half down to one-tenth or tighter depending on how much of the noise budget the designer is willing to spend on reflections. The rule flags nets for analysis rather than drawing a precise boundary; what ultimately matters is whether the resulting reflections and distortion stay within the receiver's margins.

The numbers are sobering in practice. A stripline in ordinary FR-4 propagates at roughly 170 picoseconds per inch, so a 500-picosecond edge occupies about three inches of trace, and the one-sixth rule places the threshold near half an inch. Sharpen the edge to 100 picoseconds and the threshold falls to about a tenth of an inch—shorter than many connector pins, package traces, and via structures. Because edge rates have grown far faster than clock frequencies, nets that switch at modest data rates still routinely carry edges sharp enough to demand transmission-line treatment, and a designer who classifies nets by clock frequency alone will miss them.

The Distributed Model and Characteristic Impedance

A transmission line is modeled as a cascade of infinitesimal segments, each contributing series resistance and inductance and shunt conductance and capacitance—the distributed R, L, G, and C parameters per unit length. The telegrapher's equations, a pair of coupled partial differential equations derived from this ladder, describe how voltage and current waves propagate along the structure. For a line whose loss is small enough to neglect, the analysis simplifies dramatically and yields two defining quantities.

The characteristic impedance is the ratio of voltage to current for a wave traveling in one direction along the line. In the general case it is frequency dependent:

Z₀ = √((R + jωL) / (G + jωC))

Above the frequency where the inductive reactance dominates the series resistance, which for typical board geometries occurs well below a gigahertz, this converges on the familiar lossless form:

Z₀ = √(L / C)

Characteristic impedance depends only on the line's cross-sectional geometry and the surrounding dielectric, not on its length, and it represents the instantaneous impedance a launched edge encounters before any reflection returns. A driver charging a long 50-ohm line therefore sees a 50-ohm load during the flight time, whatever sits at the far end. Two practical corollaries follow from the same relations: the characteristic impedance equals the one-way delay divided by the total capacitance of the line, and equally the total inductance divided by that delay. These identities make impedance measurable from a capacitance meter and a delay measurement, and they explain why any feature that adds capacitance without adding inductance—a via pad, a test point, an unloaded connector footprint—pulls the local impedance down.

Geometry sets the value. Widening a trace or thinning the dielectric beneath it raises capacitance and lowers impedance; narrowing the trace or moving the reference plane farther away raises impedance. As a rough guide, a 50-ohm microstrip on FR-4 is about one and a half to two times as wide as the dielectric is thick, and the same trace over the same dielectric will measure a lower impedance if it is buried as a stripline, because it then couples to reference planes on both sides.

Propagation Velocity and Delay

The velocity of the wave is set by the same per-unit-length quantities that fix the impedance:

v = 1 / √(L C)

In a uniform, non-magnetic dielectric this reduces to v = c / √ε_r, where c is the speed of light and ε_r is the relative permittivity of the medium. A signal therefore travels more slowly through a denser dielectric. Expressed as delay per unit length, the free-space figure of roughly 85 picoseconds per inch—about 3.3 picoseconds per millimeter—scales with the square root of the effective permittivity.

The distinction between microstrip and stripline follows directly. A microstrip on the outer layer shares part of its field with the air above the board, so it sees an effective permittivity lower than that of the laminate and propagates at roughly 140 to 150 picoseconds per inch on FR-4. A stripline buried between planes in the same material is fully embedded in the dielectric and runs closer to 170 to 180 picoseconds per inch. Mixing the two layer types within a length-matched bus is a classic source of timing error, because equal physical lengths on different layers are not equal delays.

Two further effects complicate delay in real boards. Laminate permittivity falls slowly with frequency, so a broadband edge disperses as its components travel at slightly different speeds; accurate simulation therefore uses a causal, frequency-dependent dielectric model rather than a single value. And because woven-glass laminates are inhomogeneous at the scale of a trace, the local permittivity depends on where the conductor happens to sit: glass has a higher permittivity than the resin around it, so a trace running above a glass bundle propagates measurably more slowly than one running above a resin-rich window in the weave. On a differential pair this fiber-weave effect converts into skew between the two members, which is why designers rotate the board on the panel, route at a small angle to the weave, or specify spread-glass styles on the fastest links.

Standard Impedances and Why They Are Used

Interconnects are designed to a small set of conventional impedance targets so that drivers, receivers, cables, and connectors can be matched to one another. Single-ended radio-frequency and high-speed digital interconnects commonly target 50 ohms. The value is a deliberate compromise: for air-dielectric coaxial geometry, power handling peaks near 30 ohms while attenuation reaches its minimum near 77 ohms, and 50 ohms splits the difference in favor of voltage handling. Video and cable-television coaxial systems standardized instead on 75 ohms, close to the minimum-loss value, because receiving systems care about attenuation rather than transmitted power.

Differential interfaces specify the impedance seen between the two members of the pair, and the targets vary more than engineers often expect. USB 2.0 high-speed calls for 90 ohms differential. SATA and general-purpose LVDS links use 100 ohms, as do the twisted pairs of Ethernet cabling. PCI Express specified 100 ohms in its first generation and moved to 85 ohms from the second generation onward, with the tolerance tightening from roughly twenty percent to fifteen percent along the way. USB 3.x SuperSpeed splits the difference between media, targeting 85 ohms on board and package traces but 90 ohms in the cable. Parallel memory buses take yet another approach, driving single-ended nets at roughly 40 to 50 ohms so that on-die termination can match them without excessive current. The lesson is not that any one number is correct but that impedance targets belong to the specification, evolve between generations, and must be read rather than assumed.

Holding the chosen impedance is the central goal of controlled-impedance design. The value is set by trace width, dielectric thickness, copper weight, and the permittivity of the laminate, and it is verified in fabrication on a test coupon against a tolerance that is typically about ten percent, with five to seven percent available at added cost and yield risk. Where the impedance departs from its target—at a connector, a via, a stub, or a layer transition—a discontinuity forms that launches a reflection, which is why impedance control, termination, and reflection management are treated together throughout high-speed design.

Differential Pairs and Coupled Lines

When two lines run close enough to couple, a single characteristic impedance no longer describes them. The pair supports two propagation modes: the odd mode, in which the conductors carry equal and opposite voltages, and the even mode, in which they carry equal voltages of the same polarity. Each mode has its own impedance, and the quantities quoted in specifications derive from them:

Z_diff = 2 × Z_odd and Z_common = Z_even / 2

The odd-mode impedance is not the impedance the same trace would have in isolation. Coupling between the conductors lowers the odd-mode impedance and raises the even-mode impedance, and the effect grows as the pair is brought closer together. A 100-ohm differential pair is therefore built from traces whose uncoupled single-ended impedance is somewhat above 50 ohms, and tightening the spacing without widening the traces will drive the differential impedance below target. Treating a differential pair as two independent 50-ohm lines is one of the most common errors in high-speed layout, and a field solver that models the coupled cross section is the reliable remedy.

The two modes matter for termination as well as for geometry. A single resistor across the pair terminates the differential mode but presents no path for common-mode energy; splitting that resistor into two halves with a capacitor from the midpoint to ground terminates both. Because real pairs are never perfectly balanced, some differential energy converts to common mode at every asymmetry—a length mismatch, a via that breaks symmetry, a connector pinout—and common-mode current on an exiting cable is a leading cause of radiated emissions failures.

Reflections and Termination

When a traveling wave meets a change in impedance, part of its energy reflects back toward the source. The fraction that reflects is the reflection coefficient:

Γ = (Z_L − Z₀) / (Z_L + Z₀)

The coefficient is zero only when the load impedance Z_L equals the line impedance Z₀. An unterminated open end reflects the full wave with the same polarity and momentarily doubles the voltage there; a short reflects an inverted wave that cancels the incident one. Because the reflected wave re-reflects at the source unless the driver is also matched, energy bounces back and forth, decaying by the product of the two reflection coefficients on each round trip. The result at the receiver is overshoot, undershoot, ringing, stair-stepped settling, and intersymbol interference that erode both timing and voltage margins.

Termination suppresses reflections by presenting a matched impedance somewhere in the path. Series termination places a resistor at the driver whose value, added to the driver's own output impedance, equals the line impedance; a half-amplitude wave travels down the line, doubles to full amplitude at the high-impedance receiver, and the returning wave is absorbed at the matched source. It costs no static power and suits point-to-point nets, but it forbids receivers along the middle of the line, where the half-amplitude wave would be sampled. Parallel termination places a resistor equal to the line impedance at the load, giving clean settling and supporting multiple loads at the cost of continuous direct current. Thevenin termination substitutes a resistor pair to a supply rail and ground whose parallel combination equals the line impedance, setting a bias point as well as a match. AC termination adds a series capacitor to block the direct current at the price of a time constant that must be chosen against the data pattern. Differential termination matches the pair as described above, and modern high-speed devices increasingly integrate on-die termination, which eliminates the stub between a discrete resistor and the receiver pad and allows the value to be calibrated and switched under controller command.

Discontinuities in Real Interconnects

A uniform line is an idealization. Real channels pass through vias, connectors, package escapes, breakout regions, and layer transitions, and each one perturbs the impedance. The severity of a discontinuity depends on its electrical size: a feature much shorter than the signal's rise time behaves as a small lumped capacitance or inductance and produces a modest, localized reflection, while a feature comparable to the rise time reflects strongly and can resonate.

Vias illustrate the point. The barrel adds inductance and the pads and antipads add capacitance, so a via can be tuned by adjusting antipad diameter and removing unused pads. More damaging is the unused length of barrel below the exit layer: this stub behaves as an open-circuited line and resonates when its length approaches a quarter wavelength, cutting a deep notch into the channel's insertion loss. Back-drilling the stub away, or routing the signal on layers that minimize it, is standard practice above a few gigabits per second.

Return-path continuity is equally important and easier to overlook. The return current flows in the reference plane directly beneath the signal, and a trace that crosses a plane split or changes reference planes forces that current to detour. The detour adds inductance, distorts the waveform, and radiates. Stitching vias beside a signal via that changes between planes of the same net, or stitching capacitors where the planes carry different voltages, restore the path. Connectors and package interfaces deserve the same scrutiny, since the impedance of a mated pair depends on the footprint and the surrounding copper as much as on the connector itself.

Loss, Dispersion, and Channel Budget

Real lines attenuate as well as delay. Two mechanisms dominate on printed circuit boards. Series resistance grows with frequency as the skin effect confines current to a thin layer at the conductor surface: the skin depth in copper is roughly 2.1 micrometers at 1 gigahertz and falls with the square root of frequency, so at multi-gigahertz rates only a small fraction of a standard copper foil actually carries current. Conductor attenuation therefore rises approximately with the square root of frequency. Dielectric loss, by contrast, rises roughly in proportion to frequency and to the laminate's dissipation factor, so material choice dominates the budget on long channels.

The spread among laminates is large. Standard FR-4 has a dissipation factor near 0.02, whereas engineered low-loss materials reach far lower values—Rogers RO4350B is specified at 0.0037 at 10 gigahertz and Panasonic Megtron 6 at roughly 0.002—which translates directly into a several-fold reduction in dielectric attenuation over the same length. Copper surface roughness adds a third term: the rough foil that promotes adhesion lengthens the current path within the skin layer, and very-low-profile and hyper-very-low-profile foils are specified on demanding designs to recover the loss.

Because these mechanisms attenuate the high-frequency content of an edge more than its low-frequency content, a channel does not merely shrink the signal; it slows the edges, spreads each bit into its neighbors, and closes the eye. That is the origin of intersymbol interference and the reason multi-gigabit links pair careful impedance control with transmitter pre-emphasis and receiver equalization. Managing characteristic impedance, propagation delay, reflections, and loss together is what allows a modern link to carry tens of gigabits per second reliably.

Measuring and Verifying a Line

Two complementary instruments dominate transmission line characterization. Time-domain reflectometry launches a fast step into the line and records the reflections, producing an impedance profile against distance that localizes each discontinuity; its spatial resolution is limited by the rise time of the reflected step, so a slow step blurs closely spaced features together. A vector network analyzer instead sweeps frequency and measures scattering parameters, yielding insertion loss, return loss, and—on a four-port measurement of a differential pair—the mixed-mode terms that quantify mode conversion. The two views are mathematically related, and modern instruments transform freely between them.

Fabricators verify controlled impedance on a coupon placed in the panel border, measuring representative traces from each impedance-controlled layer with time-domain reflectometry and reporting the results against the specified tolerance. Before any board is built, two-dimensional field solvers compute impedance from the cross section, three-dimensional solvers handle vias and connectors where the geometry is not uniform along the line, and channel simulation combines the extracted models with driver and receiver behavioral models to predict the eye at the receiver. Correlating measurement with simulation on each new stackup is what turns these tools from estimates into a dependable design flow.

About This Category

The topics gathered here develop the subject from theory to practice. Transmission line theory establishes the distributed model and the equations that govern wave propagation; transmission line types survey the physical structures that implement it; impedance control covers the stackup, geometry, and tolerance work required to hit a target value in manufacturing; and termination strategies close the loop by matching the line to its source and load. Together they supply the vocabulary and the quantitative tools on which the rest of signal integrity depends.

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