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Where Reflections Come From

A wave traveling along an interconnect carries a fixed ratio of voltage to current set by the characteristic impedance of the structure it occupies. For a line whose series resistance and dielectric conductance are small compared with its reactive terms—the usual case for a printed-circuit trace above a few megahertz—that impedance reduces to Z₀ = √(L / C), where L and C are the inductance and capacitance per unit length. Because both quantities follow from the geometry of the conductor and its reference plane and from the surrounding dielectric, the characteristic impedance depends on cross section rather than on length. A wave entering a region whose geometry differs from the one it just left must satisfy a different voltage-to-current ratio, and the only way to reconcile the two is to send part of the energy back.

It follows that every physical transition is a potential reflection site. The far-end load is the most obvious: a high-impedance CMOS receiver input is close to an open circuit and reflects almost the entire incident wave. The driver is the second: whatever returns from the far end meets the output impedance of the source and reflects again. Between the two ends, a working board offers many smaller perturbations. A signal via adds capacitance at its pads and inductance along its barrel, and the unused portion of the barrel below the exit layer forms a resonant stub. Connectors present their own impedance profile and, where ground contacts are sparse, disturb the return path. Surface-mount pads for series capacitors sit on widened copper that drops the local impedance, while a trace necking down to escape a fine-pitch ball-grid array raises it. Branches and unterminated spurs load the main line. Even a plain change of layer alters the reference geometry.

The return path deserves particular emphasis, because the impedance a wave experiences belongs to the loop, not to the signal conductor alone. Current that flows out along a trace must flow back through the nearest reference plane, and above a few megahertz it does so directly beneath the trace, where the loop inductance is lowest. A slot, a plane split, or an antipad field that forces the return current to detour raises the loop inductance abruptly and produces a reflection exactly as a change in trace width would—while also converting the detour into an efficient radiator. Return-path breaks are therefore among the most damaging discontinuities a design can contain, and among the easiest to overlook, because nothing in the signal-layer artwork reveals them.

Finally, the nominal impedance itself is not exact. Controlled-impedance traces are ordinarily specified to a tolerance of about ten percent, tightened to five percent only at added cost, so a nominally 50-ohm line may arrive from the fabricator anywhere within a several-ohm band. A reflection budget that assumes perfect impedance leaves no room for the variation that fabrication guarantees.

The Reflection Coefficient

The fraction of an incident voltage wave that reflects at a discontinuity is the reflection coefficient, conventionally written with the Greek letter gamma:

Γ = (Z_L − Z₀) / (Z_L + Z₀)

Here Z₀ is the characteristic impedance of the line the wave is leaving and Z_L is the impedance it encounters. For a purely resistive passive load the coefficient is real and ranges from −1 to +1; a load with reactance makes the coefficient complex, and passivity limits only its magnitude, which cannot exceed one. When Z_L equals Z₀ the numerator vanishes, no energy turns back, and the line is matched. An open circuit drives Z_L toward infinity, giving a coefficient of +1 and a reflected wave in phase with the incident one, so the voltage at the open end doubles. A short circuit gives a coefficient of −1 and an inverted reflection that drives the voltage there to zero while the currents add.

A few worked values make the scale concrete. A load at twice the line impedance reflects one-third of the wave in phase; a load at half the line impedance reflects one-third inverted; a 60-ohm section inserted into a 50-ohm channel reflects about nine percent. Because reflected power scales as the square of the coefficient, that one-third voltage reflection returns only about eleven percent of the incident power, and the nine-percent reflection returns under one percent. The wave that continues past the discontinuity carries the balance, and its amplitude at the junction is (1 + Γ) times the incident amplitude, which is why the voltage at an open end reaches twice the launched value rather than zero. The radio-frequency expressions of the same quantity, return loss and the voltage standing wave ratio, are developed in Impedance Matching; the only one used below is return loss, −20 log₁₀|Γ|, under which a coefficient of 0.1 corresponds to 20 decibels and larger values are better.

The sign of the coefficient tells the designer what kind of feature caused the reflection. An impedance higher than the line reflects with the same polarity as the incident wave; an impedance lower than the line reflects inverted. For the reactive discontinuities that dominate a printed-circuit channel, the mapping is direct: excess series inductance—a necked-down trace, a via barrel, a connector pin, a bond wire—raises the instantaneous impedance and produces a positive-going reflection, while excess shunt capacitance—a via pad, a component land, a receiver input, a widened area over a plane—lowers it and produces a negative-going one. Reading a time-domain reflectometer trace is largely a matter of applying that rule to each bump and dip in sequence.

Reflections occur at the source as well as the load, governed by the same expression with the driver output impedance in place of Z_L. That second coefficient is what turns a single reflection into a sustained disturbance.

Multiple Reflections and Settling Time

A launched edge that meets a mismatch at both ends does not reflect once; it bounces. Each round trip multiplies the surviving amplitude by the product of the source and load reflection coefficients, so the disturbance decays geometrically at a rate set by how badly the two ends are mismatched. Engineers track this bookkeeping with a lattice diagram, sometimes called a bounce diagram, which plots position against time and follows each wave as it crosses the line, reflects, and crosses back.

A numerical example shows the scale of the problem. Consider a driver with a 10-ohm output impedance launching a step into a 50-ohm line whose far end terminates in a high-impedance receiver. The driver and the line form a divider, so the launched wave is about 83 percent of the full swing. At the open far end the coefficient is +1 and the wave doubles, so the receiver first sees roughly 167 percent of the final level—a 67 percent overshoot. The reflection returns to the source, where the coefficient is (10 − 50) / (10 + 50), or about −0.67, and comes back inverted. The receiver voltage then falls to about 56 percent of the final level, rises to about 130 percent, falls to about 80 percent, and so on, the error shrinking by a third on each round trip. Six arrivals pass before the waveform settles within ten percent of its final value, and on a line with a 1-nanosecond one-way delay the sixth arrival lands 11 nanoseconds after the first edge left the driver.

The same arithmetic shows how effective a single component can be. Adding a 40-ohm resistor in series with that driver raises the source impedance to 50 ohms, which drives the source reflection coefficient to zero. The launched wave is now half amplitude, doubles at the open far end to full amplitude, and the returning reflection is absorbed rather than sent back out. The line settles after one round trip instead of six, at the cost of a receiver that sees a half-amplitude plateau for the duration of that round trip.

When Reflections Matter: Electrical Length

Reflections always occur at a mismatch, but they degrade a digital signal only when the round-trip travel time is a significant fraction of the signal edge. If an interconnect is electrically short, the reflected energy returns and settles well within the rising edge, and the net effect is a small, fast perturbation that the receiver never resolves as a separate event; the line behaves as a lumped load. As the interconnect lengthens, the round trip eventually exceeds the rise time, reflected edges arrive after the receiver has begun responding, and the trace must be treated as a transmission line with controlled impedance and deliberate termination.

The usual rule of thumb compares the one-way propagation delay of the trace with the signal rise or fall time, whichever is faster, and calls for transmission-line treatment once the delay exceeds a small fraction of that edge. One-sixth is the most widely quoted threshold, but published values range from roughly one-third down to one-twentieth, because the tolerable amount of reflection-induced distortion depends on the noise budget of the specific design. The rule is therefore a screen that flags nets for analysis, not a verdict on any one of them; what ultimately matters is whether the resulting overshoot, ringing, and settling time stay within the receiver's margins.

The arithmetic is easy to carry out on any net. A printed-circuit trace propagates at roughly 150 picoseconds per inch, faster on an exposed microstrip whose fields share the air above the board and slower in stripline buried entirely in dielectric. A driver with a 500-picosecond edge therefore reaches the one-sixth threshold at a little over half an inch, and a driver with a 100-picosecond edge reaches it at little more than a tenth of an inch—a distance comparable to the package escape itself, which is why on-die and in-package structures dominate the reflection budget of the fastest interfaces. Because edge rates have improved far faster than clock frequencies, many nets that switch at modest data rates still carry edges sharp enough to require this treatment, and a part substitution that brings a faster driver into an unchanged layout can turn a previously quiet net into a marginal one.

How Reflections Degrade Signal Quality

Once reflections become significant, they manifest as several familiar signal-quality defects:

• Overshoot and undershoot. A reflection that adds to the incident wave drives the voltage above the supply rail or below ground. Large excursions forward-bias the clamp diodes on a receiver input, injecting current into the rails, and sustained operation beyond a device's absolute-maximum ratings degrades gate oxide and shortens service life.
• Ringing. Successive reflections bouncing between the ends of a poorly terminated line produce a decaying oscillation around the final level. Ringing that crosses the receiver's switching thresholds is read as a genuine transition, so a single edge can be counted as several.
• Settling delay. A signal that rings must wait for the oscillation to decay inside the valid logic band before it can be sampled, which consumes setup margin directly and is often the binding constraint on how fast a bus may be clocked.
• Non-monotonic edges. Reflections arriving partway up a transition create plateaus or reversals in the threshold region. Where a clock or an asynchronous input passes through that region more than once, the receiver may double-clock, and the failure is intermittent because it depends on the exact arrival time of the reflected energy.
• Intersymbol interference. On a fast serial link, residual reflections from one bit that have not fully decayed overlap the bits that follow, shifting their levels and their crossing times. The result is data-dependent jitter and a closed eye, and because the effect depends on the preceding bit pattern, it appears only with certain traffic.
• Rise-time degradation. A capacitive discontinuity acts as a low-pass element, so a channel that accumulates several of them delivers an edge slower than the one the driver produced. A slower edge spends longer in the threshold region, where noise and crosstalk translate directly into timing uncertainty.

These defects rarely appear alone, and they compete for the same margin as crosstalk, loss, and power-supply noise. A link budget that allocates margin to each impairment separately is the practical way to decide how much reflection a design can tolerate.

Termination Strategies

Reflections are controlled by arranging impedances so that the reflection coefficient approaches zero at the points that matter. Two placements do most of the work, and each leaves a distinct signature on the waveform. Series, or source, termination raises the effective output impedance of the driver to the line impedance, so the far-end reflection is absorbed when it returns rather than sent back out; the receiver sees a half-amplitude plateau for one round trip before the open-end reflection completes the swing, which is why the scheme suits a single receiver at the end of the line and not loads tapped along it. Parallel, or end, termination places the matching impedance at the receiver, absorbing the incident wave on arrival so that no reflection forms and every point on the line carries full amplitude from the first instant, at the cost of current that flows whenever the line rests at a level away from the termination reference.

The remaining schemes extend those two ideas. Thevenin, or split, termination realizes the parallel match with one resistor to each rail and so also fixes the level an undriven line rests at. AC termination places a capacitor in series with the terminating resistor, so the resistor damps the edges while the capacitor blocks the static current, at the price of a time constant that must be matched to the round-trip delay. Differential termination puts a resistor across a balanced pair, where any imbalance between its halves converts part of the differential signal into a common-mode component that the pair no longer cancels. On-die termination moves the resistor onto the silicon, removing the package stub that an external part cannot avoid and allowing the value to change with the state of the bus. Impedance Matching develops each scheme in full, including the standard resistor values, the choice of termination rail, and the calibration that on-die elements require; what concerns the waveform is only which reflection each scheme removes and which it leaves behind.

The right choice follows from the topology, the number and placement of loads, the available power budget, the required voltage swing, and whether the driver impedance is well controlled. Point-to-point nets on a power-constrained board favor series termination; multidrop buses and any net whose intermediate voltage must be valid favor parallel termination; and the most demanding links are terminated at both ends, trading power for the lowest residual reflection and the most forgiving timing. No termination, however, absorbs a reflection that forms between the two ends rather than at them, which is why topology and layout belong to the same decision.

Topology, Stubs, and Layout

Termination cannot rescue a topology that creates reflections faster than a resistor can absorb them, so the routing plan is part of the reflection strategy. A point-to-point net between one driver and one receiver is the easiest case, because it has exactly two ends to match. Every branch added to that net creates a junction, and a junction is a discontinuity by construction: where a line splits into two branches of equal impedance, the incident wave sees the two in parallel, so a 50-ohm line meeting two 50-ohm branches encounters 25 ohms and reflects about one-third of the wave inverted. Balanced T and star topologies mitigate this by matching branch lengths so that reflections arrive together and by sizing the branch impedances deliberately, but the junction reflection never disappears entirely.

Daisy-chain and fly-by topologies avoid the junction by running one continuous line past each load and terminating it once at the far end, accepting a skew between loads that the receiving devices must compensate. Memory interfaces illustrate the progression: the branched command and address routing of earlier DDR generations gave way to a fly-by arrangement from DDR3 onward, with per-device write leveling added to absorb the resulting skew. The lesson generalizes—a topology that keeps the signal on one continuous, terminated line is easier to make quiet than one that relies on cancelation among branches.

Stubs are the other recurring hazard. A short spur off the main line behaves as a lumped capacitance and merely rounds the edge, but once its round-trip delay approaches the rise time it reflects a distinct wave, and at a quarter wavelength it resonates and can null the signal outright. The unused barrel of a through-hole via is the most common example, which is why high-speed designs back-drill the unused portion away, choose exit layers that leave the shortest possible stub, or use blind and buried vias. Test points, unpopulated footprints, and connector fingers deserve the same scrutiny.

The remaining layout work is a matter of removing avoidable impedance changes: keeping trace width and dielectric spacing constant along a net, stitching reference vias beside every layer transition so the return current follows the signal, keeping serpentine delay-matching sections spaced far enough apart that the coupling between adjacent segments does not lower the local impedance, and avoiding routes that cross plane splits. None of these measures is expensive at layout time, and all of them are expensive to retrofit.

Measuring and Simulating Reflections

Time-domain reflectometry is the natural instrument for reflections. It launches a fast step into the channel and displays the returning energy against time, and because time converts to distance through the propagation velocity, each bump and dip appears at the physical location of the feature that caused it. The instrument reads impedance directly, so a designer can see a connector as a dip, a via as a capacitive notch, and a necked trace as a rise, then compare the measured profile against the intended stackup. Two cautions apply. The spatial resolution is limited by the system rise time—features closer together than roughly half an edge length merge into one—so an instrument slower than the signals in question will understate the damage. And the reflection from the first discontinuity alters what reaches the second, so the amplitudes further along the trace must be interpreted with that shadowing in mind.

The frequency-domain view is complementary. A vector network analyzer sweeps frequency and reports the input reflection as the scattering parameter S₁₁, which most high-speed standards constrain with a published return-loss mask. The two views are mathematically equivalent, and modern instruments transform between them, but the frequency domain is the one in which compliance is usually specified and in which a periodic structure—a repeating via pattern, an evenly spaced set of stubs—reveals itself as a resonant notch that the time-domain trace obscures.

Simulation carries the analysis before hardware exists. Pre-layout studies use behavioral driver and receiver models, most commonly in IBIS form, together with an estimated interconnect to choose a topology and a termination scheme while the choice is still free. Post-layout studies replace the estimate with S-parameter models extracted from a field solver for the vias, connectors, and package transitions, then run time-domain simulation to produce the waveform a receiver will actually see. For multi-gigabit serial links, statistical channel analysis extends this to the millions of bits needed to predict an eye contour at a low bit-error ratio, which no transient simulation could reach directly. Measurement then closes the loop, confirming that overshoot, ringing, and settling stay inside the receiver's voltage and timing specifications on real hardware rather than only in the model.

About This Category

Sound reflection control begins with a controlled-impedance stackup, continues through a layout that removes abrupt discontinuities at vias, connectors, branches, and stubs, and concludes with a termination scheme matched to the topology and verified against the receiver's margins. Pre-layout simulation predicts the reflections a candidate channel will produce, post-layout extraction refines the prediction with the real geometry, and measurement on fabricated hardware confirms that overshoot, ringing, and settling stay within specification. The topics gathered here develop each of these ideas in depth. Reflection mechanisms establish the underlying physics and the arithmetic of repeated bounces; discontinuity analysis characterizes the individual features that launch reflections; return path management addresses the loop that determines impedance in the first place; and signal distortion effects trace the consequences through to the timing and voltage budgets that decide whether a link works.

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