Electronics Guide

Jitter Metrics

Several complementary metrics are in common use:

• Period jitter: variation in the time between successive rising (or falling) edges of a clock. It bounds setup and hold margins inside a synchronous domain, where a single short cycle is what causes a failure.
• Cycle-to-cycle jitter: the difference between adjacent periods, mathematically the first difference of period jitter. It matters where an abrupt step in period would disturb a load such as a switching converter or a memory controller.
• Time interval error (TIE): the displacement of each observed edge from the corresponding edge of an ideal reference timebase. TIE accumulates phase error rather than differencing it, which makes it the natural metric for serial links, because it maps directly onto how much of the eye remains at the sampling instant.
• Phase jitter: the same displacement expressed in degrees or radians of the carrier, convenient for radio and clocking work where phase rather than absolute time is the quantity of interest.

Very slow phase variation is conventionally separated from jitter and called wander. Telecommunications practice, following ITU-T Recommendation G.810, places the boundary at a modulation frequency of 10 hertz: phase variation below that rate is wander, and variation at or above it is jitter. The distinction is practical rather than physical, since a receiver tracks slow phase movement and only fast movement costs margin.

Viewed in the frequency domain, the same phenomenon is phase noise, the power spread into sidebands around the carrier and expressed in dBc/Hz at a stated offset. Integrating the single-sideband phase-noise curve over a defined offset band and converting the result to time yields an RMS jitter value. This is why oscillator data sheets never quote jitter without an integration band, and why two parts with identical integrated jitter over different bands are not comparable.

Peak-to-Peak Versus RMS Jitter

Jitter is characterized by both peak-to-peak and RMS values, and the two are not interchangeable. RMS jitter is the standard deviation of the timing error distribution and is the appropriate figure for random components that are approximately Gaussian. Peak-to-peak jitter captures the total observed spread, but for a random process it grows without limit as the observation lengthens: acquire more edges and a larger extreme will eventually appear. A peak-to-peak number is therefore only meaningful together with the population or error ratio at which it was taken.

For design work, the relevant peak-to-peak value at a target bit error ratio is derived from the RMS random jitter through the Gaussian tail. At a bit error ratio of 10^-12 the multiplier is approximately 14.07, corresponding to a one-sided tail argument of about 7.03 standard deviations. Tightening the target by three decades to 10^-15 raises the multiplier only to about 15.9. That slow growth is instructive in both directions: reducing RMS random jitter improves the deep tails disproportionately, whereas demanding a lower error ratio costs comparatively little additional margin.

Measuring jitter requires instruments whose own contribution is small compared with the signal under test. Real-time oscilloscopes with sufficient bandwidth and sample rate, equivalent-time sampling oscilloscopes, bit error ratio testers, and phase-noise analyzers each suit different parts of the problem. When the signal approaches the instrument's noise floor, the measured value must be corrected for the instrument's own jitter, which combines with the signal's random jitter in a root-sum-square sense.

Random Jitter

Random jitter arises from physical noise processes that produce unpredictable timing variation. The principal contributors are:

• Thermal noise: random thermal motion of charge carriers in resistors and transistors creates a voltage fluctuation that displaces threshold crossings in time.
• Shot noise: the discrete nature of charge transport produces current fluctuations, significant in semiconductor junctions and dominant in photodiode front ends for optical links.
• Flicker noise: low-frequency noise whose power spectral density rises as frequency falls, roughly as 1/f. In oscillators it is up-converted around the carrier and dominates close-in phase noise.

Random jitter is modeled as Gaussian and unbounded, meaning arbitrarily large excursions occur with exponentially decreasing probability. This is the reason a link never carries an absolute error-free guarantee, only a probability, and the reason total jitter must always be stated against a target error ratio.

The Gaussian model is an engineering approximation with one important limitation. Because flicker noise is not stationary over long intervals, measured random jitter grows with record length rather than converging to a fixed standard deviation. Practical measurements therefore either restrict the observation window, apply the high-pass response of the receiver's clock recovery loop, or specify an explicit integration band, so that only the phase movement a real receiver cannot track is counted.

Deterministic Jitter

Deterministic jitter has identifiable causes, repeats with its stimulus, and has a finite peak-to-peak span. Unlike random jitter it can often be reduced or eliminated by design. The usual subdivision is by mechanism:

• Periodic jitter: modulation at a discrete frequency unrelated to the data, typically injected by power supply ripple, a switching converter, a nearby oscillator, or electromagnetic interference. It appears as a discrete line in the spectrum of the TIE record, which makes the aggressor easy to identify by frequency.
• Data-dependent jitter: timing variation correlated with the transmitted pattern. Its dominant mechanism is intersymbol interference, in which the bandwidth limitation of the channel leaves residual energy from earlier bits that shifts the present transition. Baseline wander through AC-coupling capacitors adds a slower, pattern-dependent offset of the same kind.
• Duty cycle distortion: a systematic difference between the high and low intervals, displacing rising and falling edges in opposite directions. It traces to threshold offset in a driver or receiver, or to asymmetric rise and fall times. Some taxonomies treat duty cycle distortion as a subset of data-dependent jitter, since it too is correlated with the pattern; others count it separately. What matters is that it is counted exactly once in a budget.
• Bounded uncorrelated jitter: the crosstalk-driven remainder, bounded in amplitude but uncorrelated with the victim's own data and without a single dominant frequency. Aggressor lanes carrying unrelated traffic are the usual source.

Combining deterministic components requires care. Independent bounded terms may be added peak to peak for a conservative worst case, which assumes they align in the same bit, but this overestimates the realistic total because simultaneous alignment of several independent mechanisms is rare. Convolving the individual distributions, as statistical link simulation does, gives a more accurate result and is the preferred method when the component distributions are known.

Total Jitter and the Dual-Dirac Model

Because random jitter is unbounded, total jitter cannot be stated as a single peak value and must be specified at a particular bit error ratio. The standard estimator is the dual-Dirac model, which represents the deterministic distribution as two delta functions and convolves them with the Gaussian random part:

TJ(BER) = DJ(δδ) + α(BER) × RJ_rms

Here α(BER) is twice the Gaussian tail argument at the chosen error ratio, approximately 14.07 at 10^-12 and 15.9 at 10^-15. One caveat deserves emphasis: DJ(δδ) is a fitted model parameter chosen so that the model reproduces the observed tails, not a direct measurement of the true peak-to-peak deterministic jitter. When the deterministic distribution is not well approximated by a pair of impulses, as happens with a dominant sinusoidal component or with strong intersymbol interference, the two quantities differ appreciably and the model can understate the real total. Statistical link simulation, which propagates full distributions rather than a two-parameter summary, is the appropriate tool when that assumption fails.

Slope-Dependent Timing Uncertainty

When a waveform carrying noise crosses a threshold, the instant of crossing depends on the noise value at that moment. For small perturbations the relationship is linear:

σ_t = σ_v / (dV/dt)

where σ_t is the resulting RMS timing uncertainty, σ_v is the RMS noise voltage, and dV/dt is the slew rate at the crossing. Three consequences follow directly:

• More amplitude noise produces proportionally more jitter.
• Faster edges reduce noise-induced jitter, because the same voltage perturbation displaces the crossing by less time.
• Jitter is worst where the slope is smallest, which is why a lossy channel that rounds edges hurts timing margin even when the eye still has adequate height.

The numbers involved are small enough to be easy to underestimate. A differential signal swinging 800 millivolts with a 40 picosecond transition presents roughly 20 millivolts per picosecond at the crossing, so 5 millivolts RMS of noise contributes about 0.25 picoseconds RMS of jitter. That is a modest figure at a 200 picosecond unit interval and a serious one at 31.25 picoseconds. The same arithmetic explains why deliberate edge-rate control, often adopted to reduce radiated emissions, trades electromagnetic compatibility against timing margin.

Multilevel signaling sharpens the coupling further. Four-level pulse-amplitude modulation stacks three eyes into the amplitude range formerly occupied by one, costing roughly 9.5 decibels of signal-to-noise ratio and reducing both the vertical opening and the slew rate at each threshold. Amplitude noise that was tolerable in a two-level system converts into materially more jitter in a four-level one.

Power Supply Noise

Noise on power rails reaches the timing budget through several mechanisms:

• Threshold modulation: where a receiver's decision threshold is referenced to the supply, supply ripple moves the threshold and therefore the crossing instant.
• Driver delay modulation: transistor drive current varies with supply voltage, so the propagation delay of an output stage follows the rail. Ripple at a fixed frequency, such as the switching frequency of a converter, produces periodic jitter at that frequency.
• Oscillator and PLL sensitivity: voltage-controlled oscillators have a finite supply pushing figure, and a clock generator converts supply noise into phase noise with high efficiency. This path often dominates, because the resulting jitter is then multiplied along with the clock and distributed to every load.

Simultaneous switching of many outputs is a particularly effective aggressor, since the current transient it draws through package and plane inductance produces a supply disturbance correlated with the data pattern. The resulting jitter is therefore data-dependent rather than periodic, and it does not appear in a test pattern that fails to exercise the aggressors realistically. Power integrity and timing integrity are, in practice, one problem.

Crosstalk-Induced Jitter

Coupled energy from neighboring nets adds noise that the slope relationship converts into timing error. Its statistical character depends on the aggressor. A clock aggressor produces periodic jitter at a predictable frequency. Parallel data lines in a synchronous bus produce data-dependent jitter. Lanes carrying unrelated traffic produce bounded uncorrelated jitter that resembles random jitter in a histogram but, unlike true random jitter, has a hard bound and responds to layout changes.

Because far-end crosstalk in an inhomogeneous dielectric grows with coupled length and with edge rate, the mitigations are geometric: adequate spacing, a continuous reference plane beneath every high-speed net, avoidance of long broadside-coupled runs, and attention to connectors and via fields where spacing is dictated by mechanics rather than by electrical preference. Multiple aggressors do not simply add; worst-case alignment is rare, and statistical treatment gives a more realistic figure than summing peak contributions.

Setup and Hold Checks

A synchronous circuit requires data to be stable for a minimum interval before the capturing clock edge, the setup time, and to remain stable for a minimum interval after it, the hold time. Two independent checks follow, and they behave differently.

The setup check bounds the slowest path against the clock period:

Setup slack = T_period + T_skew - T_clk-q(max) - T_logic(max) - T_setup - T_jitter

The hold check bounds the fastest path against the clock edge itself and contains no period term at all:

Hold slack = T_clk-q(min) + T_logic(min) - T_hold - T_skew - T_jitter

Both must be non-negative. The asymmetry has a practical consequence that catches designers regularly: slowing the clock relieves a setup violation but does nothing whatever for a hold violation, which must be fixed by adding delay to the data path or by correcting clock skew. Jitter erodes both checks, since an early capturing edge shortens the setup window while a late one threatens hold, and the appropriate figure to insert is the jitter the clock distribution cannot remove, not the raw oscillator specification.

Clock skew enters with opposite signs in the two equations. Deliberate skew, sometimes called useful skew, can therefore buy setup margin at the direct expense of hold margin, which is a legitimate technique when a design has hold slack to spare.

Eye Diagrams and Bathtub Curves

The eye diagram remains the most immediate picture of timing health on a serial link. Overlaying many unit intervals on a common time axis produces an eye whose horizontal opening is the timing margin surviving jitter and whose vertical opening is the amplitude margin surviving loss and noise. Its key parameters are eye width at the decision threshold, eye height at the sampling instant, the horizontal spreading of transitions that represents jitter, and the vertical spreading that represents noise.

Because random jitter is unbounded, an eye's apparent width depends on how long the instrument accumulated data, so a meaningful eye is always specified with a population or an error ratio attached. The bathtub curve makes that dependence explicit by plotting bit error ratio against sampling position within the unit interval. The flat floor near the center is set by deterministic jitter; the steep walls rising toward each edge are governed by the random component's standard deviation. Fitting those Gaussian walls at error ratios measurable in reasonable time and extrapolating inward is what makes low-error-ratio compliance testing practical at all. Direct confirmation of a 10^-15 error ratio with enough observed errors for statistical confidence would require on the order of 10¹⁷ transmitted bits, roughly a month of continuous measurement on a single multi-gigabit lane.

Jitter Transfer and Jitter Tolerance

Not all jitter is equally harmful, and the reason is clock recovery. A receiver that extracts its sampling clock from the incoming data follows slow phase movement in the transmitted signal, so low-frequency jitter displaces the data and the sampling instant together and costs no margin. Only jitter above the recovery loop's tracking bandwidth appears as relative error at the decision point. The receiver therefore behaves as a high-pass filter on incoming jitter, and compliance measurements emulate this by processing the captured TIE record through a specified reference clock recovery response, often called a golden PLL, before judging the result.

Two complementary tests characterize the behavior. Jitter transfer measures the ratio of output to input jitter against modulation frequency for a retiming element such as a repeater or a jitter-cleaning PLL; specifications cap the permitted gain peaking so that jitter does not accumulate multiplicatively through a chain of regenerators. Jitter tolerance works in the opposite direction, injecting sinusoidal jitter of increasing amplitude at each frequency and finding the amplitude at which the receiver fails its target error ratio. The resulting mask is high at low frequency, where the loop tracks the modulation, and falls at roughly 20 decibels per decade above the loop corner to a small high-frequency floor. The corner in the mask effectively sets a minimum recovery bandwidth that any conforming receiver must provide.

Spread-spectrum clocking illustrates the principle vividly. To reduce peak radiated emissions, many interfaces modulate the reference frequency slowly, commonly with a down-spread of about 0.5 percent at a modulation rate near 30 to 33 kilohertz. That deliberately injects tens of nanoseconds of accumulated time interval error, far more than a unit interval, yet it is harmless because it lies well inside the recovery loop's tracking band. The same modulation applied to a clock feeding a jitter-critical converter, or placed above the loop bandwidth, would be destructive. Jitter must always be judged against the bandwidth of the loop that has to follow it.

Timing Budgets

A timing budget allocates the unit interval among all contributors and requires that the residual eye remain open at the target error ratio. A high-speed serial budget typically accounts for:

• Transmitter jitter: the serializing clock and output stage, including any residual reference-clock jitter that survives the transmitter PLL.
• Channel effects: intersymbol interference from frequency-dependent loss, reflections from impedance discontinuities, and mode conversion in differential pairs.
• Crosstalk: converted to timing error through the slope relationship, and treated statistically when several aggressors are present.
• Power supply effects: periodic jitter from converter ripple and data-dependent jitter from simultaneous switching.
• Reference clock: the portion of the source's phase noise that falls outside the receiver's tracking band.
• Receiver jitter: clock recovery tracking error, sampler aperture uncertainty, and decision-circuit noise.

Independent random terms combine in a root-sum-square sense, because their variances add; deterministic terms are added directly on the assumption that in the worst case they align. The budget must also carry margin for manufacturing variation, supply and temperature range, and aging, and it must state the conditions under which the numbers hold. A budget that closes only at nominal voltage and room temperature has not been closed.

Oscillator and PLL Jitter

Crystal oscillators serve as the timing reference for most systems and exhibit phase noise that converts to jitter. The characteristics that matter are:

• Phase noise: random phase variation specified as a power spectral density in dBc/Hz against offset frequency, integrated over a stated band to yield RMS jitter.
• Allan deviation: a time-domain measure of frequency stability against averaging interval, the appropriate figure for long-term holdover rather than for link timing.
• Spurious tones: discrete components arising from supply coupling, vibration sensitivity, or fractional-N synthesis, which appear as periodic jitter and can fail a mask even when integrated jitter is comfortable.

A phase-locked loop multiplies a reference to the required rate and shapes jitter as it does so. Within the loop bandwidth the output follows the reference and therefore inherits its phase noise; outside the loop bandwidth the output follows the voltage-controlled oscillator and inherits its noise instead. Choosing the bandwidth is therefore a crossover decision between the two noise sources, and the optimum sits near the offset frequency where their curves intersect. A clean reference argues for wider bandwidth, a quiet oscillator for narrower. Loop damping matters as well, since an underdamped loop produces gain peaking near the corner that amplifies jitter rather than filtering it.

The requirements have tightened sharply. Reference-clock specifications once stated in picoseconds are now stated in femtoseconds for the fastest interfaces, and they are evaluated through the specification's own filter function rather than as a raw wideband figure, precisely because only the untrackable portion matters.

Interconnect-Induced Jitter

Propagation through PCB traces, connectors, and cables adds jitter by several routes:

• Intersymbol interference: conductor loss rising as the square root of frequency and dielectric loss rising roughly linearly combine to attenuate high-frequency content, spreading pulses so that each transition is displaced by the pattern preceding it. On a long backplane channel this is usually the dominant deterministic term.
• Reflections: impedance discontinuities at vias, connectors, and stubs return energy that arrives late and shifts subsequent crossings. An unterminated via stub is a resonant structure that can notch the channel response at a frequency inside the signal band.
• Mode conversion: asymmetry between the two halves of a differential pair, from length mismatch or from fiber-weave variation in the laminate, converts differential energy to common mode and back, producing pattern-dependent jitter that ordinary length matching does not remove.
• Skin-effect and dielectric dispersion: frequency-dependent propagation velocity spreads the edge in time, contributing to the same data-dependent term.

Driver and Receiver Jitter

The silicon at each end contributes as well. Transmitter output timing varies with supply voltage and with the data pattern loading the output stage. At the receiver, noise in the comparator translates into timing uncertainty through the slope relationship, and the sampler's aperture has its own uncertainty. Clock recovery adds tracking error whenever the incoming jitter varies faster than the loop can follow, and a decision feedback equalizer contributes error propagation effects that appear as additional jitter when its taps are mistrained. In serializer and deserializer blocks the divider chain and phase interpolators used for clock generation add quantization steps that appear as bounded deterministic jitter.

Clean Clock Generation and Distribution

Low-jitter timing begins at the source:

• High-quality oscillators: temperature-compensated and oven-controlled crystal oscillators, and SC-cut resonators for the most demanding stability requirements, at correspondingly higher cost and power.
• Jitter attenuators: clock generator and buffer devices built around a narrow-bandwidth PLL that filters reference jitter above the loop corner, at the price of slower lock and greater sensitivity to their own oscillator's noise.
• Spread-spectrum clocking: an intentional addition of low-frequency jitter for emissions control, which must be declared in the budget and confirmed to lie inside every downstream recovery bandwidth.

Distribution then has to preserve what the source achieved. Balanced trees keep skew low, proper termination prevents reflections from corrupting edges, differential distribution rejects common-mode disturbance, and physical separation keeps clock nets away from switching aggressors. A clock buffer with a poor supply rejection ratio, or a clock net routed beside a switching regulator, can undo the benefit of an expensive oscillator entirely.

Power Integrity

Because the supply-to-jitter path is often dominant, power delivery deserves explicit attention:

• Decoupling: a distribution of capacitor values and mounting inductances that keeps the impedance seen by the load below its target across the frequency range of the current demand.
• Plane design: continuous power and reference planes closely spaced, with splits avoided beneath high-speed nets so that return current is never forced to detour.
• Regulator selection and isolation: low-noise linear regulators, or well-filtered switching supplies, dedicated to oscillators and PLLs, with ferrite and capacitor filtering sized against the actual ripple spectrum rather than chosen by habit.

Signal Conditioning

Equalization restores the channel's high-frequency response and directly reduces the data-dependent jitter term:

• Transmitter feed-forward equalization: a short finite-impulse-response filter across adjacent unit intervals. In practice it emphasizes the transition bit relative to steady-state bits, an operation described as pre-emphasis when the transition amplitude is raised and as de-emphasis when the steady-state amplitude is lowered instead. The two are the same filter viewed from different amplitude references; de-emphasis is generally preferred because it does not increase peak output swing.
• Continuous-time linear equalization: an analog receiver stage whose gain rises with frequency to invert the channel's loss, cheap in power but amplifying noise and crosstalk along with the signal.
• Decision feedback equalization: a receiver filter that subtracts the known contribution of previously detected bits, removing post-cursor interference without amplifying noise, at the cost of a demanding timing loop and vulnerability to error propagation.
• Retiming repeaters: full recovery and regeneration part way along a long path, which resets the accumulated deterministic jitter at the price of latency and power, in contrast to a redriver that amplifies the impairments along with the signal.

Clock and Data Recovery Optimization

The receiver's recovery loop must track incoming jitter without amplifying noise, and its bandwidth is the governing trade-off. A wide loop follows more of the transmitted phase movement, which relaxes the jitter tolerance requirement, but it also admits more of its own oscillator's noise and can produce gain peaking that accumulates through cascaded links. A narrow loop filters aggressively but fails the low-frequency corner of the tolerance mask and risks losing lock on long runs without transitions. Specifications constrain both ends of this range, and adaptive implementations widen the loop during acquisition before narrowing it for tracking.

Instrument-Based Measurement

Real-time and equivalent-time sampling oscilloscopes support several complementary views:

• Histogram analysis: the distribution of edge positions, whose Gaussian tails and non-Gaussian core reveal the random and deterministic proportions.
• Trend analysis: the time series of period or TIE values, which exposes drift, modulation, and intermittent disturbances that a histogram averages away.
• Spectral analysis: the Fourier transform of the TIE record, in which periodic jitter appears as discrete lines whose frequencies identify the aggressor and random jitter appears as a broadband floor.

Bit error ratio testers complement the oscilloscope by measuring errors directly rather than inferring them, which is what makes tolerance testing and bathtub extrapolation possible. Phase-noise analyzers cover the clock side of the problem with far better close-in sensitivity than an oscilloscope can achieve. In every case the instrument's own jitter and its trigger or timebase noise must be characterized and removed, and the measurement bandwidth must be stated, since a wider bandwidth admits more noise and yields a larger number for the same signal.

Jitter Decomposition

Separating the total into components enables root-cause analysis. Established techniques include tail fitting, which extracts the random standard deviation from the Gaussian portion of the histogram tails; dual-Dirac fitting, which derives both parameters from measured bathtub data; spectral separation, which isolates periodic components by frequency; and pattern-correlated averaging, which extracts the data-dependent term by averaging edge positions at each position in a repeating pattern. Modern analysis software applies these in combination and reports a hierarchical breakdown.

Two cautions apply. The separation is model-dependent, so different algorithms applied to the same acquisition can report meaningfully different splits between random and deterministic jitter, and a comparison against a specification limit is only valid when the specified method is the one used. Second, a decomposition inherits the limits of its record length: a periodic aggressor slower than the acquisition window appears as drift or as inflated random jitter rather than as a spectral line.

Interface Specifications

Common high-speed interfaces define jitter budgets in these terms:

• PCI Express: total jitter is specified at a bit error ratio of 10^-12 through the 32 GT/s generation, with separate transmitter, reference-clock, and receiver allocations and a defined filter function for the reference clock. PCI Express 6.0 changes the framework: four-level signaling at 64 GT/s raises the raw error rate far above that target, so the specification instead sets a first burst error rate below 10^-6 and relies on lightweight forward error correction together with a strong cyclic redundancy check and link-level retry to reach an acceptable effective error rate.
• Ethernet: IEEE 802.3 defines jitter generation, transfer, and tolerance limits by rate class. The PAM4 lanes used at 400 gigabits per second and above rely on the RS(544,514) Reed-Solomon code, commonly called KP4, which corrects a pre-FEC error ratio of roughly 2.4 × 10^-4 down to a post-FEC target below 10^-15. Electrical compliance for these lanes is therefore expressed in terms of a pre-FEC error ratio rather than a raw eye.
• USB: eye diagram templates and jitter limits are defined per speed mode, with separate transmitter and receiver requirements and specified test fixtures and compliance patterns.
• Serial ATA: transmit and receive jitter are specified separately, with distinct deterministic and total limits at each generation and defined test patterns for each.

The trend across all of them is consistent. Once forward error correction enters the physical layer, the meaningful electrical target moves from an extremely low raw error ratio to a moderate pre-correction one, and the burden shifts from proving a nearly perfect eye to proving that the error statistics fall within what the code can repair.

Test Methodologies

Comparable measurements depend on controlled conditions:

• Pattern selection: pseudo-random binary sequences of specified length, together with protocol-defined compliance patterns, exercise the low-frequency content and worst-case transition densities that expose data-dependent jitter. A short pattern can hide intersymbol interference that a long one reveals.
• Observation time: statistical confidence requires enough edges, and extrapolation to low error ratios requires enough of the bathtub wall to fit reliably.
• Filtering and reference response: the specified clock recovery response must be applied before evaluation, since an unfiltered measurement counts phase movement that a real receiver tracks harmlessly.
• Calibration and de-embedding: fixtures, cables, and probes contribute loss and reflection that must be characterized and removed, and the instrument's own jitter must be subtracted from the measured random component.