Electronics Guide

Characteristic Impedance and the Goal of Matching

A transmission line presents a characteristic impedance, written Z₀, that relates the voltage and current of a wave traveling in one direction along it. The general expression, Z₀ = √((R + jωL) / (G + jωC)), reduces to the familiar Z₀ = √(L / C) whenever the series resistance and the dielectric conductance are small compared with the reactive terms, which is the usual case for a printed-circuit trace above a few megahertz. In that regime the value depends only on the line's geometry and surrounding dielectric, not on its length. A launched edge sees Z₀ as a real resistance for the entire time before any reflection returns, which is why a driver feeding a 50-ohm line initially behaves as though it were loaded by a 50-ohm resistor regardless of what sits at the far end.

Matching means presenting an impedance equal to Z₀ at the point where a reflection would otherwise form. When the impedance seen by the wave never changes, no energy turns back, and the entire incident wave is delivered to the load. Two distinct criteria travel under the name "matching," and confusing them causes trouble. Reflectionless matching sets the load equal to the line impedance, Z_L = Z₀, and is what a terminated digital net or a well-matched antenna feed requires. Conjugate matching sets the load equal to the complex conjugate of the source impedance, Z_L = Z_S*, and is the condition that extracts the maximum available power from a source of fixed internal impedance. On a line whose Z₀ is essentially real and driven from a matched source, the two conditions coincide; where source and load reactances are significant they do not, and the designer must decide which objective governs. Radio-frequency power amplifiers illustrate the split: a small-signal stage is conjugately matched for maximum gain, while a power stage is instead presented the load impedance found by load-pull measurement, which maximizes output power or efficiency and is deliberately not the conjugate match.

Because real interconnects contain connectors, vias, and package transitions that each perturb the impedance, perfect matching is an ideal that design approaches rather than reaches. Board fabrication reinforces the point: controlled-impedance traces are ordinarily specified to a tolerance of about ten percent, tightened to five percent only at added cost, so a nominally 50-ohm line may arrive anywhere in a several-ohm band. The practical aim is therefore not a perfect match but a residual reflection small enough to stay inside the receiver's margin.

The Reflection Coefficient

The fraction of a wave that reflects from an impedance discontinuity is the reflection coefficient. At a load of impedance Z_L terminating a line of impedance Z₀, it is:

Γ = (Z_L − Z₀) / (Z_L + Z₀)

For a purely resistive passive load the coefficient is real and ranges from −1 to +1; a load with reactance makes Γ complex, and passivity limits only its magnitude, which cannot exceed one. When Z_L equals Z₀, the numerator vanishes and Γ is zero: the load is matched and nothing reflects. An open circuit gives Γ = +1, reflecting the full wave in phase and doubling the voltage at the open end; a short circuit gives Γ = −1, reflecting an inverted wave that drives the voltage there to zero. A load that is twice the line impedance reflects one-third of the wave, while a load at half the line impedance reflects one-third inverted. Because reflected power scales as |Γ|², that one-third voltage reflection returns only about eleven percent of the incident power. Reflections occur at the source as well as the load, governed by the same expression with the source impedance in place of Z_L, and a wave can bounce repeatedly between two mismatched ends.

Two related figures express the same information. The voltage standing wave ratio, common in radio-frequency work, is (1 + |Γ|) / (1 − |Γ|); a perfect match gives a ratio of 1, and larger values signal worse mismatch. The return loss, expressed in decibels as −20 log₁₀|Γ|, states how far below the incident wave the reflected wave falls, so a larger return loss is better. A reflection coefficient of 0.1 corresponds to 20 decibels of return loss and a standing wave ratio of about 1.22; a coefficient of 0.2 corresponds to roughly 14 decibels and a ratio of 1.5. One convention trips up newcomers: a network analyzer plots the input reflection as the scattering parameter S₁₁, whose magnitude in decibels is the negative of the return loss, so a port that a datasheet describes as having 20 decibels of return loss appears on the instrument as −20 decibels.

The two standard instruments read the same mismatch in complementary domains. A vector network analyzer sweeps frequency and reports S₁₁ in magnitude and phase, which suits radio-frequency components and the compliance masks that high-speed standards impose on return loss. A time-domain reflectometer launches a fast step and displays the reflected voltage against time, which converts directly to distance and therefore locates each discontinuity—a connector, a via, a stub, a section of trace that necked down under a component pad—at its physical position along the channel. The two views are mathematically equivalent, and modern instruments transform between them.

Series, Parallel, and AC Termination

Termination resistors are the everyday tools of impedance matching in digital systems, and they fall into a few canonical arrangements. Series termination, also called source-series termination, places a resistor in series with the driver close to its output. The resistor is chosen so that the driver's own output resistance plus the series resistor sums to the line impedance: a CMOS output stage of roughly 10 to 30 ohms feeding a 50-ohm trace therefore takes a series resistor of about 22 to 33 ohms, values that dominate the standard resistor kits of digital boards. The driver launches a half-amplitude wave into the matched source; the wave doubles at the unterminated, high-impedance receiver to reach full amplitude, and the reflection that returns to the source is absorbed there because the source is now matched. The resistor must sit within a few millimeters of the driver pin, because the trace between the pin and the resistor is itself an unterminated stub. Series termination dissipates no static power, which suits point-to-point nets driven from a single source, but the half-amplitude step exists along the line until the far-end reflection arrives, so it favors topologies with one receiver at the end rather than several distributed along the line.

Parallel termination places a resistor equal to Z₀ from the line to a reference at the far end, absorbing the incident wave directly at the load so that no reflection ever forms. It delivers a clean full-amplitude signal and tolerates multiple loads, but it draws continuous current whenever the line is held at a logic level, raising power consumption and loading the driver. The reference the resistor returns to is itself a design choice. Terminating a 50-ohm line to ground from a 3.3-volt rail draws about 66 milliamperes whenever the line is high and none when it is low; terminating instead to a dedicated mid-rail supply, conventionally called V_TT, halves the swing across the resistor and so draws about 33 milliamperes in either state, at the cost of a regulator that must both source and sink current. Memory interfaces show both approaches in sequence: DDR3 uses stub-series terminated logic with command and address lines terminated to V_TT at half the supply, whereas DDR4 moved to pseudo-open-drain signaling that terminates to the supply rail itself so that termination current flows only in the low state.

AC termination, or RC termination, addresses static dissipation by placing a capacitor in series with the terminating resistor. The capacitor blocks direct current, so no power is wasted holding a static level, while passing the high-frequency edges to the resistor that damps reflections. Sizing it is the whole design: the resistor-capacitor time constant is usually made several times the line's round-trip delay so that the resistor still looks connected while reflections are alive, which puts board-level values in the range of tens to a few hundred picofarads. Too small a capacitor fails to damp the reflection; too large a one restores much of the static current the scheme was meant to avoid and adds transient current on every edge. The result is a scheme that works well over a band of edge rates and data patterns rather than universally, and it is most attractive on clock and strobe lines whose activity is predictable.

Source Termination Versus Load Termination

Whether to terminate at the source or at the load is a design decision shaped by topology, power, and signal levels. Source termination consumes no static power and is therefore attractive for low-power and battery-operated designs, but it relies on a single driver and a single far-end receiver, because the half-amplitude wave traveling outbound would be misread by any receiver tapped along the middle of the line before the far-end reflection completes the swing. It also depends on the driver's output impedance being predictable, which is why many output stages include controlled or calibrated drive strength.

Load termination, by contrast, presents a clean full-amplitude waveform at every point on the line from the first instant, so it serves multidrop and multireceiver buses well, at the cost of continuous current and added driver loading. Many high-speed systems combine both, terminating the source to absorb residual reflections while terminating the load to suppress the primary one, a doubly terminated line that trades efficiency for the lowest reflection and the most forgiving timing. The choice is rarely abstract: it follows from how many receivers share the net, how much power the rail can spare, and how much voltage swing the receiver requires.

Thevenin and Differential Termination

Thevenin termination, also called split termination, implements parallel termination with two resistors instead of one: one resistor ties the line to the supply and the other ties it to ground. The parallel combination of the two equals the line impedance, satisfying the match, while their divider ratio sets the bias voltage the line settles to when undriven. A 50-ohm line on a 3.3-volt rail terminated with a matched pair of 100-ohm resistors is the textbook case: the pair presents 50 ohms to the wave and holds the idle line at 1.65 volts, drawing 16.5 milliamperes through the divider when the net is quiet and about 33 milliamperes when the driver holds either rail. An unequal pair shifts the idle level toward one rail while still meeting the impedance target, which is how designers bias a bus to a defined inactive state. This arrangement lets a single termination supply a defined idle level—useful when the receiver expects the bus to rest at a particular voltage—and it can reference the termination to the full supply rather than a separate termination rail. Its drawback is that current flows through the resistor pair continuously, and the two resistors together can draw more power than a single parallel resistor returned to a dedicated mid-rail termination voltage.

Differential termination matches a complementary pair rather than a single-ended line. The simplest form places one resistor equal to the differential impedance directly across the two conductors at the receiver, absorbing the differential wave. Target values follow the governing standard rather than a universal number: low-voltage differential signaling under ANSI/TIA/EIA-644 terminates in 100 ohms across the pair, as do HDMI and 1000BASE-T Ethernet; USB 2.0 and USB 3.x specify 90 ohms; and PCI Express, which began at 100 ohms, moved to 85 ohms from its second generation onward. A refinement splits the terminating resistor into two halves in series and connects their midpoint through a capacitor to ground, which terminates the common-mode component as well as the differential component without dissipating static power in the common-mode path; the capacitor is typically a few nanofarads or larger, chosen to look like a short circuit across the signal band.

Because differential signaling relies on the tight coupling and balance of the pair, the termination must be symmetric and placed close to the receiver so that the stub beyond it does not reintroduce reflections. Resistor tolerance matters as much as nominal value: a mismatch between the two halves of a split termination converts part of the differential signal into common mode, which the balance of the pair no longer cancels and which radiates. One-percent parts are the norm, and the resistor's own package parasitics argue for the smallest footprint the assembly process allows, since the inductance of a larger case appears in series with the termination exactly where the match must be cleanest. Differential termination underpins effectively every multi-gigabit standard that carries data as balanced pairs.

On-Die Termination and Calibration

As data rates climbed, the short stub between a package pin and an external termination resistor became a meaningful discontinuity in its own right, and the resistor was moved onto the silicon. On-die termination integrates the terminating resistance inside the receiver or transceiver, eliminating the package and board parasitics that an external resistor would add and removing components from an already crowded board. The resistance is realized with transistors operating in their linear region or with switched resistor arrays, and because the absolute resistance of an on-chip device varies with process, voltage, and temperature, on-die termination is almost always calibrated.

The calibration mechanism in DDR memory is the clearest illustration. Each device carries a ZQ pin tied to a single external reference resistor of 240 ohms held to one-percent tolerance, a component chosen precisely because a discrete resistor holds its value across temperature far better than anything on the die. A calibration engine compares the on-die pull-up and pull-down arrays against that reference and trims them until they agree, then repeats the comparison periodically to track drift. Because every termination value derives from the same reference, the available settings are simple fractions of it: DDR4 offers nominal termination resistances of 240, 120, 80, 60, 48, 40, and 34 ohms, corresponding to the reference divided by one through seven, and the DRAM output driver is typically configured to 34 or 48 ohms.

On-die termination also enables dynamic behavior that discrete resistors cannot match. A memory interface applies one termination value while a device is being written, another while it is idle but selected, and none at all on the device that is currently driving, switching between them through mode-register settings and a dedicated control signal. Ranks that are not participating in a transfer can present termination that damps reflections for the rank that is, which is what makes multi-rank buses viable at gigabit rates. This flexibility, combined with the parasitic reduction, has made on-die termination standard in DDR memory, SerDes links, and most multi-gigabit interfaces, where an external resistor simply could not be placed close enough to the receiver to be effective.

Discontinuities and the Limits of a Match

A terminating resistor matches the end of the line, but a channel is matched only if its impedance stays constant everywhere in between. Every physical transition perturbs it. A signal via adds capacitance at its pads and inductance along its barrel, and the unused portion of the barrel below the exit layer forms a resonant stub that can be removed by back-drilling or avoided by choosing exit layers deliberately. A connector introduces its own impedance profile and, more damagingly, disturbs the return path where ground contacts are sparse. Surface-mount pads for series capacitors and resistors sit on a widened copper area that drops the local impedance, and traces necking down to escape a fine-pitch ball-grid array narrow enough to raise it.

Each of these perturbations is small on its own, and whether they matter depends on how they compare with the signal's rise time. A discontinuity whose delay is a small fraction of the edge produces a brief, low-amplitude reflection that the edge itself smooths over; the same feature becomes a hard reflection once the edge sharpens enough to resolve it. This is why interconnect that was invisible at hundreds of megabits becomes the dominant impairment at tens of gigabits, and why the discipline at high rates shifts from adding termination to removing discontinuities: shortening stubs, tuning antipad geometry, keeping return paths continuous beneath every transition, and simulating the full channel rather than the trace alone.

The corollary is that a match is a property of the whole path, not of one component. A perfectly calibrated on-die termination behind a resonant via stub delivers a worse channel than a modest external resistor on a clean one. Design flows therefore evaluate the assembled channel against the return-loss and insertion-loss masks that the governing standard publishes, using field-solver models of the vias and connectors alongside the driver and receiver models, and treat any single-point termination value as one term in that larger budget.

Matching Networks for Radio Frequency

When a source and load have unequal impedances that cannot simply be made equal—an antenna whose impedance is fixed by its physics, or an amplifier with a particular optimum load—a matching network transforms one impedance into the other across a band of frequencies. Unlike a terminating resistor, which absorbs energy, a matching network is built from reactive components, inductors and capacitors, that store and exchange energy without dissipating it, so it transforms impedance with low loss. The simplest is the L-network, two reactive elements that move an impedance to a desired value at a single design frequency. Its loaded quality factor is not a free parameter: for a given ratio of the higher resistance to the lower, the L-network takes the one value √(R_high / R_low − 1), and that value fixes the bandwidth. Adding a third element forms a pi-network or a T-network, which restores control over the loaded quality factor—but only upward. Because a three-element network can raise the loaded quality factor above the L-network minimum and never below it, pi- and T-networks narrow the match and sharpen harmonic rejection rather than broaden it. Widening the band instead calls for cascading L-sections or using a multisection transformer, each stage stepping part of the way.

Designers commonly reason about these transformations on the Smith chart, a graphical map of the reflection coefficient on which adding a series or shunt reactance traces a predictable arc, letting a network be synthesized by following arcs from the load impedance to the center, where the match is perfect. At higher frequencies the reactive elements may be replaced by transmission-line sections—quarter-wave transformers and stubs—that achieve the same transformation through the line's own impedance-transforming property. A quarter-wave section matches two real impedances when its own characteristic impedance is their geometric mean, √(Z₀ Z_L), so a 50-ohm source feeding a 100-ohm load matches through a quarter-wave line of about 70.7 ohms at the design frequency.

Every matching network is narrowband to some degree, because the reactances that produce a perfect match at one frequency drift away from it at others, and widening the matched band accepts a less perfect match across it. That trade is not merely practical but fundamental: the Bode–Fano limit bounds how well any lossless network can match a load with reactive energy storage over a given bandwidth, so the reactance of an antenna or a transistor input sets a ceiling that no amount of network complexity can lift. Real components tighten the ceiling further. Inductor and capacitor quality factors are finite, so a high-Q network dissipates a measurable fraction of the power it was built to deliver, and every part has a self-resonant frequency above which it ceases to behave as the element the schematic names. Practical designs therefore keep the loaded quality factor no higher than the specification demands and verify the finished network by measurement rather than by synthesis alone.

When Impedance Matching Matters

Matching is not always necessary, and applying it where it is not needed wastes power and components. The deciding factor is whether the interconnect behaves as a transmission line, which it does once its one-way propagation delay is an appreciable fraction of the signal's rise time. A short trace carrying a slow edge settles long before reflections can matter, and a terminating resistor on it would only burn power. As edges sharpen or lines lengthen, the round-trip delay grows comparable to the rise time, reflections persist into the bit period, and termination becomes essential to keep overshoot, ringing, and intersymbol interference within the receiver's budget.

Rules of thumb put a number on that threshold, though published values disagree by a factor of three: designers variously treat a net as electrically long once its one-way delay exceeds a tenth, a sixth, or a third of the rise time, with one-sixth the most widely quoted. The arithmetic is easy enough to do on any net. A printed-circuit trace propagates at roughly 150 picoseconds per inch, faster on an exposed microstrip and slower buried in stripline, so a driver with a 500-picosecond edge reaches the one-sixth threshold at a little over half an inch. Note what the rule does and does not settle: it identifies which nets deserve attention, not what the reflection on any of them will be. The spread among the published thresholds is itself the warning that the criterion is a screen rather than a verdict, and marginal nets belong in simulation, where the actual overshoot can be compared against the receiver's absolute-maximum and timing specifications.

The cost of mismatch differs by domain. In digital signaling the penalty is distortion and lost timing margin, so the threshold for adding termination is set by the noise and timing budget of the link. In radio-frequency and power applications the penalty is reflected power: a mismatched antenna radiates less and can reflect energy that destabilizes or damages the source, making a good match a requirement rather than an optimization. Across both, the engineering task is to identify which nets and interfaces are sensitive, choose a termination or matching scheme suited to the topology and power constraints, and verify with simulation and measurement that the residual reflections stay safely below the level that would compromise the system.

Summary

Impedance matching arranges the impedances along a signal path so that a wave travels from source to load without harmful reflection. The reflection coefficient, set by the ratio of the load impedance to the line's characteristic impedance, quantifies how much of a wave turns back at any discontinuity and is zero only when the two are equal. Digital systems realize matching with termination resistors—series at the source, parallel, AC, Thevenin, and differential at the load—chosen according to topology, power budget, and required signal swing, and increasingly with calibrated on-die termination that removes the parasitics of an external part. Radio-frequency systems transform unequal impedances with reactive matching networks, subject to fundamental bandwidth limits that no network topology can evade. In both domains the match belongs to the whole path: a termination is only as good as the vias, connectors, and pads between it and the driver. Matching matters wherever an interconnect acts as a transmission line, and the discipline is to apply it where reflections would otherwise erode timing margin or waste transmitted power, then confirm the result by measurement.

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