Electronics Guide

Fundamentals of Impedance Discontinuities

An impedance discontinuity exists wherever the characteristic impedance of the propagation path departs from its nominal value. The cause may be geometric, such as a change in conductor width or in the distance to the reference plane, or it may be material, such as a change in dielectric constant or a resin-rich region in the glass weave. It may also be structural, as when the return path is interrupted by a plane split or by an antipad clearance.

The Reflection Coefficient

When a wave traveling in a line of impedance Z₁ meets a line of impedance Z₂, the fraction of the incident voltage that reflects is given by the reflection coefficient Γ = (Z₂ − Z₁) / (Z₂ + Z₁). The remainder, 1 + Γ, continues forward. The sign of Γ carries physical meaning: a step up in impedance produces a positive reflection that adds to the incident wave, while a step down produces a negative reflection that subtracts from it. An open circuit gives Γ = +1 and a short circuit gives Γ = −1.

The formula shows why designers worry about impedance tolerances that sound modest. A ten percent step, from 50 ohms to 55 ohms, yields Γ ≈ 0.05, so roughly five percent of the incident amplitude turns around. One such step is usually harmless. A channel that accumulates a dozen of them, each launching a reflection that bounces between the other discontinuities, is a different matter. Reflections do not simply add; they interfere, and the resulting ripple can be considerably larger or smaller than any single contribution.

Two discontinuities separated by a length of line behave as a weak resonant cavity. Energy reflected from the second feature travels back to the first, reflects again, and re-emerges delayed by the round-trip time. In the frequency domain this appears as periodic ripple in the return loss and insertion loss, with a spacing between peaks equal to the reciprocal of twice the one-way delay between the two features. Reading that ripple period backwards is a practical way to locate the pair of features responsible for a resonance.

Rise Time Decides What Matters

Whether a discontinuity behaves as a lumped parasitic or as a length of mismatched transmission line depends on its electrical delay compared with the signal edge. The common working rule is that a feature whose one-way delay is less than roughly one-tenth of the signal rise time acts as a simple lumped capacitance or inductance, and the edge largely averages over it. Once the delay approaches the rise time, the feature must be treated as a distributed structure with its own impedance and its own reflections at entry and exit.

Converting that rule into physical dimensions requires the propagation delay of the medium. In FR-4 stripline, with a dielectric constant near 4, signals travel at roughly 170 picoseconds per inch, or about 6 inches per nanosecond. Microstrip, whose fields are partly in air, is faster, typically in the region of 145 to 155 picoseconds per inch. A signal with a 100-picosecond edge therefore spreads that edge over roughly 0.6 inch of stripline, and a discontinuity shorter than about a tenth of that distance is unlikely to be resolved on its own.

A companion rule of thumb converts edge rate into bandwidth: the knee frequency, above which the spectral content of a digital edge falls away quickly, is approximately 0.35 divided by the rise time. A 100-picosecond edge implies a knee near 3.5 GHz, which is the frequency to which interconnect models and measurements must remain trustworthy. This is why the specified rise time of the driver, not the bit rate printed on the datasheet, is the correct starting point for deciding which features deserve analysis.

Time-Domain and Frequency-Domain Views

Discontinuity analysis uses both domains because each answers a different question. Time-domain reflectometry maps impedance against distance and therefore says where a problem is: a bump in the impedance profile can be traced to a specific via field or connector footprint. Frequency-domain analysis through S-parameters says how much the problem costs, expressing the result as return loss, insertion loss, and phase or group-delay distortion across the band of interest.

The two views are mathematically equivalent, related by the Fourier transform, and modern instruments convert freely between them. High-speed serial standards generally state their interconnect requirements as frequency-domain masks that the assembled channel must satisfy, so frequency-domain results are usually the contractual form. Time-domain results remain the diagnostic form, because they localize the offending feature.

Via Modeling and Optimization

Vias are the most common and, in dense multilayer boards, usually the most consequential discontinuity. A via is a short vertical transmission line whose geometry is dictated by drilling and plating rather than by impedance control, so it rarely matches the horizontal traces it joins.

Via Parasitics

To a first approximation the signal via and the surrounding antipad in the reference planes form a crude coaxial line, with the barrel as the inner conductor and the plane edges as the outer. The impedance follows the coaxial relation, rising roughly as the natural logarithm of the ratio of antipad diameter to barrel diameter and falling as the square root of the dielectric constant. For practical ratios this places most signal vias below the impedance of the traces they connect, commonly somewhere between 25 and 50 ohms against single-ended traces near 50 ohms and differential pairs near 85 to 100 ohms. Enlarging the antipad raises the via impedance and improves the match; shrinking it does the opposite.

A lumped model captures the same behavior with two elements. The pads left on every layer the via passes through form parallel-plate capacitance to the adjacent planes, typically contributing a few tenths of a picofarad up to about a picofarad in total, depending on layer count and pad size. The barrel and its return path contribute inductance, commonly in the range of roughly 0.3 to 1.5 nanohenries, falling as ground vias are placed closer and the return loop is shortened. Because pad capacitance usually dominates in ordinary stackups, the net effect of a via is most often capacitive, showing as a downward dip in the impedance profile.

Stub Resonance

The more damaging via effect is not the barrel impedance but the stub. A plated through hole spans the full board thickness even when the signal leaves at an intermediate layer, and the unused remainder forms an open-circuited stub hanging off the signal path. At the frequency where that stub is a quarter wavelength long, it transforms the open at its far end into a near short at the junction, producing a deep null in insertion loss.

The first null falls approximately at the propagation velocity divided by four times the stub length. Using 6 inches per nanosecond for FR-4, a 100-mil stub resonates near 15 GHz and a 200-mil stub near 7.5 GHz. Those numbers set the design constraint directly. A 25 Gb/s NRZ link has its Nyquist frequency at 12.5 GHz, so a 100-mil stub places a deep null barely above the fundamental of the worst-case data pattern, which no amount of receiver equalization will repair. Thick backplanes are the classic offender, because a signal dropping to an upper layer leaves nearly the whole board thickness behind as stub.

Optimization Strategies

Several levers control via behavior, and most designs use more than one. Back-drilling removes the unused stub after plating by drilling out the barrel to just past the exit layer, leaving a short remnant that pushes the resonance well above the band of interest; it is the standard remedy for thick boards. Blind and buried vias avoid the stub entirely at higher fabrication cost. Via-in-pad places the via inside the component land to shorten the horizontal stub as well, though it requires conductive or nonconductive fill and capping so that solder does not wick away during reflow. Ground via fencing places return vias close beside the signal via to shorten the return loop, and removing unused pads on layers the via merely passes through trims capacitance.

For differential pairs the objective shifts from matching a single impedance to preserving symmetry. Symmetric via pairs with ground vias placed identically on both sides keep the two halves of the pair electrically alike, which limits the conversion of differential energy into common mode. An asymmetric via structure can meet its differential impedance target and still be unacceptable because of the mode conversion it creates.

Full-Wave Modeling

Lumped models are useful for intuition and for fast what-if studies, but they lose accuracy once the structure becomes an appreciable fraction of a wavelength. Full-wave electromagnetic solvers integrate Maxwell's equations over the three-dimensional geometry and capture what lumped models cannot: cavity resonances between plane pairs, coupling between neighboring vias in a dense field, radiation, and the frequency dependence of conductor and dielectric loss. A credible via model must include skin effect, dielectric loss, surface roughness, and the surrounding ground structure, and it must remain valid to at least the knee frequency of the signals it will carry.

Pad and Antipad Effects

Component pads and the antipad clearances in the reference planes act as a complementary pair of perturbations, and they push the local impedance in opposite directions.

A pad is a patch of copper wider than the trace, so it adds capacitance to the nearest reference plane in proportion to its area and inversely with the dielectric thickness beneath it. Added capacitance lowers the local impedance. Larger pads give better assembly yield and mechanical robustness but a deeper impedance dip, which is the central trade-off in footprint design for high-speed parts.

An antipad works the other way. Clearing copper from the reference plane around a via is electrically necessary to avoid a short, but it removes the plane surface directly opposite the conductor and therefore reduces capacitance, raising the local impedance. Enlarging the antipad is consequently one of the simplest tools for pulling a capacitive via back toward the trace impedance. It is not free: the wider clearance carves a larger hole in the plane, lengthening the return path for any other signal routed nearby and enlarging the plane-pair cavity that can resonate.

Because pad capacitance and antipad clearance oppose one another, footprint design is an exercise in cancellation rather than in minimizing either quantity alone. Practical measures include removing pads on layers the via only passes through, choosing noncircular antipad outlines such as ellipses or stadium shapes so that adjacent vias in a dense array can share clearance without merging into a large plane void, and reducing the land size on critical nets to whatever the fabricator's registration tolerance allows. For the most demanding nets, designers tune the pad and antipad geometry in a field solver until the simulated impedance profile is flat through the transition, then verify the result on a test coupon.

Reference Plane Transitions

A signal that changes layers changes reference planes, and the return current has to follow. Return current is not an abstraction: it flows in the plane directly beneath the trace, tracking the signal closely because that path has the lowest loop inductance at high frequency. When the signal jumps through a via, the return current must jump too, and it can only do so where a conductive or capacitive path exists between the two planes.

If the transition is between two planes held at the same potential, a stitching via placed beside the signal via provides that path directly. If no such via is nearby, the return current is forced to detour to the nearest plane connection, which may be inches away. The detour enlarges the current loop, and the added inductance shows up as an impedance bump at the transition, as ground bounce shared with every other signal using those planes, and as an efficient loop antenna that radiates. This is the mechanism behind a large share of the emissions failures traced to layer changes.

The remedy is short and well established. Place at least one ground via immediately beside each signal via, typically within a via diameter or two, and place them symmetrically around differential pairs. Coaxial arrangements that surround a critical signal via with a ring of ground vias give the tightest control. On boards that change layers frequently, a general grid of stitching vias between plane pairs keeps a return path available everywhere rather than only where a designer remembered to add one.

Transitions between planes at different potentials, such as from a ground-referenced layer to a power-referenced layer, cannot use a direct via and are intrinsically worse. The return current must cross through the interplane capacitance, through nearby decoupling capacitors, or through both. Decoupling capacitors help but bring their own mounting inductance and are effective only over a limited band. Buried capacitance layers, formed by a very thin dielectric between a power and ground plane pair, raise the interplane capacitance and improve the transfer across a broad band. The most reliable approach is to avoid the situation in the stackup: route critical high-speed layers so that layer changes stay between planes of the same potential.

Connector Launch Design

The launch is the region where a board trace hands its signal to a connector, and it is often the single worst discontinuity in an otherwise well-controlled channel. It combines every difficulty already discussed and adds a change of field geometry: a planar microstrip or stripline mode has to become the coaxial or quasi-coaxial mode the connector supports, over a distance of a few millimeters, through a footprint whose dimensions are fixed by the mechanical part rather than by the electrical requirement.

Several problems arrive together. The footprint's through holes leave stubs unless they are back-drilled or the connector is a press-fit part designed for the full board thickness. The pads for the connector pins add capacitance where the trace is trying to hold a constant impedance. The ground pattern of the connector may not align with the return path the board provides, so return current has to reorganize itself precisely where the signal is most vulnerable. Plating and press-fit tolerances vary the geometry from board to board.

Connector vendors respond by publishing recommended footprints, and following them is almost always the right decision. These recommendations specify hole and pad sizes, antipad outlines, ground via placement, and often the shape of the trace taper approaching the pins. They embody simulation and measurement that individual designers cannot easily repeat, and departing from them, most often to reclaim routing space, is a frequent cause of channels that fail return loss with no obvious explanation. Where a recommended footprint is unavailable, the usual practice is to void the reference plane locally beneath the launch pads, which reduces the capacitive loading that the oversized pads would otherwise add.

Differential launches carry the same symmetry requirement as differential vias. Matched via lengths, identical ground structures on both sides of the pair, and equal trace lengths into the pins preserve balance and limit mode conversion. Complete verification requires joining the board simulation to the connector's own S-parameter model, supplied by the manufacturer, so that the two halves of the interface are analyzed as one structure rather than separately.

Right-Angle Bend Effects

A square corner in a trace adds a small triangle of copper at the outer edge beyond the width the straight trace would occupy. That extra metal adds capacitance and therefore dips the local impedance, while current crowding at the inner corner contributes a small inductive effect. The corner is a genuine discontinuity, but its magnitude deserves to be stated honestly.

For a typical digital board trace, the excess capacitance of a single square corner is a small fraction of the capacitance of one via. Measurements of ordinary printed circuit geometries have repeatedly shown that the effect on digital signals well into the multi-gigahertz range is minor and usually buried beneath the reflections from vias, connectors, and package transitions in the same channel. The long-standing prohibition against right-angle bends, which also invoked etching and radiation arguments, is largely folklore as applied to digital layout on modern processes, though the habit of avoiding them is harmless.

Where corners do matter is microwave and millimeter-wave work, in which trace dimensions become an appreciable fraction of a wavelength and a corner can no longer be treated as a lumped element. There the standard remedy is the mitered corner: cutting the outer corner at 45 degrees removes the excess copper and largely cancels the capacitive perturbation. The optimum amount to cut depends on the ratio of trace width to dielectric height. Empirical microstrip studies place it in the region of half to roughly three-quarters of the corner diagonal for common width-to-height ratios, with the cut growing as the trace narrows relative to the dielectric; the precise figure for a given stackup is best confirmed in a field solver. A pair of 45-degree bends or a swept arc achieves a similar result and is easier to draw consistently in layout tools.

The practical conclusion is one of proportion. On a digital board, effort spent eliminating corners is effort not spent on via stubs and connector launches, which are one or two orders of magnitude more important. On a millimeter-wave board, corner geometry is a first-order design variable.

Serpentine Routing Impacts

Serpentine routing, or trace meandering, inserts folded sections of line to add propagation delay so that the members of a bus or a differential pair arrive together. It is standard practice, and it introduces a family of side effects that are worth understanding because the most important one is counterintuitive.

The obvious costs are straightforward. Each fold contributes corner discontinuities, and the added copper contributes added conductor and dielectric loss, so a heavily meandered net is slightly lossier than a straight one of the same electrical length. Neither effect is usually decisive.

The subtle cost is that a meander does not deliver the delay its physical length implies. The parallel segments of the fold run close together and couple to each other, and that coupling supports a faster propagating mode along the folded structure. The result is that tightly packed serpentines run measurably fast: a matching structure drawn to add fifty picoseconds may deliver noticeably less. Since the entire point of the structure is timing accuracy, this shortfall directly undermines its purpose, and it grows worse as the segments are packed more tightly to save area.

The mitigation follows from the mechanism. Increasing the spacing between parallel segments weakens the coupling and restores the expected delay; a common guideline is a separation of at least three times the trace width, and four or more where board area permits. Keeping the meander amplitude and period uniform avoids introducing impedance variation of its own, and using mitered or arced corners keeps the per-fold discontinuity small. Distributing the required delay across several small meanders rather than concentrating it in one dense block also reduces coupling. Where timing margin is tight, the honest approach is to extract the meander in a field solver and use its simulated delay rather than its drawn length.

Differential pairs add a symmetry requirement. Both traces must follow the same meander pattern with synchronized bends so that the pair stays balanced and the differential impedance stays constant. Compensating skew by lengthening only one member of a pair, sometimes called intra-pair matching, should be done as close to the source of the skew as possible and with the smallest structure that works, because any asymmetry in the pair converts differential energy into common mode.

Necking and Spreading

Necking is the narrowing of a trace and spreading is its widening. Because characteristic impedance falls as the conductor widens toward its reference plane, necking raises the local impedance and behaves inductively, while spreading lowers it and behaves capacitively.

Necking is rarely a choice. Escape routing from a fine-pitch ball grid array frequently leaves less clearance between adjacent lands than the nominal trace width requires, so the trace narrows for the length of the escape and widens again once it is clear of the array. The same happens between the pins of fine-pitch connectors and beneath small passive components. The necked section itself can be perfectly well controlled; the reflections come from the abrupt steps at its two ends.

The rise-time criterion governs how much this matters. A necked section whose one-way delay is well under a tenth of the signal rise time acts as a small series inductance and is generally tolerable. A section long enough for the edge to resolve behaves as a length of line at the wrong impedance, reflecting at entry and again at exit, with the two reflections interfering according to the section's delay. The design objective is therefore to keep escapes short rather than to keep them wide, which is fortunate because escape geometry is fixed by the component.

Where a width change cannot be kept short, tapering the transition spreads the impedance change over distance and reduces the reflection, because a change that is gradual compared with the spatial extent of the edge presents no sharp boundary for the wave to reflect from. Linear tapers are simple and effective; profiled tapers borrowed from microwave practice perform better for a given length but are seldom warranted on digital boards. Where a taper is impractical, compensating locally is an alternative: a deliberately widened section of trace placed beside an inductive feature adds capacitance that partially cancels it, and the same idea in reverse compensates a capacitive via with a short necked section. Compensation of this kind is a tuning exercise that requires electromagnetic simulation and is sensitive to etch and stackup tolerances, so it belongs on the few nets that justify the effort rather than as a general practice.

Teardrop Connections

A teardrop is a tapered fillet of copper added where a trace meets a pad or a via land, replacing the abrupt step in width with a smooth flare. Most modern layout tools generate them automatically from a design rule.

The primary justification is manufacturing, and it is a strong one. Drilled holes cannot be registered perfectly to the etched artwork, and a drill that breaks slightly out of its land on the side where the trace enters can sever the connection outright. The teardrop adds copper exactly where that failure would occur, so the joint survives the tolerance stack. Teardrops also relieve mechanical and thermal stress at the junction, where trace separation otherwise tends to begin during thermal cycling or flexure. For high-reliability and high-layer-count work, many fabricators either require them or recommend them as a matter of course. A related but distinct fabrication concern, the acid trap, arises from acute angles between conductors rather than from trace-to-pad junctions, and teardrops are not primarily a remedy for it.

The signal integrity contribution is real but modest, and it should not be oversold. Softening the width step does reduce the abruptness of the impedance change, but a teardrop is physically small, so its electrical length is short compared with the edges on most boards and the improvement it produces is correspondingly small. It also adds copper, which adds capacitance, so on a net already suffering from capacitive pad loading a teardrop is a marginal net negative rather than a positive. The honest summary is that teardrops are a manufacturing feature with a mild and situational electrical side effect, and they should be specified for the reason that actually justifies them.

Their real cost is space. Teardrops widen copper exactly where dense designs have the least room, and they can force spacing violations in tight escape regions. Standard practice is to enable them globally and allow the tool to suppress them where clearance rules would be violated, then review the exceptions on critical nets. Where a genuinely optimized transition is required, at millimeter-wave frequencies for instance, the geometry should be designed as a taper in a field solver rather than left to a generic teardrop rule.

Differential Discontinuities and Mode Conversion

Differential signaling changes what counts as a discontinuity. A differential pair carries two modes, and a feature can be harmless to one and damaging to the other. The quantity that matters alongside differential impedance is symmetry, because it is asymmetry that couples the two modes together.

When the two halves of a pair encounter unequal geometry, whether unequal via structures, an asymmetric ground arrangement, a plane split crossed by only one trace, or length mismatch introduced by an unbalanced meander, part of the differential signal converts into common mode. The consequences are twofold. The differential signal loses the converted energy and gains distortion, and the resulting common-mode current flows on both conductors in phase, which the pair's cable or connector shield cannot cancel, making it a far more efficient radiator than the differential signal it came from. A large share of emissions failures on differential interfaces trace back to a small asymmetry somewhere in the launch or via structure.

Mixed-mode S-parameters express this directly. The differential insertion and return loss terms describe the wanted path, while the mode-conversion terms describe how much differential energy leaves as common mode and vice versa. Modern high-speed standards specify limits on both, and a channel can meet its differential requirements comfortably while failing on mode conversion. Since conversion originates in asymmetry, the design response is geometric: keep the two halves of every discontinuity as nearly identical as fabrication allows, and correct skew where it is created rather than compensating for it far downstream.

Analysis Techniques and Tools

Discontinuity work relies on a small set of complementary tools, each with characteristic strengths and characteristic blind spots.

Time-Domain Reflectometry

Time-domain reflectometry launches a fast step into the interconnect and records what returns. Because the delay of a reflection maps to the distance of the feature that produced it, the result reads as an impedance profile along the line, which makes it the natural tool for localizing a problem to a particular via field or footprint.

Its resolution is limited by the rise time of the incident step, and the limit is tighter than it first appears. The reflection makes a round trip, so two features separated by less than roughly half the spatial extent of the incident edge blur into a single event. A step with a 30-picosecond edge therefore cannot cleanly separate features a few millimeters apart in a dense via field, and the measured profile understates the depth of narrow features because the instrument averages over them. Interpreting a time-domain trace requires keeping this smoothing in mind, and comparing against a simulated profile produced with the same effective rise time is a standard way to avoid over-reading the result.

Vector Network Analysis and S-Parameters

A vector network analyzer measures the interconnect's frequency response directly, producing the S-parameter set from which return loss, insertion loss, group delay, and mode conversion are derived. This is the form in which channel requirements are normally specified, and the form in which measured interconnect is handed to simulation for system-level analysis.

The dominant practical difficulty is de-embedding. The measurement includes the cables, probes, launch structures, and test fixtures used to reach the device, and separating the interconnect of interest from that surrounding hardware is essential to a meaningful result. Calibration and de-embedding methods based on purpose-built test coupons address this, and designing those coupons alongside the board is part of the job rather than an afterthought. Sanity checks on the resulting data, notably passivity and causality, catch a large fraction of the errors that would otherwise propagate silently into simulation.

Electromagnetic Simulation

Three-dimensional full-wave solvers, using finite element, finite-difference time-domain, or method-of-moments formulations, compute the field distribution around a structure and extract its S-parameters. They are the only tools that reliably capture plane-cavity resonance, via-to-via coupling in dense fields, and radiation. Their cost is computational, so they are applied to bounded structures such as a via transition, a connector launch, or a plane crossing, rather than to a whole board.

Two-dimensional and quasi-three-dimensional field solvers handle uniform cross sections and are what layout tools use for everyday impedance calculation. Lumped equivalent circuits, extracted from full-wave results or from closed-form approximations, run quickly enough for the many-iteration studies used in optimization and remain accurate as long as the structure stays electrically short. The customary workflow combines all three: full-wave models for the critical structures, transmission line models for the uniform runs between them, and behavioral driver and receiver models at the ends.

A Practical Workflow

A workable sequence starts with the driver's rise time, which sets the bandwidth to which everything must be accurate, and with the channel's return loss and insertion loss requirements, which set the pass criteria. A pre-layout study then establishes stackup, impedance targets, and the via and launch geometries the design will use, so that the layout is drawn around structures already known to work. After layout, the critical structures are extracted and simulated, cascaded with the uniform line segments and the vendor models for connectors and packages, and evaluated as a complete channel through eye-diagram or statistical analysis.

Correlation closes the loop. Test coupons carrying the same via and launch structures as the production board are measured and compared against their simulated S-parameters, which validates the material properties, the roughness model, and the fabricator's etch behavior. Where measurement and simulation disagree, the disagreement itself is informative: an unexplained resonance usually points to a return path problem, and a broadband loss discrepancy usually points to a dielectric or roughness parameter that needs correcting. Simulation that has never been correlated should be treated as a comparative tool rather than as a prediction of absolute margin.

Conclusion

Discontinuity analysis rests on one physical idea applied consistently: wherever the impedance seen by a traveling wave changes, part of that wave turns around. Vias, pads, antipads, plane transitions, connector launches, corners, meanders, and width changes are all instances of the same mechanism differing in magnitude and in electrical length, and the reflection coefficient describes every one of them.

The practical skill lies in proportion. The features that dominate a real channel are via stubs, connector launches, and return path interruptions, and these deserve simulation, careful geometry, and correlation against measurement. Corners and teardrops belong to a second tier whose importance is frequently overstated on digital boards and genuinely first-order only at microwave frequencies. Directing effort by the size of the effect, rather than by the age of the design rule, is what separates effective signal integrity work from ritual.

Because edge rates continue to fall, the boundary between what can be ignored and what must be analyzed keeps moving, and it moves for existing designs whenever a faster component is substituted. Deciding the analysis bandwidth from the driver's rise time, controlling the discontinuities that dominate, verifying the result against measured coupons, and revisiting those judgments whenever the silicon changes is what keeps an interconnect trustworthy as data rates rise.

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