Electronics Guide

The Physical Mechanism

When a signal travels along a transmission line with characteristic impedance Z₀ and encounters a termination or discontinuity with impedance Z_L, the boundary conditions require continuity of voltage and current. However, the different impedances cannot simultaneously satisfy these conditions with only the incident wave. To maintain electromagnetic boundary conditions, a reflected wave is generated that travels back toward the source.

The incident wave carries energy forward with specific voltage and current relationships determined by the line impedance. At the discontinuity, the load impedance imposes different voltage-current relationships. The reflected wave adjusts the total voltage and current at the boundary to satisfy both the transmission line equations and the load impedance simultaneously.

Key concepts in reflection physics include:

• Incident wave: The original signal traveling toward the discontinuity, with voltage V_i and current I_i related by the characteristic impedance
• Reflected wave: The portion of signal energy bouncing back, with voltage V_r and current I_r
• Transmitted wave: The signal energy that continues past the discontinuity (in multi-section systems)
• Voltage superposition: The total voltage at any point equals the sum of incident and reflected wave voltages
• Current superposition: The total current equals the incident current minus the reflected current (due to opposite propagation direction)

Energy Conservation

Reflections obey energy conservation principles. The incident power must equal the sum of reflected power and absorbed power in the load. For a lossless transmission line, no energy is lost during propagation, so all incident energy either reflects back or dissipates in the load impedance.

For a real characteristic impedance, the power carried by each wave scales with the square of its voltage amplitude:

• P_incident = (V_i)² / Z₀
• P_reflected = (V_r)² / Z₀ = |Γ|² × P_incident
• P_absorbed = P_incident − P_reflected = (1 − |Γ|²) × P_incident

The voltages in these expressions are root-mean-square values for sinusoidal excitation, or step amplitudes for a launched edge. The ratios P_reflected / P_incident = |Γ|² and P_absorbed / P_incident = 1 − |Γ|² hold regardless of the amplitude convention, which is why they appear so often in link budgets.

Perfect impedance matching (Z_L = Z₀) results in zero reflected power, with all incident energy absorbed by the load. Conversely, an open circuit (Z_L = ∞) or short circuit (Z_L = 0) reflects all incident energy back, differing only in the phase of the reflected wave. A reactive load also returns all the incident power in the steady state, because an ideal inductor or capacitor dissipates nothing; it simply delays the return.

When Reflections Matter: Electrical Length and Rise Time

Not every interconnect needs transmission line treatment. Reflections matter when the round-trip delay of the interconnect is comparable to the signal's transition time, because only then do reflected waves arrive late enough to distort the edge rather than blend into it.

The usual criterion compares one-way flight time t_flight to rise time t_r. A widely used conservative threshold treats the line as electrically long when:

t_flight > t_r / 6

Some authors use t_r / 2 for a less strict test. Either way, the trigger is edge speed, not clock frequency. A 100 MHz clock with a 200 ps edge behaves like a high-speed signal; a 1 GHz clock with a deliberately slowed edge may not.

Signals propagate at roughly 6 inches per nanosecond in FR-4 stripline and closer to 7 inches per nanosecond in microstrip, where part of the field travels in air. Applying the t_r / 6 rule at 6 inches per nanosecond gives the following critical lengths:

• 1 ns edge: about 1 inch
• 500 ps edge: about 0.5 inch
• 100 ps edge: about 0.1 inch
• 30 ps edge: about 0.03 inch, which is shorter than a typical via or component pad

The last row explains why modern designs worry about structures that were once invisible. Once edges fall below roughly 50 ps, vias, pads, and connector footprints become distributed structures in their own right, and the reflection mechanisms described in the rest of this article dominate the signal quality budget.

Mathematical Definition

The voltage reflection coefficient (Γ, Greek letter gamma) is defined as the ratio of reflected voltage to incident voltage at the discontinuity:

Γ = V_r / V_i = (Z_L - Z₀) / (Z_L + Z₀)

Where:

• Γ = voltage reflection coefficient (dimensionless; −1 to +1 for passive real impedances, and |Γ| ≤ 1 for any passive load)
• V_r = reflected voltage wave amplitude
• V_i = incident voltage wave amplitude
• Z_L = load impedance at the discontinuity
• Z₀ = characteristic impedance of the transmission line

The current reflection coefficient has the same magnitude but opposite sign: Γ_i = -Γ. This sign difference reflects the fact that reflected current flows in the opposite direction to incident current.

Special Cases and Boundary Conditions

Several important cases illustrate reflection behavior:

• Matched load (Z_L = Z₀): Γ = 0, no reflection occurs, all energy absorbed by load
• Open circuit (Z_L = ∞): Γ = +1, voltage doubles at open end, current becomes zero
• Short circuit (Z_L = 0): Γ = -1, voltage becomes zero, current doubles at short
• Purely resistive mismatch: 0 < |Γ| < 1, partial reflection with no phase shift beyond 0° or 180°
• Reactive load (complex Z_L): Complex Γ with magnitude ≤ 1, reflection includes phase shift

For a 50-ohm transmission line terminated with various loads:

• 25-ohm load: Γ = (25-50)/(25+50) = -0.33, about 33% reflection with inverted polarity
• 75-ohm load: Γ = (75-50)/(75+50) = +0.20, about 20% reflection with same polarity
• 100-ohm load: Γ = (100-50)/(100+50) = +0.33, about 33% reflection with same polarity

Return Loss and Related Metrics

The reflection coefficient relates to several commonly used signal integrity metrics:

Return Loss (RL) expresses the reflected power relative to the incident power. Because the magnitude of the reflection coefficient is at most one for a passive load, the formula's leading minus sign makes return loss a positive decibel value:

RL = -20 × log₁₀(|Γ|) dB

Higher return loss (a larger positive dB value) indicates better impedance matching, because more of the incident power is delivered to the load rather than reflected. For example, Γ = 0.1 corresponds to RL = 20 dB, while Γ = 0.01 gives RL = 40 dB. Typical design targets range from 15 dB (moderate quality) to 30 dB or more (high-performance systems).

At the input port of a network measured against Z₀, the reflection coefficient is the scattering parameter S₁₁, so return loss is simply that parameter's magnitude in decibels with the sign flipped: RL = −20 log₁₀|S₁₁| dB. Because a passive network returns less power than it receives, |S₁₁| expressed in decibels is negative and RL is positive. Vector network analyzer plots almost always show the negative quantity 20 log₁₀|S₁₁|, so a specification of "20 dB return loss" and a trace reading "−20 dB S₁₁" describe the same match. Confusing the two signs is a common source of misread specifications.

Voltage Standing Wave Ratio (VSWR) describes the voltage variation along a mismatched line:

VSWR = (1 + |Γ|) / (1 - |Γ|)

A perfectly matched line has VSWR = 1:1, while increasing mismatch produces higher ratios like 1.5:1, 2:1, or worse. VSWR is the ratio of the maximum to the minimum voltage amplitude in the standing wave pattern along a mismatched line, so it is measurable with nothing more than a slotted line and a detector. That practical heritage explains its persistence in RF work, while return loss and S₁₁ dominate digital signal integrity.

The three metrics are different views of the same quantity:

• |Γ| = 0.01: RL = 40 dB, VSWR ≈ 1.02:1
• |Γ| = 0.056: RL = 25 dB, VSWR ≈ 1.12:1
• |Γ| = 0.1: RL = 20 dB, VSWR ≈ 1.22:1
• |Γ| = 0.2: RL ≈ 14 dB, VSWR = 1.5:1
• |Γ| = 0.33: RL ≈ 9.5 dB, VSWR = 2:1

Note how quickly the decibel scale compresses: the difference between an excellent match and a mediocre one spans only a few percent of reflected voltage but tens of decibels of return loss.

Termination Mismatches

The most obvious source of reflections is improper line termination. When a transmission line ends at a component or connector whose input impedance differs from the line's characteristic impedance, reflections occur.

Common termination scenarios include:

• Unterminated lines: High-impedance CMOS inputs approximate open circuits at low frequency, causing nearly full reflection (Γ ≈ +1) and doubling the voltage at the receiver
• Capacitive loads: IC input capacitance creates frequency-dependent impedance, appearing high at low frequencies but decreasing at high frequencies
• Wrong resistor value: Using 75-ohm termination on a 50-ohm line produces 20% reflections
• Series termination at wrong end: Series resistors should be placed at the source, not the load
• Temperature-dependent resistance: Resistor tolerance and temperature coefficients cause impedance variations

Trace Geometry Changes

PCB trace geometry directly determines characteristic impedance. Any change in trace dimensions creates an impedance discontinuity and potential reflection point.

Geometric mismatch sources include:

• Width changes: Transitioning from 5-mil to 10-mil trace width alters impedance, potentially by 10-20 ohms depending on stackup
• Layer transitions: Moving from outer layer (microstrip) to inner layer (stripline) changes field distribution and impedance
• Reference plane gaps: Breaks in ground or power planes under signal traces dramatically increase local impedance
• Copper weight variation: Different copper thickness between layers affects trace cross-section
• Routing corners: Sharp 90-degree bends create local impedance changes, though effects are minor at moderate frequencies

Modern PCB design tools include impedance calculators that account for trace width, height, dielectric properties, and reference plane spacing. Maintaining consistent geometry is essential for controlled impedance routing.

Dielectric Property Variations

The dielectric constant (εr) of PCB substrate material directly affects characteristic impedance through the relationship Z₀ ∝ 1/√εr. Any spatial or frequency variation in dielectric properties causes impedance changes.

Dielectric-related mismatches include:

• Material transitions: Moving from FR-4 (εr ≈ 4.3) to Rogers 4350B (εr ≈ 3.5) changes impedance by approximately 10%
• Prepreg thickness variation: Manufacturing tolerances in dielectric thickness affect impedance
• Frequency dispersion: Dielectric constant decreases with frequency in most materials, causing impedance to rise at higher frequencies
• Moisture absorption: Humid environments increase effective dielectric constant, lowering impedance
• Temperature effects: Dielectric properties change with temperature, typically increasing εr as temperature rises

Stub Topologies

A stub is classified by how it connects to the main line, not by its physical orientation on the board.

Shunt stubs connect in parallel with the through path: the signal reaches a junction, and one branch dead-ends. Nearly every unintentional stub in a printed circuit board is of this type. Common examples include the unused portion of a via barrel below the destination layer, a trace that overshoots a component pad, an unloaded test point, a spur to an unused connector pin, and the abandoned leg of a multidrop bus. Because the branch presents its input impedance in parallel with the through path, a low stub impedance drags the junction impedance down and diverts energy back toward the source.

Series stubs are inserted in line with the signal, so the through current must pass through the stub's impedance. These are almost always deliberate: series open- and short-circuited stubs are classic RF impedance matching elements, and they appear in filters and bias networks. They rarely arise by accident in digital layout.

The distinction matters because the two behave oppositely. A quarter-wave open-circuited stub in shunt looks like a short at the junction and produces a deep transmission notch, whereas the same stub in series looks like an open and passes the signal. Since accidental board stubs are shunt stubs, the shunt case governs practical signal integrity.

Stub resonance occurs when the electrical length equals odd multiples of a quarter-wavelength. For an open-ended shunt stub, these resonances transform the high impedance at the far end into a low impedance at the junction, creating a notch in transmission. The notch frequencies are approximately:

f_resonant = (2n − 1) × v / (4 × L_stub)

Where n = 1, 2, 3... for successive resonances, v is propagation velocity in the stub, and L_stub is the physical stub length. Insertion loss begins to degrade well below the first null, so a stub whose quarter-wave resonance sits at twice the Nyquist frequency of a link is already costing margin.

Via Stubs

Vias create particularly problematic stubs in multi-layer PCBs. When a signal transitions from one layer to another, the via barrel typically extends through the entire board thickness. The unused portion of via beyond the destination layer forms a stub that radiates and reflects signals.

Signals travel through FR-4 at roughly v = 11.8 / √εr inches per nanosecond, or about 5.9 inches per nanosecond for εr ≈ 4. The first transmission null of an open stub falls at v / (4 × L_stub). Two cases bracket the practical range:

• Thin board, worst-case stub: On a 62-mil board, a signal entering on the top layer and leaving near the top leaves a stub approaching the full 62 mils. The null lands near 5.9 / (4 × 0.062) ≈ 24 GHz.
• Thick backplane: On a 200-mil backplane, a signal that drops to a layer 50 mils below the surface leaves a 150-mil stub, putting the null near 5.9 / (4 × 0.150) ≈ 10 GHz.

A 24 GHz null looks safely out of band, and for slow logic it is. The controlling number, however, is the signal's knee frequency, approximately 0.35 / t_r, above which an edge carries little energy. A 1 ns edge has a knee near 350 MHz and is essentially blind to either stub. A 50 ps edge has a knee near 7 GHz, and a 30 ps edge near 12 GHz, so both interact strongly with the backplane stub and begin to feel the thin-board stub.

Serial links make the case sharper because their spectra concentrate near the Nyquist frequency, which is half the bit rate for binary signaling. A 25 Gbps binary link has its Nyquist point at 12.5 GHz, squarely inside the degraded region of a 150-mil stub. This is why back-drilling became standard practice on thick backplanes as line rates passed roughly 5 to 10 Gbps, while thin daughtercards often tolerate full-length through vias.

Mitigation techniques include:

• Back-drilling: Mechanically counterboring the unused portion of a plated via after fabrication, leaving a residual stub typically in the 5 to 15 mil range set by drill registration and depth tolerance
• Blind vias: Vias that extend only partway from an outer layer, ending at the destination layer and leaving no stub
• Buried vias: Layer-to-layer connections entirely inside the stackup that never reach an outer surface
• Layer assignment: Routing the highest-rate nets on layers that minimize the leftover barrel, which costs nothing in fabrication
• Via-in-pad: Placing the via directly in the component land, removing the short trace stub that otherwise runs from pad to via
• Non-functional pad removal: Deleting the unused pads on layers the via does not connect to, which reduces capacitive loading and slightly raises via impedance

Component Lead and Pad Stubs

Surface mount component pads and through-hole component leads create small but significant stubs at high frequencies. The pad area beyond the actual connection point acts as a short transmission line stub.

Consider a 50-mil land, roughly the overall footprint length of an 0805 chip resistor. On a microstrip with an effective dielectric constant near 3, the wavelength at 10 GHz is about 680 mils, so the land spans on the order of 30 degrees of electrical length. That is enough to cause measurable reflection and phase shift, which is why precision high-frequency circuits use the smallest practical case sizes and tightly controlled land geometry.

Through-hole components present even larger stub problems, as component leads extend through the board and may protrude on the opposite side. The combination of lead inductance and stub effects limits through-hole component usage in high-speed designs.

Via Barrel Impedance

The via barrel itself has characteristic impedance different from the connected traces. Via impedance depends on barrel diameter, anti-pad opening in reference planes, and the number and spacing of nearby ground vias.

To a first approximation, the barrel and the surrounding anti-pad form a short coaxial line, so the standard coaxial expression applies:

Z_via ≈ (60 / √εr) × ln(D_antipad / D_barrel)

Where D_antipad is the anti-pad diameter cleared in the reference planes and D_barrel is the plated barrel diameter. The anti-pad must always be larger than the signal pad, which in turn is larger than the barrel; otherwise the via would short to the plane.

A conventional through via might have:

• Barrel diameter: 10 mils after plating
• Pad diameter: 20 mils on connected signal layers
• Anti-pad diameter: 40 mils of clearance in reference planes

With εr ≈ 4.2, this geometry gives (60 / 2.05) × ln(40 / 10) ≈ 41 ohms. The pads add shunt capacitance that the coaxial formula ignores, pulling the effective impedance lower still, so real through vias commonly measure in the 25 to 45 ohm range. That sits well below a 50-ohm single-ended trace and far below the 50-ohm-per-side impedance of a 100-ohm differential pair, so a via typically reads as a downward dip on a TDR impedance profile.

Two levers raise via impedance toward the trace value: enlarging the anti-pad, which the logarithm rewards only slowly, and shrinking the pads. Enlarging the anti-pad has a cost, since it carves a larger hole in the reference plane and disturbs the return current of neighboring traces. More accurate design work requires 3D field solvers that account for pad stack geometry, nearby ground vias, and the full reference plane arrangement.

Capacitive and Inductive Effects

Vias exhibit both capacitive and inductive parasitics that affect signal transmission:

Via capacitance arises from the pad area on each layer, acting as a parallel-plate capacitor to adjacent reference planes. Total via capacitance equals the sum of contributions from all layers:

C_via ≈ Σ (ε₀ × εr × A_pad / h)

Where A_pad is pad area, h is dielectric thickness to the reference plane, and the sum includes every layer carrying a pad. Typical totals range from about 0.3 to 1.0 pF depending on layer count, pad size, and anti-pad clearance. Removing non-functional pads eliminates most of the terms in this sum, which is why the practice is standard on high-speed boards.

Via inductance results from current flowing along the via barrel and returning through nearby ground vias or plane connections. A widely used engineering estimate for an isolated via is:

L_via ≈ 5.08 × h × [ln(4h / D_barrel) + 1] nH, with h and D_barrel in inches

For a 62-mil board and a 10-mil barrel this gives about 1.3 nH. The estimate assumes a distant return path, so it is pessimistic for a well-stitched design: ground vias placed close to the signal via shrink the current loop and can cut the effective inductance by half or more. Practical values fall in the range of roughly 0.3 to 1.5 nH.

Whether a via behaves as a capacitive or an inductive discontinuity depends on which parasitic dominates, and the comparison is best made through the characteristic impedance of the equivalent short line, √(L_via / C_via):

• Capacitance dominant: Large pads, tight anti-pads, and many layers push √(L/C) below the trace impedance. The via appears as a low-impedance dip on a TDR trace and as a shunt capacitor in a lumped model. Most conventional through vias fall here.
• Inductance dominant: Thick boards with small pads, non-functional pads removed, and generous anti-pads push √(L/C) above the trace impedance. The via appears as an impedance bump and behaves as a series inductor.

Because the parasitics are distributed rather than lumped, the two also resonate. The lumped picture stays valid only while the via is electrically short compared with the signal's rise time; beyond that point the via must be treated as a transmission line segment, and its stub resonances, not its lumped L and C, set the behavior.

Return Current Path Discontinuities

When a signal via transitions between layers, the return current must also transition between reference planes. If no dedicated ground via exists nearby, return current must flow laterally to find a distant via, creating a large current loop with high inductance.

Best practices for via return paths include:

• Ground via placement: Position ground vias within 20-30 mils of signal vias to provide low-inductance return paths
• Symmetry in differential pairs: Place ground vias symmetrically between differential pair vias to maintain impedance balance
• Via stitching: Connect adjacent reference planes with via arrays to provide multiple return current paths
• Coaxial via structures: Surround high-speed signal vias with rings of ground vias for the ultimate in return path control

Connector Impedance Characteristics

High-speed connectors are designed with target characteristic impedances matching common system impedances (50 ohms single-ended, 85-100 ohms differential). However, achieving consistent impedance through the complex 3D connector geometry presents significant challenges.

Connector impedance variations arise from:

• Pin geometry: Contact shape, plating thickness, and pin-to-pin spacing determine impedance through the connector body
• Dielectric material: Connector plastic housings have different dielectric constants than PCB substrate
• Ground structure: Ground pin placement and internal shielding affect field distribution
• PCB launch: The transition from PCB trace to connector footprint creates a localized impedance change
• Mating discontinuity: The contact point between mating connectors introduces mechanical and electrical variability

Impedance uniformity varies widely by class. General-purpose connectors often hold only about ±10 percent through their structure, so a part specified at 100 ohms differential may swing between 90 and 110 ohms along its length, creating several reflection points in series. Purpose-built multi-gigabit connectors do considerably better, but even they concentrate their residual mismatch at the two ends, where the controlled geometry inside the connector meets the PCB footprint. In practice the launch region on the board, not the connector body, is often the dominant discontinuity, and it is the part the system designer actually controls.

Connector Stub and Crosstalk Issues

Multi-pin connectors create additional problems beyond simple impedance discontinuity:

Unused pin stubs: Connectors with more pins than actively used signals create stubs from every unused contact. These stubs couple to active signals through mutual capacitance and inductance, causing both reflections and crosstalk.

Pin-to-pin coupling: Adjacent pins in dense connectors couple electromagnetic energy between signals. This crosstalk appears as additional noise and creates reflections when coupled signals encounter mismatches.

Ground bounce: Shared ground pins carry return currents for multiple signals. Simultaneous switching creates voltage variations on ground pins, appearing as common-mode noise that reflects at mismatches.

Connector manufacturers address these issues through:

• Increased ground-to-signal pin ratios (1:1 or higher for critical applications)
• Differential pair routing optimization within the connector
• Internal shielding structures to reduce crosstalk
• Carefully controlled impedance through precision manufacturing
• Shortened connector bodies to minimize discontinuity length

Cable Connector Interfaces

When cables connect between two boards, the complete signal path includes:

• PCB trace 1 (source board)
• Connector 1 on source board
• Cable assembly with its own impedance
• Connector 2 on destination board
• PCB trace 2 (destination board)

Each transition creates potential mismatches. For example, a system might use 50-ohm PCB traces, connectors varying from 45-55 ohms, and cable impedance of 50 ±5 ohms. The accumulated reflections degrade signal quality, particularly if impedance changes occur in the same direction at multiple points.

Proper cable assembly design includes impedance matching at both ends, typically through careful PCB layout at the connector footprint. Some designs use back-terminated traces or series resistance to damp reflections from cable connector systems.

Wire Bond Transitions

Traditional wire-bonded packages use fine gold or copper wires, typically 0.8 to 2 mils in diameter, to connect die pads to package leads or substrate traces. These wire bonds introduce significant inductance and impedance discontinuities.

A useful rule of thumb puts bond wire inductance near 1 nH per millimeter of length, with the exact value depending on wire diameter, loop height, and the proximity of the return path. A 3 mm bond wire therefore contributes roughly 3 nH. At 10 GHz that inductance presents about 188 ohms of reactance, far above typical 50-ohm system impedances, and even at 1 GHz it presents nearly 19 ohms in series with the signal.

The high inductance causes several problems:

• Reflection at the bond: The inductive impedance mismatches with both the die and package impedances
• Resonances: Bond wire inductance resonates with pad capacitances, creating frequency-dependent behavior
• Ground bounce: Shared ground bond wires carry return current for multiple signals, creating common impedance coupling
• Simultaneous switching noise: Multiple drivers switching together create voltage variations through bond wire inductance

Wire bond limitations restrict their use in applications above a few GHz. Multiple parallel bond wires reduce inductance but cannot overcome fundamental geometric constraints.

Flip-Chip and Controlled Collapse Chip Connection

Flip-chip technology directly connects die pads to package substrate through solder bumps, eliminating wire bonds. The much shorter connection length (typically 50-100 microns) dramatically reduces inductance to approximately 50-100 pH per bump.

Flip-chip advantages for signal integrity include:

• Low inductance: Short bump height provides minimal series inductance
• Controlled impedance: Bump array geometry can be designed for specific impedance characteristics
• Dense ground distribution: Ground bumps interspersed with signal bumps provide excellent return paths
• Reduced package size: Eliminates peripheral wire bond area, allowing smaller packages

However, flip-chip introduces its own discontinuities. The solder bump itself, typically 100-150 microns in diameter, creates a capacitive element. The transition from on-die metal to bump to package substrate involves multiple material and geometry changes.

Advanced 2.5D and 3D packages use microbumps roughly 10 to 25 microns across at pitches of about 40 microns and below, cutting parasitics further for die-to-die interfaces on silicon interposers and bridges. Hybrid bonding pushes the trend to its limit by joining copper pads directly, with no solder bump at all, at pitches of a few microns. At that scale the interconnect parasitics largely stop being the limiting discontinuity, and attention shifts to the on-die and interposer routing.

BGA Package-to-PCB Interface

Ball Grid Array packages connect to PCBs through solder ball arrays on the package underside. The BGA interface introduces impedance discontinuities from multiple sources:

Ball impedance: The solder ball itself has inductance (typically 50-200 pH) and forms part of the signal path. Ball diameter, height, and spacing determine these parasitics.

PCB land geometry: The land on the PCB has a different impedance than the connecting trace, because its broad copper area sits closer to the reference plane than a narrow trace does and therefore adds shunt capacitance. Common practice sizes a non-solder-mask-defined land somewhat smaller than the ball, on the order of 80 percent of the ball diameter, so that solder wets the pad sides and the joint fillets properly; solder-mask-defined lands are instead set by the mask opening. Either way, the land is a local capacitive discontinuity that must be accounted for in the escape design.

Via transition: Most BGA connections require vias to escape from the dense ball array to routing layers. These vias add the discontinuities discussed earlier.

Trace fanout: Traces fanning out from the BGA footprint often change width to squeeze between balls, creating impedance variations.

High-speed BGA design requires careful attention to:

• Via-in-pad techniques to minimize stub length
• Controlled impedance trace widths accounting for via and pad discontinuities
• Ground ball placement adjacent to high-speed signals
• Escape routing that maintains differential pair symmetry
• Package substrate design coordinated with PCB design for consistent impedance through the complete path

Reflection Sequence and Timing

When a signal encounters multiple discontinuities, reflections bounce back and forth between mismatches, creating complex waveforms. Each reflection arrives at different times determined by discontinuity spacing and propagation velocity.

Consider a simple example: a source drives a line with characteristic impedance Z₀ that connects to a load Z_L, with a discontinuity of impedance Z_D midway between source and load.

The reflection sequence proceeds as:

1. Initial wave travels from source to midpoint discontinuity
2. Partial reflection at discontinuity returns to source; partial transmission continues to load
3. Transmitted wave reaches load, reflects based on load impedance
4. Load reflection travels back, encountering discontinuity again
5. Discontinuity partially reflects (toward load) and partially transmits (toward source)
6. Wave reaching source reflects based on source impedance
7. Process continues with decreasing amplitude as energy dissipates

Each reflection multiplies by the relevant reflection coefficient at each discontinuity. With typical reflection coefficients of 0.1 to 0.3, reflections decrease rapidly after several round trips.

Reflection Addition and Cancellation

Multiple reflections add vectorially at any point along the transmission line. Depending on timing and polarity, reflections can add constructively (increasing distortion) or destructively (partially canceling).

Critical scenarios include:

Resonant enhancement: When discontinuity spacing equals multiples of half-wavelength, reflections arrive in-phase with incident signals, creating standing wave patterns and voltage peaks. This occurs at frequencies f = n × v / (2 × L), where L is the spacing between discontinuities.

Null points: At odd multiples of quarter-wavelength spacing, certain reflections arrive out-of-phase, potentially canceling. However, this cancellation occurs only at specific frequencies and cannot be relied upon for broadband signals.

Overshoot accumulation: Multiple positive reflections arriving close together in time create voltage overshoot exceeding levels from any single reflection. This is particularly problematic near clock edges where timing is critical.

Ringing: Reflections bouncing between two strong discontinuities (like unterminated source and load) create oscillatory ringing that takes many bit periods to settle.

Dominant Reflection Identification

Not all discontinuities contribute equally to signal degradation. Identifying dominant reflection sources focuses mitigation efforts on the most impactful problems.

Factors determining reflection impact include:

• Reflection coefficient magnitude: Larger impedance mismatches create stronger reflections
• Distance from observation point: Nearby discontinuities affect signal quality more than distant ones due to less attenuation
• Number of reflections: A discontinuity that signals traverse multiple times (like a source termination) impacts quality more than single-pass discontinuities
• Electrical length relative to signal bandwidth: A discontinuity much shorter than the spatial extent of the rising edge behaves as a lumped parasitic and produces a brief, partially self-canceling glitch; one comparable to or longer than the edge acts as a transmission line section and produces a full-amplitude reflection. The usual threshold places the boundary near one-tenth of a wavelength at the knee frequency

Time-domain reflectometry (TDR) measurements identify reflection locations and magnitudes, allowing designers to focus on the worst discontinuities. Simulation tools can also perform sensitivity analysis to rank discontinuity impacts.

Constructing Lattice Diagrams

A lattice diagram uses a two-dimensional graph with:

• Vertical axis: Represents distance along the transmission line, from source (bottom) to load (top)
• Horizontal axis: Represents time, advancing left to right
• Diagonal lines: Represent traveling waves, with slope determined by propagation velocity
• Annotations: Voltage amplitudes or reflection coefficients label each wave segment

Construction procedure:

1. Draw vertical lines at source and load positions
2. Calculate source and load reflection coefficients: Γ_s and Γ_L
3. Draw initial wave from source to load (diagonal line up and right)
4. At load, multiply by (1 + Γ_L) for transmitted voltage, and draw reflection returning (diagonal line down and right) with amplitude × Γ_L
5. At source, multiply returning wave by Γ_s and draw new reflection toward load
6. Continue process until reflections become negligibly small

Each reflection multiplies the previous amplitude by the reflection coefficient at the boundary. For example, with Γ_s = 0.2 and Γ_L = -0.3, the sequence might be: 1.0 (initial), -0.3 (first load reflection), -0.06 (first source reflection), 0.018 (second load reflection), etc.

Reading and Interpreting Lattice Diagrams

Lattice diagrams reveal important system behavior:

Voltage at any point and time: To find the voltage at a specific location and time, draw a vertical line at that time and note all wave segments crossing it at the desired position. Sum all contributions (incident and reflected waves) to obtain total voltage.

Settling time: The time required for reflections to decay to acceptable levels is visible as the point where diagonal lines become too small to distinguish. Systems with small reflection coefficients settle quickly; large mismatches cause prolonged ringing.

Worst-case voltage: Maximum voltage occurs when multiple reflections arrive simultaneously with the same polarity. The diagram shows when and where this occurs.

Effect of source and load impedances: The reflection coefficients Γ_s and Γ_L directly determine how rapidly reflections decay. Matched terminations (Γ = 0) eliminate that end's reflections entirely, visible as diagonal lines stopping at matched boundaries.

Complex System Lattice Diagrams

Lattice diagrams extend to multi-section transmission lines with multiple discontinuities. Each discontinuity adds a vertical line in the diagram where waves partially reflect and partially transmit according to the local reflection and transmission coefficients.

For a system with source impedance Z_s, line 1 with impedance Z₁, discontinuity impedance Z_d, line 2 with impedance Z₂, and load impedance Z_L, the diagram includes reflection coefficients at four boundaries plus two transmission coefficients at the internal discontinuity.

The complexity increases rapidly, but the fundamental principle remains: trace each wave segment, apply appropriate reflection/transmission coefficients at boundaries, and sum all contributions at the point of interest.

Modern simulation tools automate this process, but manually constructing lattice diagrams for simple cases builds intuition about reflection behavior and helps verify simulation results.

Time-Domain Reflectometry

Time-domain reflectometry (TDR) is a measurement technique that sends a fast step voltage into a transmission line and observes the reflected signal. Reflections return from impedance discontinuities at times proportional to their distance from the measurement point.

TDR operating principles:

• Step generation: A pulse generator launches a fast voltage step into the transmission line. General-purpose instruments produce edges of roughly 100 to 200 ps, while sampling-oscilloscope TDR modules reach system rise times in the 25 to 35 ps range
• Reflection observation: An oscilloscope monitors voltage at the launch point, displaying incident plus reflected waves
• Distance calculation: Time delay to reflection corresponds to distance: d = (t × v) / 2, where the factor of 2 accounts for round-trip travel
• Impedance determination: Reflection amplitude indicates impedance change: Z = Z₀ × (1 + Γ) / (1 - Γ)

TDR reveals:

• Open circuits appear as positive steps in reflected voltage
• Short circuits appear as negative steps
• Capacitive loads show gradual voltage rise
• Inductive discontinuities create voltage spikes
• Distributed variations appear as sloped voltage changes

Spatial resolution is set by the system rise time, not by the sampling rate or the horizontal scale of the display. Two discontinuities merge into one feature unless they are separated by roughly:

d_min ≈ (t_r × v) / 2

The factor of two again accounts for the round trip. With a 30 ps system rise time and a propagation velocity of 6 inches per nanosecond, d_min is about 0.09 inch, so a via and the pad feeding it appear as a single blended discontinuity rather than two. Slower instruments resolve proportionally less. This limit is physical: no amount of averaging or interpolation separates features closer than the incident edge can distinguish, though deconvolution against a known reference improves the picture somewhat.

TDR remains invaluable for diagnosing fabrication defects, locating connector and cable problems, and verifying controlled impedance routing, provided its resolution limit is respected when interpreting closely spaced features.

Transient Response Analysis

Digital signals are inherently transient, consisting of edges and transitions rather than steady-state sine waves. Analyzing transient response shows how reflections affect signal quality metrics like rise time, overshoot, and ringing.

Key transient phenomena include:

Edge degradation: Reflections interfere with clean edges, causing staircase-like waveforms as each reflection adds to the transition. Severe reflections can create multiple false crossings of logic thresholds.

Overshoot and undershoot: When reflections arrive during edge transitions with the same polarity as the edge, they add to create voltage excursions beyond final values. Positive overshoot stresses receiver input protection; negative undershoot can forward-bias substrate diodes.

Ringing: Oscillatory behavior from reflections bouncing between two discontinuities separated by a line of length L. When both ends reflect with the same sign, as with an open at each end or a short at each end, the round trip returns the wave in phase and the ringing frequency is approximately v / (2 × L). When the ends reflect with opposite signs, the common case of a low-impedance driver feeding a high-impedance receiver, the wave needs two round trips to return in phase and the frequency drops to about v / (4 × L). Ringing amplitude depends on the magnitudes of the two reflection coefficients, and the decay rate depends on their product.

Inter-symbol interference: In high-speed serial data, reflections from one bit period persist into subsequent bits, causing accumulated distortion. Eye diagram closure results when ISI becomes severe.

Settling Time Calculations

Settling time quantifies how long reflections take to decay to acceptable levels. This parameter determines maximum signaling rate and affects timing budget analysis.

For a transmission line of length L with source reflection coefficient Γ_s and load reflection coefficient Γ_L, each round trip reduces reflection amplitude by the product Γ_s × Γ_L. After n round trips, the reflection amplitude is:

V_n = V_initial × (Γ_s × Γ_L)^n

To settle to within a fraction ε of the final value requires:

n = ln(ε) / ln(|Γ_s × Γ_L|)

Each round trip takes time 2L/v, so total settling time is:

t_settle = (2L/v) × ln(ε) / ln(|Γ_s × Γ_L|)

For example, with L = 10 inches, v = 6 inches/ns, Γ_s = 0.2, Γ_L = -0.3, and settling to within 1% (ε = 0.01):

• Round-trip time = 2 × 10 / 6 = 3.33 ns
• Magnitude of the reflection product = |0.2 × (−0.3)| = 0.06
• Required round trips = ln(0.01) / ln(0.06) ≈ 1.64
• Settling time ≈ 3.33 × 1.64 ≈ 5.5 ns

The result is an estimate rather than an exact figure, since reflections arrive in discrete steps rather than decaying continuously and the calculation ignores line loss, which speeds settling. It nonetheless makes the design consequence clear: this modest pair of mismatches costs more than five nanoseconds of settling on a ten-inch line, which alone forbids clocking that net much above 150 MHz. Halving the line length halves the settling time, and terminating either end so that its reflection coefficient approaches zero removes the round trips entirely. That is the arithmetic behind the general preference for short, terminated high-speed nets.

Relationship to Frequency-Domain Measurements

Time-domain and frequency-domain views describe the same physics and are related by the Fourier transform. Vector network analyzers measure S-parameters across frequency and then transform to a time-domain impedance profile, while sampling oscilloscopes measure the step response directly and transform the other way. Either instrument can produce either view, so the choice is driven by dynamic range, fixture de-embedding needs, and available equipment rather than by the quantity of interest.

Reading the same defect in both domains is a practical diagnostic skill:

• A single discontinuity appears as a step or bump in the TDR profile and as a broad ripple in the return loss curve, with the ripple spacing set by the distance from the reference plane.
• An open stub appears as a modest feature in TDR but as an unmistakable narrow null in insertion loss at its quarter-wave frequency, which is why stubs are usually easier to identify in the frequency domain.
• Two spaced discontinuities produce periodic ripple in both return loss and insertion loss. The ripple period Δf relates to the spacing L by Δf ≈ v / (2L), so measuring the period locates the reflecting pair even when TDR cannot resolve them individually.
• Distributed loss appears as a gradually rising TDR impedance profile along a long line and as a smooth downward slope in insertion loss, distinguishing it from the localized features that reflections create.

Because reflections remove energy from the through path, they register in insertion loss as well as return loss. A link that misses its loss budget is not necessarily suffering from dielectric or conductor loss; energy returned by an unnoticed stub or an impedance step reduces transmitted power the same way. Examining return loss alongside insertion loss separates the two causes, and it is the first check to run when measured loss exceeds the value the stackup predicts.

Impedance Matching

The most fundamental approach eliminates reflections by matching impedances throughout the signal path. Each scheme trades power, signal swing, and topology flexibility differently:

• Parallel termination: A resistor equal to Z₀ at the load absorbs the incident energy and sets Γ_L = 0. It preserves full edge rate and supports multidrop loads, but it draws steady DC current in one logic state and loads the driver continuously.
• Series termination: A resistor at the source brings R_driver + R_series up to Z₀ so that returning waves are absorbed rather than re-reflected. It costs no static power and needs only one component, but it works only for point-to-point nets, because the half-amplitude wave traveling down the line does not reach a valid logic level until the load reflection doubles it. Any receiver tapped partway along sees an invalid intermediate level for one round trip.
• Thevenin termination: A divider to the supply rails presents Z₀ to the line while biasing the idle level. It is common on open-drain and bused signals but dissipates power in both logic states.
• AC termination: A capacitor in series with the termination resistor blocks DC while matching at signal frequencies. It removes the static power penalty at the cost of an added time constant, so the capacitor must be large enough for the longest run of identical bits yet small enough not to blunt the edge.
• On-die termination: Calibrated termination integrated into the transceiver eliminates the stub between the package pin and a discrete resistor. It is now standard on memory interfaces and serial links, and it usually outperforms any external scheme at multi-gigabit rates.

Termination fixes reflections at the ends of a line. It does nothing for discontinuities in the middle, such as vias, connectors, and stubs, which is why the geometric measures that follow remain necessary even on a fully terminated net.

Controlled Impedance Design

Maintaining consistent impedance throughout the signal path prevents reflections from arising:

• Use PCB stackup calculators to design traces with target impedance
• Specify controlled impedance fabrication with testing to verify results
• Avoid unnecessary trace width changes
• Taper transitions smoothly when width changes are unavoidable
• Maintain consistent reference plane distance
• Coordinate PCB, connector, and cable impedances

Discontinuity Minimization

Design practices to reduce unavoidable discontinuities:

• Back-drill via stubs on the highest-rate signals, and assign layers so that leftover barrels are short even where back-drilling is not used
• Use blind and buried vias to eliminate through-board stubs where the stackup and budget allow
• Remove non-functional pads to cut via capacitance
• Minimize connector pin count and avoid leaving unused contacts connected to live traces
• Select connectors qualified for the intended data rate rather than the intended clock frequency
• Compensate via capacitance by locally narrowing the trace or enlarging the anti-pad, so the discontinuity is offset instead of merely tolerated
• Design component footprints with minimal pad overhang beyond the connection point
• Keep ground vias close to every signal via so the return current follows the signal through the layer change

These measures are ordered by leverage for most designs: stub length dominates, pad and anti-pad geometry comes next, and footprint detail matters mainly above roughly 10 GHz. Simulating the stackup before fabrication is far cheaper than diagnosing the assembled board.