Electronics Guide

Signaling Conventions and Complete Link Standards

It helps to separate two different kinds of "standard." The first kind defines only an electrical convention: how a driver produces a differential voltage, what common-mode level it sits on, how the line is terminated, and what a receiver must resolve. LVDS, current-mode logic (CML), positive emitter-coupled logic (PECL), and high-speed current steering logic (HCSL) belong to this group. They say nothing about packets, framing, or link management, and designers combine them freely with whatever protocol they need.

The second kind defines a complete link: electrical layer, line code, framing, flow control, link training, power states, and a compliance program. PCI Express, USB, HDMI, DisplayPort, and Ethernet belong to this group. Their electrical layers are usually CML or a close relative, but the specification that matters to a system designer covers far more than voltage swing. The distinction explains why an LVDS datasheet runs to a few dozen pages while the PCI Express base specification runs to well over a thousand.

A third distinction cuts across both groups: whether the link carries its own clock. Source-synchronous interfaces such as LVDS display links and MIPI D-PHY transmit a forwarded clock alongside the data, which simplifies the receiver but makes the design sensitive to skew between the clock and data pairs. Embedded-clock interfaces such as PCI Express, USB 3.x, and SerDes-based Ethernet scramble or block-code the data to guarantee transition density and recover timing from the data stream itself, trading receiver complexity for immunity to pair-to-pair skew.

Low-Voltage Differential Signaling (LVDS)

Electrical Definition

Low-Voltage Differential Signaling is defined by ANSI/TIA/EIA-644-A and, in a closely related form, by IEEE 1596.3 (SCI-LVDS). The driver is a current source of approximately 3.5 mA that is steered through a single 100-ohm termination resistor at the receiver, producing a nominal differential voltage of 350 mV about a 1.2 V common-mode level. Because the current is constant and merely changes direction, supply current is nearly independent of data rate, and the switching noise injected into the power distribution network is small.

Receivers threshold at plus or minus 100 mV, which leaves substantial margin against attenuation and noise, and they accept input voltages across a range wide enough to tolerate roughly one volt of ground shift between transmitter and receiver. That tolerance is one of the main practical reasons LVDS displaced single-ended interfaces in cabled and backplane applications.

Speed and Reach

TIA/EIA-644-A cites a recommended maximum signaling rate of 655 Mbps and a theoretical limit near 1.9 Gbps for the reference medium it describes. Commercial devices commonly exceed the recommended figure over short, well-controlled PCB traces, and serializer families built on LVDS-compatible electrical layers reach into the low gigabits per second. The practical ceiling is set by the channel rather than by the driver: the modest 350 mV swing has little headroom for the frequency-dependent loss of long FR-4 traces or thin cable, which is why interfaces beyond a few gigabits per second move to CML with equalization.

Variants and Applications

LVDS appears in flat-panel display links (FPD-Link and its successors), machine-vision interfaces such as Camera Link, high-speed data acquisition, telecom line cards, and general-purpose point-to-point links. Several derivative conventions adapt the same current-mode idea to different loads:

• Reduced Swing Differential Signaling (RSDS) and mini-LVDS cut the swing to roughly 200 mV for the short, highly parallel connections between a display timing controller and the column drivers of a TFT LCD panel, where the driver count makes power and EMI dominate.
• SubLVDS uses a similarly reduced swing and a lower common-mode level for image sensor outputs, which must operate from low core supplies.
• Bus LVDS (BLVDS) increases drive current so that a driver can work into a multidrop backplane terminated at both ends.
• Multipoint LVDS (M-LVDS), standardized as TIA/EIA-899, extends the idea to true multipoint buses with as many as 32 nodes. Because both bus ends are terminated, the driver sees an effective 50-ohm load and must supply roughly twice the current of a standard LVDS driver to maintain an adequate swing. The standard defines two receiver types: one with symmetric thresholds for maximum sensitivity and one with offset thresholds that produce a defined output when the bus is idle.

Current-Mode Logic, PECL, and HCSL

Current-Mode Logic

Current-mode logic is the workhorse electrical convention of multi-gigabit serial links. A CML driver is a differential pair with a tail current source that steers current through resistive loads, typically 50-ohm resistors integrated on the die and tied to the positive supply. Because the transistors never leave the active region and no node is charged through a high impedance, transitions are fast and the current drawn from the supply is nearly constant. Single-ended swings near 400 mV are typical, giving roughly 800 mV of differential swing peak to peak.

The on-die 50-ohm loads serve simultaneously as the driver load and as the source termination, and matching receiver-side terminations complete the transmission line. Links between separate devices are usually AC-coupled through series capacitors so that transmitter and receiver can operate at incompatible common-mode levels and from different supplies; the line code must then guarantee DC balance so that the coupling capacitors do not accumulate charge. CML is what sits behind almost every SerDes-based interface, including PCI Express, USB 3.x and USB4, SATA, and the high-speed Ethernet variants.

PECL and LVPECL

Positive emitter-coupled logic is emitter-coupled logic operated with the traditional negative supply rail tied to ground, so that signals reference the positive supply instead. PECL runs from 5 V and LVPECL from 3.3 V. The output stage is an emitter follower, and the outputs sit roughly 1.3 V below the positive supply with a single-ended swing near 800 mV, which is considerably larger than CML.

That large swing gives excellent noise margin and very low additive jitter, which is why LVPECL remains popular for reference clock distribution, telecom timing, and instrumentation. The cost is power and complexity: an emitter follower conducts continuously and needs an external DC path to a level near two volts below the positive supply, provided either by a resistor to a dedicated bias rail or by a Thevenin-equivalent resistor pair from supply and ground. Boards that mix LVPECL, CML, and LVDS parts frequently need AC coupling plus a bias network at each interface, and getting those networks wrong is a common source of failed clock distribution designs.

HCSL and Reference Clocks

High-speed current steering logic is the convention specified for the 100 MHz reference clock in PCI Express and in many other chipset clock trees. An HCSL driver steers a current of roughly 15 mA into a 50-ohm resistor to ground placed near the driver, so each line swings between ground and about 0.7 V. The scheme is inexpensive, tolerates simple series-terminated routing, and produces low phase noise, but it dissipates static current and requires the shunt terminations to be placed close to the source rather than at the load.

Transition-Minimized Differential Signaling and HDMI

The TMDS Line Code

Transition-Minimized Differential Signaling is the physical layer of the Digital Visual Interface (DVI) and of HDMI through version 2.0. Its defining feature is a line code that maps eight data bits to ten transmitted bits with two goals: minimizing the number of transitions, which reduces both radiated emissions and driver power, and maintaining DC balance so that AC-coupled receivers see no accumulating offset.

The encoder chains the eight input bits through either XOR or XNOR operations, choosing whichever produces fewer transitions, and records the choice in a ninth bit. It then decides, based on the running disparity of ones and zeros transmitted so far, whether to invert the first nine bits, recording that decision in a tenth bit. During blanking intervals the encoder instead emits one of four fixed control characters chosen for high transition density, which lets the receiver establish and verify symbol alignment. This scheme is distinct from the IBM 8b/10b block code used by PCI Express Gen 1 and Gen 2, USB 3.0, and Fibre Channel, even though both expand eight bits into ten.

Electrical Characteristics

A TMDS link carries three data channels, corresponding to red, green, and blue or to a luma and two chroma components, plus a clock channel. Each line is driven by a current-mode output and terminated with 50 ohms to the receiver's 3.3 V supply rail, so the signal swings roughly 500 mV below that rail, giving a 100-ohm differential impedance. The symbol rate on each data channel is ten times the pixel clock, which is why the specifications quote both a TMDS clock frequency and a per-channel bit rate.

HDMI 1.4 supports a TMDS clock up to 340 MHz, corresponding to 3.4 Gbps on each of the three data channels and 10.2 Gbps in aggregate. HDMI 2.0 raises the ceiling to 600 MHz, or 6 Gbps per channel and 18 Gbps in aggregate, and adds scrambling above 340 MHz to spread the emission spectrum. HDMI also layers in auxiliary features that share the connector: Consumer Electronics Control (CEC), the Audio Return Channel and its enhanced successor, and the rarely implemented HDMI Ethernet Channel.

From TMDS to Fixed Rate Link

HDMI 2.1 introduces Fixed Rate Link (FRL) mode, which abandons the clock-locked TMDS arrangement entirely. FRL repurposes the clock channel as a fourth data lane and sends packetized data on all four lanes at one of several fixed rates, up to 12 Gbps per lane, for an aggregate of up to 48 Gbps. It replaces the TMDS code with a 16b/18b line code and adds Reed-Solomon forward error correction, since the raw error rate at those speeds is no longer negligible. The HDMI Forum has since specified HDMI 2.2, which raises aggregate bandwidth to 96 Gbps and requires the Ultra96 cable to reach it. Regardless of mode, HDMI implementations demand tight control of differential impedance, intra-pair and inter-pair skew, and connector and cable quality, because the encoded data stream carries significant energy well above the nominal symbol rate.

DisplayPort and Mobile Display Interfaces

DisplayPort

DisplayPort takes a different approach from HDMI: rather than transmitting pixels in step with a forwarded clock, it packetizes video, audio, and control data into micro-packets and sends them over up to four main-link lanes whose rate is negotiated independently of the video timing. Link rates progressed from RBR at 1.62 Gbps per lane through HBR at 2.7 Gbps, HBR2 at 5.4 Gbps, and HBR3 at 8.1 Gbps, all using 8b/10b encoding. DisplayPort 2.0 and 2.1 add the UHBR rates of 10, 13.5, and 20 Gbps per lane with 128b/132b encoding, reaching 80 Gbps of raw bandwidth across four lanes.

A separate low-speed bidirectional AUX pair carries link management, display identification, and register access, keeping configuration traffic off the main link. Embedded DisplayPort (eDP) applies the same signaling inside notebooks and tablets, replacing the older parallel and LVDS panel links, and DisplayPort Alternate Mode reassigns the high-speed pairs of a USB-C connector to carry main-link lanes directly. The packetized architecture is what makes multi-stream transport possible, allowing several independent displays to share one physical link.

MIPI D-PHY, C-PHY, and M-PHY

Mobile devices use the MIPI Alliance physical layers for camera and display connections. D-PHY is source-synchronous: a clock lane accompanies one or more data lanes, and each lane operates in two distinct modes on the same wires. High-speed mode is differential with a swing near 200 mV on a low common-mode level, while low-power mode drives the two wires single-ended at 1.2 V for control signaling and mode escapes. That dual-mode arrangement keeps idle power extremely low, which matters far more in a phone than peak throughput does. D-PHY carries the CSI-2 camera interface and the DSI display interface.

C-PHY replaces the differential pair with a three-wire "trio" driven with three-phase symbols, encoding roughly 2.28 bits per symbol and embedding the clock in the transitions, which raises throughput for a given wire count and symbol rate. M-PHY is a burst-mode SerDes with defined low-power states, used beneath UniPro and the Universal Flash Storage interface. All three place unusual demands on layout, because the same conductors must behave well both as controlled-impedance high-speed pairs and as slow single-ended control lines.

PCI Express

Generations, Encoding, and Modulation

PCI Express replaced the parallel PCI and PCI-X buses with a switched, packet-based serial fabric. Per-lane rates have roughly doubled with each generation: 2.5 GT/s in PCIe 1.0, 5 GT/s in 2.0, 8 GT/s in 3.0, 16 GT/s in 4.0, 32 GT/s in 5.0, 64 GT/s in 6.0, and 128 GT/s in PCIe 7.0, whose specification PCI-SIG released to members in June 2025 and which supports up to 512 GB/s bidirectionally in an x16 configuration. PCI-SIG has since announced work on a PCIe 8.0 specification targeting 256 GT/s.

The line code changed along the way. PCIe 1.x and 2.x use 8b/10b encoding and pay a 20 percent overhead for it. PCIe 3.0 through 5.0 use 128b/130b encoding with scrambling, cutting overhead to roughly 1.5 percent. PCIe 6.0 makes a deeper change: it drops block coding in favor of fixed-size flow control units, or flits, protected by a cyclic redundancy check and a lightweight forward error correction code, so that the effective overhead stays low despite a much higher raw error rate.

The modulation changed at the same point. Generations 1.0 through 5.0 use non-return-to-zero signaling, one bit per symbol. PCIe 6.0 adopts four-level pulse-amplitude modulation, carrying two bits per symbol so that 64 GT/s is reached at the same 32 GBaud symbol rate as PCIe 5.0 rather than by doubling the signaling frequency. PAM4 divides the available amplitude into three eyes instead of one, cutting the vertical margin by roughly a factor of three and raising the raw bit error rate by orders of magnitude, which is precisely why the forward error correction layer became mandatory. A link is built from one or more lanes; x1, x4, x8, and x16 are the widths ordinarily implemented, and the specification also defines x2, x12, and x32.

Electrical Specification and Equalization

The electrical specification fixes transmitter and receiver voltage levels, timing, jitter budgets, return loss, and equalization behavior at defined compliance points. Transmitter differential swing is nominally 800 to 1200 mV peak to peak in PCIe 1.x and 2.x and falls in later generations as equalization takes over the job of restoring margin. PCIe 1.x and 2.x rely on fixed transmitter de-emphasis and a simple receiver; PCIe 3.0 and later combine a multi-tap transmitter equalizer, receiver continuous-time linear equalization, and decision feedback equalization, with the settings negotiated during link training rather than fixed at design time. PAM4 raises that burden again, since the receiver must resolve three thresholds and compensate for the level-dependent nonlinearity of the transmitter.

Jitter budgets tighten in proportion to the shrinking unit interval. At 32 GT/s the unit interval is about 31 ps, and at 64 GT/s the PAM4 symbol interval is the same 31 ps while the vertical margin is a third of what it was, so the specification apportions random and deterministic jitter, transmitter and receiver contributions, and reference clock phase noise into a detailed budget that a design must meet at every compliance point.

Reference Clocks and Link Training

PCI Express distributes a 100 MHz reference clock in HCSL form, optionally with spread-spectrum modulation to reduce peak emissions. Three architectures are defined: a common clock shared by both link partners, separate reference clocks with independent spread spectrum, and separate clocks without spread spectrum. The choice affects how much frequency offset the clock and data recovery loop must absorb and how the elastic buffer is sized, and it is a system-level decision that must be made before board design begins.

Above the electrical layer, the link training and status state machine governs initialization, width and speed negotiation, equalization phases, low-power states, and recovery from errors. Data integrity is enforced by cyclic redundancy checks with a link-level replay mechanism, so an occasional corrupted packet costs latency rather than correctness. Successful implementation demands controlled-impedance routing, careful via and connector design, adequate decoupling for every SerDes supply, and channel simulation before fabrication.

Universal Serial Bus

USB 2.0

USB 2.0 uses a single half-duplex differential pair, D+ and D-, routed at 90 ohms differential. Low Speed at 1.5 Mbps and Full Speed at 12 Mbps use conventional 3.3 V voltage-mode drivers, and the bus relies on the same two wires in single-ended combinations to signal attachment, speed, and reset. High Speed at 480 Mbps switches to a current-mode driver of roughly 17.8 mA working into 45-ohm terminations to ground on each line, producing about 400 mV of differential swing. All speeds use NRZI encoding with bit stuffing, inserting a zero after six consecutive ones to guarantee enough transitions for clock recovery.

SuperSpeed USB

USB 3.0 added an entirely separate physical layer while retaining the USB 2.0 pair for backward compatibility. SuperSpeed uses two unidirectional differential pairs, one per direction, for full-duplex operation at 5 Gbps with scrambled 8b/10b encoding. USB 3.1 Gen 2 doubles the rate to 10 Gbps and changes the line code to 128b/132b, cutting encoding overhead from 20 percent to about 3 percent. USB 3.2 Gen 2x2 operates two 10 Gbps lanes in each direction over a USB-C connector for 20 Gbps. Low-frequency periodic signaling provides out-of-band communication for link training and power management, since the main link is unusable while the receiver is powered down.

USB4

USB4 is built on the Thunderbolt 3 protocol that Intel contributed to the USB Implementers Forum. Instead of defining a single traffic type, it tunnels USB 3.2, DisplayPort, and PCI Express traffic over a shared link and allocates bandwidth among them dynamically, at 20 or 40 Gbps over two lanes per direction. USB4 Version 2.0 raises the ceiling to 80 Gbps and is the first USB generation to abandon two-level signaling: it uses three-level pulse-amplitude modulation at 25.6 GBaud per lane, yielding 40 Gbps per lane, with forward error correction to handle the reduced margin. Its four high-speed pairs become direction-configurable, so an asymmetric mode can point three lanes the same way to deliver 120 Gbps toward a very high-resolution display while retaining 40 Gbps in the return direction.

The practical difficulty of USB lies less in any single specification than in the combination: a reversible connector, cables of unknown length and quality, power delivery negotiation that can put 48 V on the same connector, alternate modes that reassign pins to other protocols, and a compliance program that spans all of it. Designs routinely need redrivers or retimers to meet the receiver specification through a real connector and cable, and verifying them requires equipment capable of calibrated stressed-eye testing.

Ethernet Physical Layer Standards

Twisted-Pair Ethernet

Twisted-pair Ethernet is transformer-isolated and therefore strictly differential, and each generation has raised spectral efficiency rather than simply raising the clock. The original 10BASE-T uses Manchester coding at 20 megabaud with roughly 2.5 V peak differential drive. Fast Ethernet (100BASE-TX) applies 4B/5B block coding, scrambling, and MLT-3 line coding at 125 megabaud over two pairs of Category 5 cable; because MLT-3 cycles through three levels, its fundamental sits near 31 MHz rather than 125 MHz, which eases emissions and cable requirements considerably.

Gigabit Ethernet (1000BASE-T) is a large step in complexity. It uses all four pairs of Category 5e or better simultaneously in both directions, at 125 megabaud and 250 Mbps per pair, with a four-dimensional trellis-coded five-level PAM constellation. Levels are spaced 0.5 V apart between plus and minus one volt. Because each pair carries traffic in both directions at once, the transceiver must subtract its own transmitted signal with a hybrid and an adaptive echo canceller, then cancel near-end crosstalk from the other three pairs and equalize the residual channel. The waveform on the wire looks like noise on an oscilloscope; the information is recovered entirely in the digital domain.

10GBASE-T, defined in IEEE 802.3an, pushes this approach much further: 800 megabaud on four pairs, 16-level PAM arranged in a two-dimensional DSQ128 checkerboard constellation, Tomlinson-Harashima precoding at the transmitter, and low-density parity-check forward error correction. Reaching 100 m requires Category 6A cabling characterized to 500 MHz, and the digital signal processing involved makes 10GBASE-T ports notably more power-hungry than their optical equivalents. IEEE 802.3bz later defined 2.5GBASE-T and 5GBASE-T as scaled-down versions of the same technique, so that installed Category 5e and Category 6 cabling could carry more than a gigabit.

Backplane, Chip-to-Module, and High-Speed Lanes

Where Ethernet runs over a backplane, a copper cable assembly, or into an optical module, it uses SerDes lanes rather than twisted pair. 10GBASE-KR runs a single 10.3125 GBaud lane with 64b/66b encoding and a defined transmitter equalizer training protocol across a backplane. Above that, the industry consolidated on PAM4 lanes: roughly 53 Gbps per lane, then about 106 Gbps per lane, with Reed-Solomon forward error correction mandatory throughout. IEEE 802.3df-2024 defined 800 Gbps Ethernet built from eight lanes of approximately 106 Gbps, and the P802.3dj project is developing roughly 212 Gbps lanes together with 1.6 Tbps aggregate interfaces. At these rates the electrical specification is written in terms of statistical eye metrics and channel operating margin rather than a simple eye mask, because no unequalized eye exists at the receiver input.

Automotive Ethernet

Automotive variants trade bandwidth for weight, cost, and electromagnetic robustness by using a single unshielded twisted pair. 100BASE-T1 (IEEE 802.3bw) and 1000BASE-T1 (IEEE 802.3bp) provide full-duplex point-to-point links over one pair, 10BASE-T1S (IEEE 802.3cg) adds a short multidrop segment suited to replacing legacy control buses, and IEEE 802.3ch defines 2.5, 5, and 10 Gbps over a single pair for sensor and infotainment backbones. All of them must meet emissions and immunity requirements far stricter than those applied to office equipment, which drives the use of common-mode chokes, careful connector selection, and tightly controlled harness construction.

Serializer and Deserializer Architectures

SerDes circuits implement most modern high-speed differential interfaces, converting parallel data to a serial stream for transmission and reversing the process at the receiver. A SerDes integrates phase-locked loops for clock synthesis, clock and data recovery, serialization and deserialization, transmit equalization, receive equalization, and the control logic for link training and diagnostics. Because the same block can serve several protocols with different rates and line codes, SerDes IP is usually configurable and is the component around which a multi-protocol chip is planned.

On the transmit side, a multiplexer tree combines slower parallel words into the serial stream, and encoding logic applies the required line code or scrambler to guarantee transition density and DC balance. The output driver implements a feed-forward equalizer with programmable pre-cursor and post-cursor taps that pre-distort the waveform to compensate for channel loss. Programmable swing control lets a design trade power against margin, and the tap coefficients are typically negotiated with the link partner during training rather than fixed.

On the receive side, a continuous-time linear equalizer boosts high frequencies to flatten the channel response, and a decision feedback equalizer cancels post-cursor intersymbol interference using previously decided symbols. Clock and data recovery extracts timing from the data and places the sampling instant where the margin is greatest. Beyond roughly 50 GBaud, many designs replace the analog slicer chain with an analog-to-digital converter and a digital equalizer, which allows far more sophisticated processing, including maximum-likelihood sequence estimation, at the cost of power and area. Built-in pattern generators, error counters, and eye-margin scanning let a link be characterized in situ, which is often the only practical way to debug a channel whose eye is closed at the package ball.

Protocol-Specific Requirements

Beyond the electrical layer, each standard imposes protocol requirements that shape the physical implementation. These include link training sequences, equalization adaptation procedures, power management states, error detection and correction, and compliance test methodology. Treating the electrical and protocol layers separately is a common source of trouble, because many electrical parameters are only meaningful in the context of a particular training state.

Link training generally involves transmitting known patterns so the receiver can adapt its equalizer, choose a sampling point, and achieve symbol and lane alignment. PCI Express defines a comprehensive state machine with distinct equalization phases in which both ends request coefficient changes from each other. USB uses low-frequency periodic signaling for out-of-band handshaking before the main link is usable. Backplane Ethernet defines its own training frames for the same purpose. Most standards also define low-power states in which the link is partially or fully shut down, and returning from those states requires some or all of the training sequence to run again, which sets a floor on exit latency that system architects must account for.

Compliance testing ensures that independently designed devices interoperate. Each standard defines compliance test points, test patterns, calibration procedures, and pass criteria. Transmitter tests cover swing, equalization presets, rise and fall time, and jitter decomposition; receiver tests apply a calibrated stressed eye with defined amounts of random jitter, sinusoidal jitter, and intersymbol interference, and measure the resulting bit error rate; system tests confirm behavior over the full range of legal channels. Because certification is often a prerequisite for using a standard's logo, planning for compliance early, including provision for test points and for putting the device into the required test modes, materially reduces schedule risk.

Design Considerations for Multi-Standard Implementations

Modern systems typically carry several differential standards at once, and the interactions between them often matter more than any single interface. Common problems include crosstalk between adjacent high-speed pairs, insufficient isolation between SerDes supplies, reference clock jitter shared across unrelated links, and connectors that carry several protocols on neighboring pins. A USB-C connector that may present USB 3.2, DisplayPort Alternate Mode, or USB4 traffic on the same pins has to satisfy the most demanding of them.

Layout constraints diverge sharply with speed. A 100 Mbps interface tolerates stubs, unmatched vias, and layer changes that would be fatal at 32 GT/s. Higher-rate links dictate stackup, via structures, breakout geometry, and the choice of laminate, and back-drilling or blind vias may be mandatory where they are merely helpful at lower rates. Because the constraints conflict, high-speed pairs should be assigned to layers and routing channels first and slower interfaces fitted around them, not the reverse.

Reusable physical layer IP has become the normal way to implement standard interfaces in ASICs and FPGAs. Pre-verified SerDes macros reduce development time and risk substantially, but they impose requirements of their own: dedicated low-noise supplies, specific package escape patterns, reference clock quality limits, and vendor layout rules that are not optional. Evaluating PHY IP means checking supported rates and protocols, equalization capability against the intended channel, power at the target rate, and the maturity of its compliance evidence, and it is far cheaper to make that assessment before committing to a package and stackup than after.

Conclusion

The differential standards in use today fall into a small number of electrical families and a larger number of complete link specifications built on them. LVDS and its derivatives serve moderate rates where low power and simplicity matter; CML underlies nearly everything above a few gigabits per second; PECL and HCSL persist where clock quality dominates. On top of those, PCI Express, USB, HDMI, DisplayPort, MIPI, and Ethernet each solve a different problem, and each has responded to rising data rates in a similar way: better line codes, adaptive equalization negotiated during link training, forward error correction, and, at the highest rates, multilevel modulation. Understanding both what a standard specifies electrically and what its protocol layer expects of the channel is the practical basis for designing interfaces that pass compliance the first time.

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