Power-Induced Jitter

Power-induced jitter represents one of the most significant yet often underestimated sources of timing uncertainty in modern electronic systems. As supply voltages decrease and operating frequencies increase, even small variations in the power distribution network can translate into substantial timing errors. Understanding the mechanisms by which power supply noise couples into timing-critical circuits and implementing effective mitigation strategies are essential for achieving reliable, high-performance designs.

Jitter caused by power supply variations, commonly called power supply induced jitter (PSIJ), manifests across all types of timing circuits, from simple clock buffers to complex phase-locked loops and high-speed serial transceivers. The chain of causation is short and well defined: switching currents drawn by the load excite the impedance of the power distribution network, the resulting rail fluctuation modulates the delay or the oscillation frequency of a timing circuit, and that modulation appears at the output as displaced edges. The magnitude of the result depends on the supply noise spectrum, the sensitivity of the circuit at each noise frequency, and the effectiveness of isolation and filtering. In many modern systems, power supply induced jitter constitutes a dominant component of total system jitter, making it a critical consideration in timing budget analysis.

Fundamental Mechanisms

Supply Noise Sensitivity

All active circuits exhibit some degree of sensitivity to supply voltage variations. The fundamental relationship between supply voltage and circuit behavior creates multiple pathways for power supply noise to induce timing errors:

Switching Threshold Dependence: The trip point of a static CMOS gate sits at a roughly fixed fraction of the supply, so it moves with the rail; the device threshold voltages themselves shift only slightly, through body effect and drain-induced barrier lowering
Drive Strength Modulation: Output driver strength varies with supply voltage, altering signal slew rates and transition times
Bias Point Shifts: In analog circuits, supply variations can shift operating points, affecting gain, bandwidth, and timing characteristics
Reference Voltage Coupling: Comparator and receiver threshold voltages often reference the supply, making timing decisions supply-dependent

The sensitivity of circuit delay to supply voltage is often quantified as a delay sensitivity coefficient. A convenient process-independent form is the normalized sensitivity, the fractional change in delay per fractional change in supply voltage (percent delay per percent V_DD); for typical CMOS logic this is on the order of one, meaning a one-percent supply change shifts the stage delay by roughly one percent. Expressed as an absolute coefficient, a single gate with a stage delay of tens of picoseconds therefore exhibits a sensitivity on the order of tens of femtoseconds per millivolt. Because this coefficient scales with the stage delay itself, slower buffers and longer delay paths are correspondingly more sensitive, and the accumulated sensitivity of a long chain is what makes power-induced jitter significant.

The sensitivity is not constant across operating conditions. Current drive falls away as the supply approaches the device threshold voltage, so the normalized sensitivity climbs sharply at reduced supply voltages: a circuit operating in the near-threshold region can be several times more sensitive than the same circuit at nominal supply. Dynamic voltage scaling therefore trades power against jitter, and the lowest voltage state is usually the worst case for timing. Deliberate circuit techniques run in the opposite direction; supply-noise-compensated clock buffers, which play a supply-dependent bias against the supply-dependent drive, have been reported to cut the normalized sensitivity by roughly an order of magnitude relative to a plain static CMOS chain.

Propagation Delay Variation

The most direct mechanism of power-induced jitter is through modulation of gate and buffer propagation delays. When supply voltage decreases, transistors provide less drive current, resulting in slower charging and discharging of load capacitances. This relationship is approximately linear over small voltage ranges:

Δt_pd ≈ K × ΔV_DD

where K is the delay sensitivity coefficient specific to the circuit. In a chain of gates or buffers, these individual delay variations accumulate, with the total timing uncertainty growing with the number of stages. For a clock distribution network with multiple buffer stages, even modest supply noise can generate significant jitter at the endpoints.

One consequence of the linear approximation is often overlooked: the sensitivity applies at the instant the edge passes through the stage, not to the average rail voltage. Supply noise faster than the stage delay is partially averaged out, because the edge experiences the noise waveform integrated over its own transition. Supply noise slower than the stage delay is seen essentially as a static offset. The effective sensitivity therefore rolls off at high noise frequencies, and the circuit behaves as a low-pass filter on the disturbance even before any deliberate filtering is added.

Noise Spectrum and PDN Resonance

Sensitivity alone does not determine the jitter. It must be multiplied by the supply noise actually present at each frequency, and that noise is shaped by the impedance of the power distribution network. A real network is not a flat low impedance. Series inductance from the package and the board resonates against board and on-die capacitance, producing anti-resonant impedance peaks: typically a lower one set by bulk and board capacitance working against package inductance, and a higher one, commonly in the tens to hundreds of megahertz, set by package inductance working against on-die capacitance. Current drawn at or near these frequencies develops disproportionate voltage ripple.

The practical consequence is that power-induced jitter is usually concentrated in narrow bands rather than spread evenly across the spectrum. When the spectral content of the load current — the clock frequency and its subharmonics, a switching converter's fundamental, a burst or refresh rate — lands on a power distribution network impedance peak, the resulting jitter can dominate the budget even though the average supply noise looks acceptable. Flattening the impedance profile therefore does as much for jitter as improving circuit rejection, and the two must be traded against each other rather than pursued in isolation.

VCO Pushing

Voltage-controlled oscillators are particularly susceptible to power supply noise, a phenomenon known as VCO pushing or supply pushing. The coupling path depends on the topology. In a ring or relaxation oscillator the period is set directly by charging currents and switching thresholds, both of which move with the rail, so pushing is strong and largely unavoidable without regulation. In an LC oscillator the tank fixes the frequency and the rail reaches it indirectly, chiefly by shifting the varactor's bias point and by modulating the voltage-dependent parasitic capacitance of the active devices; pushing is far weaker but never zero. In either case, supply noise modulates the output frequency, producing phase noise, spurs, and jitter.

Push Coefficient

The sensitivity of VCO frequency to supply voltage is characterized by the push coefficient, K_push, also called supply pushing or supply sensitivity. Datasheets specify it in MHz/V; normalizing it to a percentage frequency deviation per volt makes parts at different carrier frequencies comparable. Narrowband VHF and UHF oscillator modules are commonly specified below 1 MHz/V. Commercial microwave LC VCOs covering roughly 12 GHz to 27 GHz typically specify worst-case pushing in the range of tens of megahertz per volt, which works out to only a few tenths of a percent per volt. Ring oscillators and other current-starved topologies without local regulation sit at the opposite extreme and can exceed 10 percent per volt, which is one reason integrated ring-oscillator PLLs almost always run from a dedicated on-chip regulator.

Pushing varies across the tuning range and with load, so a single datasheet figure is a worst-case summary rather than a constant. It is also distinct from pulling, the frequency shift caused by a varying load impedance; the two are specified separately because they are attacked by different remedies — regulation and filtering for pushing, buffering and isolation for pulling.

Jitter Generation Mechanism

Supply noise at the VCO input translates into frequency modulation, which accumulates as phase error over time. A sinusoidal supply disturbance of amplitude V_noise at frequency f_n produces a peak frequency deviation Δf_peak = K_push × V_noise. For small deviations this is narrowband phase modulation with a modulation index (peak phase deviation, in radians) of β = Δf_peak / f_n, which corresponds to a peak deterministic jitter of:

J_peak = β / (2π f_VCO) = (K_push × V_noise) / (2π f_n f_VCO)

where K_push is the push coefficient (in hertz per volt) and f_VCO is the VCO center frequency. Because the modulation frequency f_n appears in the denominator, low-frequency supply noise produces disproportionately large phase deviation, and hence jitter, compared with high-frequency noise of the same amplitude. Modulating the supply also produces spurious tones (spurs) offset from the carrier by ±f_n. For small β each sideband stands at approximately β/2 relative to the carrier, or 20 log₁₀(β/2) expressed in dBc.

Because the disturbance is a bounded sinusoid, so is the jitter it produces: the root-mean-square value is J_peak/√2 and the peak-to-peak value is 2 J_peak. That distinction matters for budgeting, since a bounded component adds directly to the deterministic term of a timing budget rather than convolving with the Gaussian random term.

PLLs and Supply Sensitivity

Phase-locked loops respond to supply noise in a strongly frequency-dependent way. The loop acts as a high-pass filter on disturbances injected at the VCO: noise well inside the loop bandwidth is tracked out by the feedback, while noise well above the loop bandwidth reaches the output unattenuated, exactly as the free-running analysis predicts. Disturbances injected ahead of the loop — on the reference path, the phase detector, the charge pump, or the dividers — see the complementary low-pass response and are passed through inside the loop bandwidth instead. Neither path is suppressed near the crossover, so supply noise at frequencies close to the loop bandwidth is usually the worst case, and a loop with a peaked response can amplify it outright.

This creates a genuine design tension. Widening the loop bandwidth suppresses more VCO-referred supply noise but admits more reference-path noise, and narrowing it does the reverse. The right choice depends on which side of the loop carries the dirtier rail, which is why the supply feeding the VCO and the supply feeding the reference and divider chain are usually budgeted separately rather than treated as one requirement.

Downstream of the PLL, a clock and data recovery loop in a serial receiver applies a further high-pass shaping to the jitter it must track. Power supply induced jitter slower than the recovery loop's bandwidth is followed by the recovered clock and consumes little timing margin; jitter faster than that bandwidth is not tracked and eats directly into the eye. The jitter tolerance masks published in serial link standards encode exactly this behavior, which is why the frequency of supply noise matters as much as its amplitude.

Buffer Delay Modulation

Clock and data buffers throughout a system contribute to power-induced jitter through delay modulation. When multiple buffers share a power domain, supply noise affects all buffers simultaneously, creating correlated jitter that can accumulate through the signal path.

Single-Stage Effects

A single buffer stage converts supply voltage variations directly into timing errors. The magnitude depends on the buffer's delay sensitivity and the supply noise amplitude. For typical CMOS buffers the normalized sensitivity is on the order of one percent of delay per percent of supply, so a heavily loaded buffer with a stage delay of a few hundred picoseconds may shift its delay by a few tenths of a picosecond for every ten millivolts of supply excursion. The absolute sensitivity grows with stage delay and load capacitance, which is why output drivers and large clock buffers contribute more jitter than minimum-size internal gates.

Cascaded Buffer Chains

Clock distribution networks often employ chains of buffers to maintain signal integrity while driving large loads. In such chains, power-induced jitter can accumulate in several ways:

Uncorrelated Noise: If each buffer experiences independent supply noise, jitter accumulates statistically as the square root of the number of stages
Correlated Noise: When buffers share power distribution and experience common supply variations, jitter accumulates linearly with the number of stages
Frequency-Dependent Behavior: Different accumulation mechanisms dominate at different frequencies, depending on PDN characteristics and buffer spacing

In practice, buffer chains often exhibit partially correlated behavior, with accumulation rates between the statistical and linear extremes.

Correlation also decides how much of the accumulated delay change actually costs timing margin. On a synchronous path, a supply excursion that shifts the launch clock and the capture clock by the same amount largely cancels, because setup and hold checks depend on the difference between the two arrival times rather than on either one alone. What survives is the mismatch: differences in stage count, in loading, and in the local supply noise seen by the two branches. Long, unbalanced clock trees and paths that cross power domains are therefore far more exposed than short, balanced ones, and supply noise that varies across the die is more damaging than a uniform rail excursion of the same amplitude.

Duty Cycle Distortion

Supply variations can affect rising and falling transitions differently, leading to duty cycle distortion in addition to edge-to-edge jitter. This occurs when:

NMOS and PMOS transistors exhibit different supply sensitivities
Rising and falling edges traverse different circuit paths with different supply domains
Supply noise contains frequency components that create asymmetric effects over the clock period

Jitter Amplification

Certain circuit topologies and operating conditions amplify power-induced jitter beyond what a simple sensitivity calculation predicts. Understanding these mechanisms helps identify vulnerable circuits and motivates appropriate mitigation.

The term itself deserves a caution. In channel-oriented signal integrity work, jitter amplification names a different effect entirely: a lossy interconnect can deliver more jitter at the receiver than the transmitter launched, because the channel's low-pass response converts edge timing variation into amplitude variation and back again. This section uses the term in the circuit sense — mechanisms inside the timing circuit that make it more sensitive to supply noise than a first-order delay calculation suggests.

Regenerative Circuits

Circuits with positive feedback, such as sense amplifiers, latches, and comparators, exhibit metastable behavior near their decision threshold. When supply noise affects the circuit during the regeneration phase, small voltage variations can significantly alter the output timing. This effect is particularly pronounced in:

High-speed receivers with decision feedback equalization
Memory sense amplifiers operating near their access time limits
Clock and data recovery circuits during edge transitions

Threshold-Dependent Circuits

Circuits that make timing decisions based on voltage thresholds are inherently sensitive to both signal amplitude variations and threshold shifts. When supply noise modulates both the signal amplitude and the decision threshold, the effects can combine to create amplified jitter. This is especially problematic in:

Single-ended signaling where the signal and reference share supply domains
Voltage-mode logic families with supply-referenced thresholds
Comparators without adequate power supply rejection

Resonant Effects

When supply noise frequencies coincide with circuit natural resonances, amplification can occur through resonant coupling. This is particularly relevant in:

LC-based oscillators where supply noise excites tank resonance
Package and PCB resonances that amplify specific noise frequencies
Clock networks with resonant distribution structures

Power Supply Rejection

Power supply rejection ratio (PSRR) quantifies a circuit's ability to reject supply voltage variations and prevent them from affecting the output. High PSRR is essential for minimizing power-induced jitter in timing-critical circuits.

PSRR Fundamentals

PSRR is typically expressed in decibels and varies with frequency. A circuit with 60 dB PSRR at a particular frequency will exhibit output variations 1000 times smaller than the supply variations at that frequency. For jitter-sensitive applications, PSRR values exceeding 40 dB across the relevant frequency range are generally desirable.

PSRR generally degrades with increasing frequency, because it depends on loop gain and on the effectiveness of filtering structures, and both fall away as frequency rises. The roll-off is rarely a clean monotonic curve. In a regulator, rejection is highest at direct current, falls as the control loop gain rolls off, and reaches its minimum near the loop crossover; above that, the output capacitor and the package and layout parasitics dominate, and the curve may flatten, recover slightly, or collapse. Predicting power supply induced jitter therefore requires the PSRR curve across the whole noise spectrum, not a single headline number quoted at direct current or at 1 kHz.

Circuit Design for High PSRR

Several circuit design techniques enhance power supply rejection:

Differential Architectures: Fully differential circuits naturally reject common-mode supply variations, providing inherently high PSRR
Cascode Structures: Cascode current sources and loads increase output impedance and improve rejection of supply noise
Regulated Bias Circuits: On-chip regulators and bandgap references provide stable bias voltages independent of supply variations
Current-Mode Logic: Logic families that operate based on current switching rather than voltage levels can achieve superior supply rejection
Feedback and Regulation: Local and global feedback mechanisms continuously correct for supply-induced variations

PSRR Measurement and Characterization

Accurate PSRR measurement requires specialized techniques to inject controlled supply disturbances while monitoring output variations. Key considerations include:

Frequency sweep across the relevant range (DC to beyond the highest jitter frequency of interest)
Separation of supply rejection from other noise sources
Accounting for measurement equipment limitations and parasitics
Correlation with jitter measurements to validate PSRR predictions

Isolation Techniques

Effective isolation prevents supply noise generated by noisy circuits from coupling into sensitive timing circuits. Multiple isolation strategies can be employed at different levels of the design hierarchy.

Physical Separation

The simplest isolation technique is physical separation of noisy and sensitive circuits, reducing coupling through substrate, package, and PCB parasitics. Effective separation requires:

Adequate spacing between noise sources and sensitive receivers
Strategic placement of guard rings and substrate contacts to shunt noise currents
Careful floorplanning to avoid routing sensitive signals near noisy power domains
Use of separate package pins and PCB regions for different power domains

Guard Rings and Substrate Isolation

In integrated circuits, guard rings provide a controlled path for substrate currents, preventing them from modulating sensitive circuit nodes. Effective guard ring implementation requires:

Complete enclosure of sensitive circuits or noise sources
Multiple parallel rings for increased isolation
Adequate guard ring width and contact density
Connection to appropriate voltage references (typically substrate or well potentials)

Power Domain Partitioning

Dividing the system into separate power domains isolates noise to specific regions. This approach requires:

Identification of noise sources and sensitive circuits
Assignment of circuits to appropriate power domains
Implementation of level shifters for signals crossing domain boundaries
Careful management of domain interfaces to prevent ground loops and coupling

Package and PCB Isolation

At the package and board level, isolation techniques include:

Separate power and ground pins for different domains
Power plane splits (with careful attention to return current paths)
Strategic via placement to create low-impedance ground connections
Ferrite beads and isolation resistors to impede AC coupling between domains

Separate Power Supplies

Providing separate, dedicated power supplies for sensitive timing circuits offers the highest level of isolation from system-wide supply noise. This approach is commonly employed for critical circuits such as PLLs, clock generators, and high-speed transceivers.

Dedicated Regulators

On-chip or on-board linear regulators can provide clean, isolated power supplies for sensitive circuits. Key design considerations include:

Regulator Bandwidth: The regulator must have sufficient bandwidth to suppress supply noise across the relevant frequency range
Load Regulation: The regulator must maintain stable output voltage despite varying load currents from the supplied circuits
Output Impedance: Low output impedance ensures that load current variations do not create voltage droop
Dropout Voltage: Adequate headroom between input and output voltages must be maintained for proper regulation
Startup Behavior: Regulator startup must be controlled to prevent disruption of sensitive circuits

LDO Regulators for Jitter-Sensitive Circuits

Low-dropout (LDO) linear regulators are particularly well suited to powering jitter-sensitive circuits, because a well-chosen part combines high supply rejection with very low self-generated output noise. The spread between parts is wide enough that it must be checked rather than assumed: general-purpose LDOs commonly fall to a few tens of decibels of rejection by 1 MHz, whereas RF-grade ultralow-noise regulators are specified in the region of 70 dB at 1 MHz with integrated output noise on the order of 1 microvolt RMS over the 10 Hz to 100 kHz band. The regulator's own output noise sets a floor that no amount of rejection can undo, so both figures must be read together — a part with superb PSRR and mediocre self-noise will not deliver a quiet VCO rail. Effective LDO implementation requires:

Selection of LDOs with high PSRR across the frequency range of concern
Adequate output capacitance to maintain stability and provide local energy storage
Proper layout to minimize parasitics and maintain regulator loop stability
Bypassing techniques to handle high-frequency current demands

Multiple Supply Domains

Complex systems often employ multiple separate supply domains, each optimized for its specific requirements:

Core Digital Logic: May tolerate significant supply noise and benefits from aggressive power management
Clock Generation and Distribution: Requires ultra-low noise supplies with excellent regulation
High-Speed I/O: Needs carefully controlled supply levels to maintain signal integrity and timing accuracy
Analog and Mixed-Signal Circuits: Demand quiet supplies isolated from digital switching noise

Trade-offs and Considerations

While separate supplies provide excellent isolation, they introduce complexity and cost:

Increased bill of materials and board area for additional regulators
More complex power sequencing requirements
Potential for ground loops if not carefully managed
Additional routing complexity for multiple supply domains

Filtering Strategies

Effective filtering removes or attenuates supply noise before it can affect timing-critical circuits. Multiple filtering approaches can be combined to provide broadband noise suppression.

Decoupling Capacitors

Decoupling capacitors form the foundation of most power filtering strategies, providing local energy storage and creating low-impedance paths for high-frequency currents. Effective decoupling requires:

Multiple Capacitor Values: A distribution of capacitor values provides effectiveness across a wide frequency range
Strategic Placement: Capacitors must be placed close to the circuits they support, minimizing inductance in the current path
Adequate Quantity: Sufficient total capacitance ensures low impedance at the frequencies of concern
Connection Quality: Low-inductance connections via multiple parallel vias enhance effectiveness

Ferrite Beads

Ferrite beads provide series impedance at high frequencies while maintaining low DC resistance, making them effective for isolating power domains. Key considerations include:

Impedance versus frequency characteristics matched to the noise spectrum
DC resistance minimized to avoid voltage drop
Saturation current rating adequate for the load
Placement to intercept noise currents before they reach sensitive circuits

A ferrite bead is not a benign component. Together with the decoupling capacitance on its load side it forms a lightly damped series-resonant network whose peak can amplify supply noise rather than attenuate it. With the inductance values typical of small beads and the capacitance typical of a local bypass network, that resonance commonly lands somewhere between tens of kilohertz and a few megahertz — squarely in the band where switching converter ripple and PLL loop dynamics live. Adding damping, through a small series resistance or a deliberately lossy bulk capacitor, is usually necessary. The bead's impedance also derates substantially as the DC bias approaches its rated current, so the impedance curve must be read at the actual operating current rather than at zero bias.

LC Filters

LC filters provide selective attenuation of supply noise at specific frequencies. They are particularly effective when the noise spectrum is concentrated in known frequency bands. Design considerations include:

Selection of cutoff frequency below the lowest noise frequency of concern
Adequate inductor current rating and low DC resistance
Capacitor values chosen for desired roll-off characteristics
Damping to control resonant behavior and prevent peaking

Pi Filters and Multi-Stage Filtering

Pi filters (capacitor-inductor-capacitor) and cascaded filter stages provide enhanced attenuation for critical applications. These structures offer:

Improved high-frequency rejection compared to simple LC filters
Better load isolation from supply impedance variations
Flexibility to optimize different stages for different frequency ranges

Active Filtering

Active filter circuits can provide very high noise rejection with smaller passive components. Techniques include:

Op-amp-based active filters with programmable characteristics
Feedback-controlled regulators that actively cancel supply variations
Noise cancellation circuits that inject compensating currents

Measurement and Characterization

Effective management of power-induced jitter requires accurate measurement and characterization techniques to validate designs and diagnose issues.

Simultaneous Power and Timing Measurement

Understanding the relationship between supply noise and jitter requires time-correlated measurement of both domains. This typically involves:

High-bandwidth power supply probing to capture noise events
Jitter measurement synchronized with supply measurements
Statistical analysis to identify correlations between supply variations and timing errors
Frequency-domain analysis to reveal spectral relationships

Jitter Decomposition

Separating power-induced jitter from other jitter sources helps quantify the specific contribution of supply noise. Techniques include:

Comparison of jitter with and without controlled supply disturbances
Spectral analysis to identify jitter components correlating with known supply noise frequencies
Statistical fitting of jitter distributions to identify deterministic components

Sensitivity Testing

Deliberate injection of supply disturbances while monitoring timing allows direct measurement of circuit sensitivity. This approach enables:

Quantification of delay sensitivity coefficients
Validation of PSRR specifications
Identification of frequency ranges where sensitivity is highest
Comparison of different power filtering and isolation strategies

Placing the Result in a Jitter Budget

Power supply induced jitter is bounded, so it belongs in the deterministic term of a timing budget rather than the random term. Periodic supply noise — a converter switching frequency, a clock harmonic, a burst or refresh rate — appears as periodic jitter, one of the standard deterministic subcomponents, and is identifiable in a jitter spectrum by its discrete tone. Broadband supply noise uncorrelated with the data pattern instead contributes bounded uncorrelated jitter. Classifying either as random jitter is a common and costly error, because random jitter is scaled by a multiplier that grows with the target bit error rate while a bounded component is not; the misclassification either wastes margin at low error rates or conceals a real failure at high ones.

Design Guidelines and Best Practices

Minimizing power-induced jitter requires attention throughout the design process, from architecture and circuit design through layout and validation.

Architecture-Level Decisions

Identify jitter-critical circuits early in the design process
Plan power domain partitioning with jitter sensitivity in mind
Budget for dedicated supplies and regulators where justified by jitter requirements
Choose circuit topologies and logic families with good inherent PSRR

Circuit Design Guidelines

Employ differential architectures where possible for timing-critical paths
Design clock distribution networks with consistent delay sensitivity across stages
Implement local regulation for VCOs and other highly sensitive circuits
Minimize the number of stages in timing-critical paths to reduce jitter accumulation
Design for adequate PSRR across the full frequency range of potential supply noise

Layout Best Practices

Place decoupling capacitors as close as possible to sensitive circuits
Use multiple parallel vias for power and ground connections to minimize inductance
Implement guard rings and substrate isolation for jitter-critical blocks
Route sensitive signals away from noisy power domains and switching circuits
Maintain clean return current paths for high-speed signals
Verify power distribution network impedance through simulation before fabrication

Validation and Testing

Include supply noise injection capability in test fixtures for sensitivity characterization
Perform time-correlated measurements of supply voltage and jitter
Validate that actual jitter sensitivity matches predictions from simulation
Test across process, voltage, and temperature corners to ensure robust performance
Document measured PSRR and sensitivity parameters for future reference

Case Studies and Practical Examples

The figures below are illustrative, using round numbers chosen to show how the mechanisms and formulas combine; specific values vary widely with process, frequency, and topology.

Clock Distribution Network

Consider a processor clock tree of ten buffer stages, each with a stage delay of roughly 200 ps on a 1.0 V supply and a normalized sensitivity near one percent of delay per percent of supply, which is an effective coefficient of about 0.2 ps/mV per stage. With 20 mV of correlated supply ripple shared across the tree, each stage shifts by about 4 ps and the deviations add linearly, moving the tree's total insertion delay by roughly 40 ps. Were the ripple perfectly uniform across the die, launch and capture clocks would move together and much of that shift would cancel; in a real chip it is not uniform, so a substantial fraction survives as jitter and as dynamic skew between branches. Dedicating a quieter supply to the clock tree and improving decoupling cut the ripple to about 2 mV, reducing the modulation to roughly 4 ps and recovering meaningful timing margin.

PLL in a High-Speed Transceiver

A transceiver PLL uses a 10 GHz VCO with a supply-pushing coefficient of 10 MHz/V, or 0.1 percent per volt. Its rail carries 5 mV peak of ripple at 1 MHz, a frequency above the loop bandwidth and therefore not corrected by the loop. The peak frequency deviation is 50 kHz, giving a modulation index of about 0.05 rad, a peak deterministic jitter near 0.8 ps, and a root-mean-square contribution near 0.56 ps. The same modulation places spurs about 32 dBc below the carrier at ±1 MHz offset, degrading the eye and raising the bit error rate. Adding a dedicated low-noise regulator with roughly 60 dB of rejection at 1 MHz cuts the ripple by a factor near one thousand and pushes the resulting jitter into the femtosecond range — provided the regulator's own output noise is low enough not to become the new limit.

Mixed-Signal IC with Digital Noise Coupling

In a mixed-signal device, digital switching generates supply and substrate noise that couples into a sensitive clock generator, producing excessive jitter. Spectral analysis shows that harmonics of a 100 MHz digital clock dominate the disturbance. Combining power-domain separation, a ferrite bead between the digital and analog rails, and targeted decoupling tuned to 100 MHz and its low-order harmonics reduces the coupling by roughly 30 dB (a factor of about thirty in amplitude), bringing the clock-generator jitter back within specification.

Conclusion

Power-induced jitter represents a critical challenge in modern electronics, particularly as voltage margins shrink and timing requirements tighten. Understanding the mechanisms through which supply noise couples into timing variations enables designers to implement effective mitigation strategies. Success requires a multi-faceted approach combining circuit design for high PSRR, careful power distribution network design, strategic isolation and filtering, and thorough validation through measurement and characterization.

As systems continue to push toward higher speeds and lower power, the interaction between power integrity and timing will only intensify. Designers who develop expertise in identifying, quantifying, and mitigating power-induced jitter will be well-positioned to deliver robust, high-performance systems that meet increasingly stringent requirements.