Electronics Guide

Phase Noise in Oscillators

Phase noise is the timing uncertainty inherent in every oscillator, arising from random fluctuations in the oscillator's instantaneous phase. These fluctuations appear as jitter in the time domain and as spectral spreading around the carrier in the frequency domain. Quartz crystal oscillators, MEMS oscillators, and integrated LC and ring oscillators all exhibit phase noise, though at vastly different levels depending on resonator quality factor (Q) and implementation technology. Phase noise is reported as the single-sideband noise power in a 1 Hz bandwidth at a given offset from the carrier, relative to the carrier power, in units of dBc/Hz. Further reading on the devices themselves appears in crystals and oscillators.

The mechanisms behind phase noise include thermal noise in active and passive components, flicker (1/f) noise in transistors, and the upconversion of low-frequency noise onto the carrier by the oscillator's nonlinear sustaining amplifier. Leeson's model captures the resulting shape as a sequence of straight-line regions on a log-log plot: closest to the carrier the noise falls at roughly 30 dB per decade as upconverted flicker noise dominates, then at 20 dB per decade within the resonator bandwidth where white noise dominates, and finally it flattens into a noise floor set by the sustaining amplifier and output buffer. High-Q resonators narrow the region where the 20 dB per decade slope applies and push the whole curve downward, which is why a quartz resonator outperforms an on-chip inductor by a wide margin.

Representative numbers illustrate the spread. Good quartz oscillators reach far-from-carrier noise floors in the range of -150 to -170 dBc/Hz. State-of-the-art 100 MHz oven-controlled crystal oscillators (OCXOs) approach roughly -175 to -180 dBc/Hz, a level so low that measuring it challenges available instrumentation and generally requires cross-correlation techniques. Low-Q ring oscillators built in standard digital processes sit tens of decibels above that, which is precisely why they are used inside a phase-locked loop that can suppress their close-in noise rather than as free-running references.

Phase noise translates into jitter by integration over a frequency band. For small phase deviations, the root-mean-square jitter contributed by a band is

σ_t = √(2A) / (2π f_c)

where A is the phase noise power integrated across that band expressed as a ratio to carrier power, and f_c is the carrier frequency. Two consequences follow. First, a jitter figure is meaningless without the integration limits, because extending the band always adds noise. Second, for a fixed phase noise curve the jitter falls as the carrier frequency rises, which is one reason system designers prefer higher-frequency references where the phase noise allows it.

Serial link standards therefore specify an integration band. Many high-speed interfaces, including PCI Express reference clocks, use 12 kHz to 20 MHz. Contemporary low-jitter clock generators specify well under 100 fs RMS across that band, and the best parts reach a few tens of femtoseconds. Close-in phase noise, below the integration band, primarily degrades long-term frequency stability and wander, while broadband noise sets the cycle-to-cycle jitter. In a clock distribution tree, the reference oscillator's phase noise establishes a floor that propagates through the entire timing hierarchy, so oscillator selection is one of the few decisions that cannot be corrected downstream.

Power Supply Noise Coupling

Variations in supply voltage couple into timing circuits through several pathways and convert directly into timing uncertainty. This power supply induced jitter (PSIJ) exists because circuit delay depends on supply voltage: a higher rail charges load capacitance faster, shortening propagation delay, and a momentary droop lengthens it. Because a clock passes through a chain of buffers, the sensitivities accumulate, and even a supply disturbance of a few tens of millivolts can produce picoseconds of timing error at the end of a long distribution path.

The coupling mechanisms include direct modulation of transistor drive strength, shifts in the effective switching threshold of receivers and comparators, modulation of a voltage-controlled oscillator's control voltage and bias, and substrate noise coupling within an integrated circuit. Sensitivity is commonly quantified as a delay sensitivity, expressed as the percentage change in delay for a one percent change in supply voltage, or equivalently in picoseconds per millivolt. Uncompensated CMOS buffer chains are considerably worse than one percent delay per one percent of supply, while circuits designed with regulated or compensated bias can be brought to roughly 0.1 percent delay per one percent of supply. Ring-oscillator VCOs are far more supply-sensitive than LC VCOs, which is a principal reason LC topologies are chosen for the most demanding synthesizers.

The frequency content of the disturbance matters as much as its amplitude. Switching regulators operate at hundreds of kilohertz to a few megahertz, placing their fundamental and lower harmonics squarely inside the 12 kHz to 20 MHz integration band used to grade reference clocks. Their ripple therefore appears as periodic jitter with an identifiable spectral line rather than as a diffuse increase in random jitter, which makes it comparatively easy to diagnose. Wide parallel buses create a different problem: simultaneous switching output noise produces a supply droop correlated with the data pattern, so the resulting jitter is data dependent and cannot be averaged away.

Mitigation begins with the power distribution network: low-impedance planes, decoupling capacitance staged across several frequency decades, and physical separation of quiet timing supplies from noisy digital rails. A linear low-dropout regulator placed close to the sensitive load adds useful rejection, but its benefit is band-limited. A general-purpose LDO typically provides on the order of 50 to 60 dB of rejection at low frequency, and that rejection falls at roughly 20 dB per decade once the regulator's loop gain rolls off, reaching negligible values somewhere in the megahertz range. Purpose-built low-noise regulators do considerably better, holding more than 70 dB of rejection out to a few megahertz. The power supply rejection ratio of the clock generator or PLL itself completes the picture, since it determines how much residual ripple the device converts into jitter and therefore how quiet the rail actually needs to be.

Thermal Noise Effects

Thermal noise, also called Johnson-Nyquist noise, arises from the random motion of charge carriers in any resistive element at a temperature above absolute zero. It has a flat spectral density proportional to temperature and resistance, and it exists in every conductor, every termination, and every transistor channel in the signal path. In timing circuits it is the irreducible source of random jitter.

The open-circuit noise voltage of a resistor is v_n = √(4kTRB), where k is the Boltzmann constant (1.380649 × 10^-23 J/K), T is absolute temperature, R is resistance, and B is the measurement bandwidth. At room temperature this works out to roughly 0.9 nV/√Hz for a 50 Ω resistor and about 4 nV/√Hz for 1 kΩ. These are small voltages, but a threshold detector converts them into time.

The conversion is straightforward and worth internalizing, because it explains most of what designers do about random jitter. At a threshold crossing, the timing error produced by an amplitude perturbation is the perturbation divided by the slew rate:

σ_t ≈ v_n / (dv/dt)

Everything follows from this relation. Faster edges convert less voltage noise into timing noise, so a degraded edge rate at the receiver raises jitter even when the amplitude noise is unchanged. Larger signal swings improve the ratio for the same reason. Restricting bandwidth to what the signal actually requires reduces the integrated noise voltage, though it also slows the edge, which makes bandwidth a genuine optimization rather than a monotonic improvement. Lowering source impedance helps where the circuit permits it, and cryogenic cooling helps in the rare applications that can justify it.

Thermal noise is Gaussian, so the jitter it produces is Gaussian and unbounded. It appears in jitter decomposition as random jitter (RJ), specified as a standard deviation rather than a peak value, and it sets the tails of the timing distribution that determine bit error rate at low probabilities. This is why random jitter must be extrapolated to the target error rate rather than simply measured: the peak-to-peak value observed in any finite acquisition understates the value that matters.

Crosstalk-Induced Jitter

Crosstalk occurs when signals on adjacent conductors couple energy through electric and magnetic fields. Where the coupled energy perturbs a victim's waveform near its threshold crossing, it produces crosstalk-induced jitter. The mechanism dominates in dense printed circuit boards, connectors, and package escapes, wherever aggressor and victim run parallel for an appreciable fraction of the rise-time length. The broader treatment of the coupling itself appears in crosstalk and coupling.

The magnitude depends on the separation and length of the parallel run, the aggressor's edge rate, the impedance environment, and the relative timing of aggressor and victim transitions. Near-end (backward) crosstalk and far-end (forward) crosstalk behave quite differently. Near-end crosstalk propagates back toward the driver as a low-amplitude pulse whose duration is approximately twice the one-way propagation delay of the coupled region, and its amplitude saturates once the coupled length exceeds half the rise-time length. It chiefly degrades the near-end environment, although reflections from impedance discontinuities can return it to the receiver.

Far-end crosstalk arrives at the victim's receiver coincident with the data transition, as a pulse proportional to the derivative of the aggressor edge, and it is therefore the component that most directly displaces the victim's decision point. Its amplitude grows with coupled length and with faster aggressor edges. Critically, far-end crosstalk is the difference between the inductive and capacitive coupling contributions. In a homogeneous dielectric these two contributions are equal and cancel, so far-end crosstalk in stripline is theoretically zero, whereas microstrip, with air above and laminate below, has no such cancellation and exhibits far higher far-end crosstalk. This is a strong argument for routing tightly packed high-speed buses in stripline. The cancellation is not perfect in practice, because glass-weave inhomogeneity in the laminate makes the local dielectric constant vary along the trace, leaving residual far-end crosstalk that fiber-weave mitigation, such as routing at an angle to the weave or specifying a spread-glass style, is intended to reduce.

Crosstalk-induced jitter is data dependent, because the coupling only acts when the aggressor transitions and its sign depends on the aggressor's direction. Worst-case patterns therefore produce worst-case timing displacement, and the jitter appears deterministic and bounded rather than random. Compliance testing exploits this by driving aggressors with patterns chosen to maximize coupling. Mitigation includes increasing trace separation, shortening parallel runs, breaking up long coupled sections, using differential signaling with tight intra-pair coupling, adding grounded guard traces with adequate stitching vias, and maintaining controlled impedance so that reflected crosstalk does not compound the direct component.

Intersymbol Interference Induced Jitter

Intersymbol interference (ISI) occurs when the channel's response to one symbol has not settled before subsequent symbols arrive. Energy from previous bits shifts the waveform at the current bit's threshold crossing, so the apparent transition time varies with the preceding bit pattern. This is the largest single deterministic jitter contributor in most long, lossy channels, and it is the reason equalization exists.

The underlying cause is that real channels are not ideal wideband systems. Conductor loss rises approximately with the square root of frequency because of skin effect, and dielectric loss rises approximately in proportion to frequency, so a long trace behaves as a low-pass filter whose step response has a long tail. Finite bandwidth in drivers, receivers, and connectors adds to the effect. Reflections contribute an equivalent impairment even in low-loss channels: an unterminated via stub, a connector discontinuity, or an impedance mismatch returns energy that arrives one or more bit periods late and displaces later transitions in exactly the same pattern-dependent way.

ISI-induced jitter is deterministic and bounded, determined by the channel's impulse response and the transmitted sequence rather than by any random process. Its magnitude scales with the ratio of the impulse response duration to the unit interval, which is why the same channel that is unremarkable at one gigabit per second becomes marginal at ten. The worst case is an isolated transition following a long run of identical bits: the run allows the channel to settle to a rail, so the lone transition starts from the largest possible displacement and crosses the threshold latest. Compliance patterns and pseudorandom sequences are chosen to exercise exactly this condition.

Equalization targets ISI directly. A continuous-time linear equalizer (CTLE) applies a high-frequency boost that partially inverts the channel roll-off. A feed-forward equalizer (FFE), usually implemented as transmitter de-emphasis, pre-distorts the launched waveform. A decision feedback equalizer (DFE) subtracts the calculated post-cursor contribution of already-decided bits, which cancels ISI without amplifying noise but cannot address pre-cursor terms. Modern receivers combine all three. Loss and equalization covers the channel behavior and the equalizer architectures in depth.

Reference Clock Jitter

The reference clock is the timing source from which most of a system's other clocks derive, and any jitter on it propagates into everything downstream. Reference jitter originates in the oscillator itself, in the buffers and dividers that condition and fan out the clock, and in the board environment through which the clock travels. It establishes a baseline uncertainty that later stages can filter but never remove, and that they can easily make worse.

Crystal oscillators provide excellent stability but are not jitter-free, and every element after them adds a contribution. Fanout buffers and clock drivers add their own noise, commonly specified as additive jitter, and the specification is only valid on a clean supply, since the same devices convert supply ripple into jitter through the mechanisms described above. Long distribution traces degrade the clock further through reflections, crosstalk, and electromagnetic pickup, and slow edges at a receiving input amplify whatever amplitude noise is present into timing noise. Practical reference clock architecture is largely the discipline of not undoing the oscillator's performance.

Frequency multiplication deserves particular attention. When a PLL multiplies a reference by N, phase noise inside the loop bandwidth appears at the output raised by 20 log₁₀(N) decibels, because multiplying frequency multiplies phase. Deriving a 10 GHz clock from a 100 MHz reference, for instance, raises the in-band reference noise by 40 dB. Outside the loop bandwidth the reference contribution is attenuated and the VCO dominates instead. This is the central trade-off in loop bandwidth selection, and it means a reference that is entirely adequate for one multiplication ratio may be unusable at another.

System architecture also determines how much reference jitter actually costs. In a common-clock architecture, both ends of a link derive their timing from the same reference, so a large part of the reference jitter is common to transmitter and receiver and cancels in the receiver's phase comparison. PCI Express formalizes this distinction: the common reference clock architecture benefits from that correlation, whereas the separate reference architectures, with and without spread spectrum, give each end an independent reference and forfeit the cancellation. The same nominal oscillator therefore imposes a tighter or looser requirement depending on the architecture around it, and jitter budgets must state which case they assume.

Phase-Locked Loop Jitter

Phase-locked loops are ubiquitous for clock generation, frequency synthesis, and clock recovery. They both generate jitter of their own and reshape the jitter presented at their input, so understanding their transfer characteristics is essential. Internal contributions arise from the voltage-controlled oscillator, the phase-frequency detector, the charge pump, the feedback divider, and the loop filter. The device-level background appears in phase-locked loops and voltage-controlled oscillators.

The VCO is usually the dominant internal source. Ring-oscillator VCOs, easy to integrate in digital processes, exhibit substantially higher phase noise than LC VCOs but occupy less area, tune over a wider range, and consume less power at low frequencies. Beyond the loop bandwidth, where feedback can no longer track and correct the oscillator, VCO phase noise passes to the output essentially unmodified, so the VCO alone sets the high-offset noise floor.

Loop dynamics determine how the PLL processes each noise source, and the two dominant sources see complementary filters. Toward the reference and the loop's own input-side circuitry the PLL behaves as a low-pass filter: noise within the loop bandwidth passes to the output, multiplied in phase by the divide ratio, while higher-frequency reference noise is attenuated. Toward the VCO it behaves as a high-pass filter: low-frequency VCO noise is suppressed by the feedback, while high-frequency VCO noise survives. The optimum loop bandwidth is approximately where the multiplied reference and loop noise curve crosses the VCO noise curve; widening the loop beyond that point admits more reference noise, and narrowing it admits more VCO noise. Jitter cleaners exploit the same mathematics deliberately, using a very narrow loop, sometimes only a few hertz to a few hundred hertz, together with a high-Q voltage-controlled crystal oscillator, so that the crystal's own excellent noise dominates almost the entire output spectrum.

Several additional mechanisms are specific to particular architectures. In a fractional-N synthesizer, a delta-sigma modulator dithers the feedback divider to realize a non-integer average ratio; the modulator's quantization error is shaped to high frequency, where the loop filter removes most but not all of it, and imperfect randomization leaves discrete fractional spurs. In an all-digital PLL, the time-to-digital converter's resolution imposes an analogous quantization floor. Charge-pump up and down current mismatch, together with dead-zone behavior near lock, produces periodic disturbances that appear as reference spurs at the phase-comparison frequency and its harmonics. Supply and substrate noise reaching the VCO control node or bias network converts into phase modulation with high efficiency, since the control node is by construction a sensitive frequency input.

Spread-Spectrum Clocking

Not every source of timing variation is unintended. Spread-spectrum clocking (SSC) deliberately modulates a clock's frequency so that its radiated energy is distributed across a band rather than concentrated in narrow harmonics, which lowers the peak measured in electromagnetic compliance testing by several decibels. Several widely deployed interfaces, including PCI Express, USB, SATA, and DisplayPort, permit or require down-spreading of roughly 0 to -0.5 percent at a modulation rate near 30 to 33 kHz, typically with a triangular profile. The subject is treated on its own terms in spread-spectrum clocking.

From a timing perspective SSC is an enormous, deliberately injected low-frequency phase modulation. Integrating a frequency deviation of that size over a modulation period accumulates a phase excursion of hundreds to thousands of unit intervals at multi-gigabit rates, far more than any timing budget could absorb. It is tolerable only because it is slow: a receiver's clock and data recovery loop tracks it, and elastic buffers absorb the resulting rate difference between clock domains. Standards accordingly exclude SSC from the random jitter budget by specifying measurement filter functions that reject the modulation frequency.

The engineering cost appears elsewhere. SSC imposes a minimum bandwidth and a minimum tracking range on every clock recovery loop in the link, and any residual the loop fails to track becomes real timing error at the sampler. It complicates clock-domain crossings, requiring elastic buffers deep enough for the worst-case accumulated skew. It interacts badly with repeaters and retimers that must track modulation applied upstream, and it forces the separate-reference architectures to account for two independent modulations that may drift in and out of phase with each other. Where an interface allows SSC to be disabled, that is often the correct choice for jitter-critical equipment, provided the resulting emissions still pass compliance.

Electromagnetic Interference

Electromagnetic interference (EMI) is externally generated field energy coupling into timing-sensitive circuits. Sources include switching converters, nearby digital circuits with fast edges, wireless transmitters, motors and other electromechanical loads, and intentional radiators such as broadcast stations. When these fields reach a clock distribution network, an oscillator, or a high-impedance signal node, they modulate timing and appear as jitter.

The coupling paths are radiation picked up by traces and cables acting as unintended antennas, conduction through shared power and ground connections, and near-field coupling between closely spaced structures. Differential signaling rejects a substantial fraction of the coupled energy as common mode, provided the pair remains balanced; skew or asymmetry within the pair converts common mode back into differential mode and defeats the rejection. Single-ended signals, high-impedance nodes, and long cable runs are the most exposed. Severity depends on field strength, frequency, coupling efficiency, and the victim's sensitivity at that frequency.

EMI-induced jitter has a distinctive signature. A narrowband interferer produces periodic jitter, visible as a discrete line in the jitter spectrum at the offending frequency, which often identifies the culprit immediately by comparison with known switching and carrier frequencies in the system. Broadband interference instead raises the apparent random jitter. Mitigation follows conventional practice: continuous reference planes, shielding of sensitive circuits and cables, filtering at every enclosure penetration, routing high-speed and clock signals away from board edges and away from noisy circuits, and, where the environment demands it, a conductive enclosure. Electromagnetic compatibility covers the design and test discipline in full.

Measurement and Characterization

Attributing jitter to a source requires systematic measurement. Real-time and equivalent-time oscilloscopes with jitter analysis software, time interval analyzers, phase noise analyzers, and bit error rate testers each reveal different aspects. Decomposing total jitter into random and deterministic parts, and then separating the deterministic part into periodic, data-dependent, and bounded uncorrelated components, narrows the field of candidate mechanisms considerably before any physical experiment is performed. The instruments and procedures are covered in jitter measurement.

Every jitter number depends on two choices that must be stated alongside it: the observation bandwidth and the timing reference. A measurement referenced to an ideal constant-rate clock reports all phase variation, whereas one referenced to a recovered clock reports only what the receiver's loop fails to track, and the two can differ by orders of magnitude on a spread-spectrum link. Standards specify a golden PLL or an equivalent filter function precisely so that results are comparable. The frequency-domain equivalent is the integration band discussed earlier; a phase noise plot and a time interval error spectrum carry the same information in different coordinates.

Correlation experiments isolate specific contributors. Injecting a known sinusoidal ripple on a supply rail while observing the jitter spectrum quantifies power supply induced jitter sensitivity directly, in picoseconds per millivolt at each frequency. Switching between a repeating clock-like pattern and a long pseudorandom sequence separates pattern-dependent jitter from everything else. Quieting or disabling a suspected aggressor and observing the change attributes crosstalk. Comparing a device driven from a laboratory-grade reference against the same device on the system reference separates additive jitter from reference jitter.

Higher-level views tie the measurements to system performance. Jitter spectrum analysis exposes periodic components and their frequencies. Jitter transfer and jitter tolerance measurements characterize how a PLL or repeater passes and withstands modulation. Bathtub curves relate sampling position to bit error rate and support extrapolation to error rates far below what can be measured directly. Eye diagrams remain the most intuitive summary of the combined result, as covered in eye diagram analysis and optimization. A jitter budget assembles all of it, allocating an allowance to each source and combining random contributions in quadrature while summing bounded deterministic contributions directly.

Design Considerations and Best Practices

Managing jitter begins with component selection. Oscillators, PLLs, and distribution devices should be chosen against phase noise and integrated jitter specifications stated over the band the application actually cares about, not against a headline figure measured elsewhere. The primary reference should use the highest practical resonator Q, typically quartz, with a jitter-cleaning PLL where a wide-band synthesizer would otherwise degrade it. Additive jitter specifications for buffers must be read together with their power supply rejection, since the two are only separable on paper.

Power distribution design has a direct and often underestimated effect. Decoupling staged across several frequency decades, low-inductance connections from capacitor to load, generous plane area, and physical separation of timing supplies from switching loads all keep supply-induced jitter in check. Local linear regulation for oscillators and PLLs is worthwhile where the noise spectrum falls within the regulator's effective range, and placing the regulator close to the load preserves that benefit. Verifying the result requires measuring rail noise in the frequency domain, not merely observing a stable direct-current level.

Layout and routing govern crosstalk and EMI susceptibility. Critical timing signals should be differential, with controlled impedance, tight intra-pair coupling, and matched intra-pair length. High-speed nets should route in stripline where far-end crosstalk cancellation is available, with parallel runs kept short and adjacent-layer routing kept orthogonal. Clock distribution deserves its own rules: controlled impedance, minimal via transitions, matched delays across the tree, continuous reference planes with stitching vias wherever a signal changes reference layer, and generous separation from switching nodes. Related practice appears in clock jitter management.

Architecture choices set the terms of the whole problem. Where throughput permits, a lower signaling rate lengthens the unit interval, so the same absolute jitter consumes a smaller fraction of the budget; conversely, each increase in data rate makes a fixed picosecond proportionally more expensive. A common-clock architecture buys correlation that a separate-reference architecture forfeits. Source-synchronous buses forward a clock alongside the data so that common-mode timing variation cancels. Asynchronous domain crossings need properly designed synchronizers and adequately deep elastic buffers, which is a distinct concern from jitter but one that timing variation aggravates. In serial links, equalization handles ISI and forward error correction absorbs the residual errors that timing margin alone cannot prevent. Throughout, simulation and measurement should confirm that the budget is met with margin and that no single source has come to dominate the total.

Conclusion

Jitter sources are diverse, spanning fundamental physical limits, component imperfections, design choices, and the external environment. Oscillator phase noise establishes a floor that no downstream circuit can remove. Thermal noise converts into timing error through the finite slew rate at every threshold crossing. Power supply noise, crosstalk, and intersymbol interference add contributions whose size is set by engineering decisions rather than by physics. Phase-locked loops simultaneously generate jitter and filter it, with a loop bandwidth that must be chosen against the specific reference and VCO in use. Spread-spectrum clocking injects timing variation on purpose. Electromagnetic interference adds whatever the operating environment supplies.

Effective design depends on knowing which of these mechanisms dominates in a given system, because the remedies are mechanism-specific and largely non-interchangeable. A quieter regulator does nothing about intersymbol interference, and an aggressive equalizer does nothing about a noisy reference. Measurement and decomposition identify the dominant contributor; a jitter budget allocates an allowance to each; and verification confirms the allocation with margin. As unit intervals continue to shrink, that discipline separates designs that hold up across process, voltage, temperature, and production volume from those that pass on the bench and fail in the field.

Related Topics