Electronics Guide

PLL Operating Principles

A basic PLL consists of three essential components connected in a feedback loop: a phase detector that compares the input and output phases, a loop filter that processes the error signal, and a voltage-controlled oscillator (VCO) that generates the output frequency. When locked, the PLL adjusts the VCO frequency until the phase difference between reference and feedback signals remains constant.

The feedback path typically includes a frequency divider, enabling the VCO to run at a multiple of the reference frequency:

f_out = N f_ref

where N is the feedback division ratio. This frequency multiplication capability makes PLLs invaluable for generating high-frequency clocks from stable, low-frequency crystal references. Many architectures divide the reference by an integer R before the phase detector as well, yielding:

f_out = (N / R) f_ref

The reference divider sets the phase-detector comparison frequency, f_ref / R, and an integer-N synthesizer moves its output only in steps of that comparison frequency. Finer steps therefore demand a lower comparison frequency and, for a given output frequency, a larger N. That resolution is not free. The loop multiplies the phase noise of everything ahead of the VCO by the ratio between the output frequency and the comparison frequency, so each halving of the step size costs 6 dB of phase noise inside the loop bandwidth. Fractional-N synthesis exists to break that trade, and the sections below develop each half of it in turn.

Reference Oscillators

A locked loop copies the long-term accuracy of its reference onto its output. No loop filter improves that accuracy, so the reference oscillator sets a ceiling the rest of the design can only fail to reach. Oscillator data sheets quote three separate numbers, all in parts per million, and treating them as one produces an over-optimistic frequency budget:

• Initial accuracy: The calibration tolerance at a single stated temperature, conventionally 25 degrees Celsius, on the day of manufacture. It is a fixed offset, and a system able to measure it against a better standard can calibrate most of it away.
• Frequency stability: The excursion over the operating temperature range, and sometimes over supply voltage and load variation as well. It changes as the equipment warms and cools, so calibration at one temperature does not remove it.
• Aging: The slow, largely monotonic drift with elapsed operating time, usually quoted for the first year and at a lower figure per year thereafter. Aging accumulates, which is why the ten-year figure is the one that matters for equipment expected to hold calibration in the field.

A worst-case frequency budget adds all three. The choice among oscillator classes then follows from the total the application allows:

• Crystal oscillator (XO): An uncompensated quartz oscillator, with stability over the industrial temperature range typically in the range of ±10 to ±100 parts per million and first-year aging of a few parts per million. Adequate for processor and interface clocking, where the far end of the link recovers timing from the data anyway.
• Temperature-compensated crystal oscillator (TCXO): A compensation network cancels most of the crystal's temperature curve, reaching stability on the order of ±0.1 to ±5 parts per million for a few tens of milliwatts. The usual choice for radio equipment and for any reference that must hold a frequency channel.
• Oven-controlled crystal oscillator (OCXO): The crystal is held at a constant elevated temperature, which removes almost all of the temperature term and brings stability into the parts-per-billion region, with aging measured in parts per billion as well. The cost is a warm-up time of minutes and oven power measured in watts, which rules the part out of most battery-powered equipment.
• Voltage-controlled crystal oscillator (VCXO and VCTCXO): A crystal oscillator with a modest electrical tuning range, used where a loop must steer the oscillator itself. The tuning range is what a jitter-cleaning PLL trades against noise, and the section on jitter cleaning returns to it.

Stability in parts per million and phase noise are separate axes, and choosing on one while ignoring the other is a familiar mistake. An oven-controlled oscillator selected for parts-per-billion stability is not automatically the quietest source at the megahertz offsets a data converter integrates over, and an inexpensive oscillator with a low far-out noise floor may drift far outside what a telecommunications reference permits. Select against the specification the application actually constrains, then confirm the other. The resonators and oscillator products themselves are surveyed in Crystals and Oscillators, and the master references that anchor absolute accuracy in Time and Frequency Standards.

Phase Detector Types

The phase detector produces an output proportional to the phase difference between reference and feedback signals. Several detector types serve different applications:

• Analog multiplier (mixer): Multiplies the two input signals together. For sinusoidal inputs the product contains a term at twice the input frequency, which the loop filter removes, and a DC term proportional to the cosine of the phase difference. The characteristic is therefore linear only near quadrature, and the loop settles with its two inputs 90 degrees apart rather than aligned. Used in analog PLLs for carrier recovery and demodulation.
• XOR gate: Digital implementation whose output duty cycle varies with the phase difference, giving a linear characteristic across a 180-degree span centered, like the mixer, on quadrature. It demands inputs with a well-controlled duty cycle, because duty-cycle distortion appears directly as a static phase error, and it carries no frequency information, so it can settle at a harmonic of the intended frequency.
• Phase-frequency detector (PFD): Sequential logic circuit that detects both phase and frequency differences, enabling acquisition from any initial frequency offset. The standard choice for frequency synthesizers, because it steers frequency during acquisition, detects phase when locked, and settles with its inputs aligned rather than in quadrature.
• Bang-bang detector: Binary phase detector that outputs only early or late indications. Its effective gain depends on how much jitter is present at its input, which makes the dynamics of a bang-bang loop depend on signal conditions in a way a linear detector's do not. Used in high-speed clock and data recovery circuits where analog phase information is difficult to extract.

The phase-frequency detector typically drives a charge pump that sources or sinks current pulses into the loop filter. The pair behaves as a gain of I_CP / 2π amperes per radian of phase error, where I_CP is the charge-pump current, and the loop holds the static phase error near zero because the filter integrates any residual charge. One refinement matters in practice. A charge pump that switches fully off near zero phase error leaves a dead zone in which the loop has no gain and the output wanders. Designers remove the dead zone with a deliberate reset delay that turns both current sources on briefly during every comparison cycle. Any mismatch between the up and down currents during that overlap injects a periodic disturbance at the comparison frequency, which is a principal origin of reference spurs in charge-pump synthesizers.

Loop Filter Design

The loop filter shapes the PLL's dynamic response, determining bandwidth, stability, and jitter transfer characteristics. Filter design involves fundamental trade-offs:

• Bandwidth versus jitter: Higher bandwidth enables faster lock acquisition and better tracking of reference variations, but allows more reference and phase detector noise to pass to the output. Lower bandwidth provides better jitter filtering but slower response.
• Stability: The loop must maintain adequate phase margin, conventionally 45 to 60 degrees, to prevent oscillation or excessive ringing during transients.
• Lock time: Applications requiring fast frequency changes need higher bandwidth, while those prioritizing spectral purity favor narrow loops.

For the charge-pump loop that dominates modern practice, a series resistor R and capacitor C form the essential filter, and the second-order description of the loop follows directly from them:

ω_n = √(I_CP K_VCO / 2πNC)

ζ = RCω_n / 2

Units repay attention here, because the two conventions for VCO tuning gain differ by a factor of 2π. These expressions take K_VCO in radians per second per volt, so a data sheet quoting hertz per volt must be converted first. With I_CP in amperes, C in farads, and N dimensionless, the natural frequency ω_n emerges in radians per second. A damping factor between roughly 0.7 and 1 is the usual target for this idealization. Do not infer phase margin from it: a practical filter adds a further pole to suppress reference spurs, and that pole costs margin the second-order expression knows nothing about, so the margin has to be read from the actual open-loop response.

One limit constrains every charge-pump design. The continuous-time description above is an approximation, because the phase detector compares only once per comparison cycle rather than continuously. The approximation holds while the loop bandwidth stays well below the comparison frequency, and a loop bandwidth under roughly one-tenth of the comparison frequency is the customary guard. A design that pushes past it may look stable in a continuous-time simulation and prove unstable in hardware.

Common filter topologies include:

• Passive lag filter: Simple RC network providing single-pole response. Adequate for non-critical applications but offers limited design flexibility.
• Passive lead-lag filter: Adds a zero to improve phase margin while maintaining low-frequency integration. The standard choice for charge-pump PLLs.
• Active filter: Uses an operational amplifier for additional gain and more complex transfer functions. Enables higher-order filtering and greater design flexibility but adds noise and complexity.
• Digital filter: Implements the loop filter in the digital domain after sampling the phase error. Enables sophisticated algorithms and eliminates analog component variations but introduces quantization effects.

VCO Considerations

The voltage-controlled oscillator determines the PLL's output frequency range and contributes significantly to output phase noise. Key VCO parameters include:

• Tuning range: The span of frequencies the VCO can produce. Must cover all desired output frequencies plus margin for process, voltage, and temperature variations.
• Tuning gain (K_VCO): The sensitivity of output frequency to control voltage, quoted either in hertz per volt or in radians per second per volt, the two differing by a factor of 2π. A high tuning gain buys tuning range and pays for it twice: noise and ripple on the control line convert to frequency modulation in direct proportion to K_VCO, and the loop filter's own thermal noise reaches the VCO by that same path.
• Phase noise: Random fluctuations in the oscillator phase, typically specified as power spectral density at various offset frequencies from the carrier. VCO phase noise dominates PLL output noise at offsets beyond the loop bandwidth.
• Power consumption: Higher-performance VCOs generally consume more power. Low-power applications must balance performance against energy constraints.

VCO implementations include LC oscillators (using inductors and capacitors, offering lowest phase noise but large area), ring oscillators (compact and easily integrated but with higher phase noise), and relaxation oscillators (simple but with poor phase noise and frequency stability).

K_VCO is not a constant, and loop design suffers when it is treated as one. Across a wide tuning range the gain of a varactor-tuned oscillator commonly varies by a factor of two or more, being highest where the varactor characteristic is steepest and lowest at the ends of the range. Both the natural frequency and the damping factor above scale as the square root of K_VCO, so a loop tuned to textbook damping at one output frequency drifts toward underdamped ringing or sluggish acquisition at another. Two remedies are common. Integrated VCOs divide the range into many overlapping switched-capacitor sub-bands, which keeps the continuous tuning gain low and reasonably uniform inside each band while an automatic calibration picks the band during acquisition. Where that is not available, the synthesizer scales its charge-pump current with the division ratio so that the product I_CP K_VCO / N stays approximately constant as the output frequency changes.

PLL Noise and Jitter

A PLL presents two different transfer functions to the noise inside it, and a designer who remembers only one of them chooses the loop bandwidth wrongly. Measured from the reference input to the output, the loop is a low-pass filter: it tracks slow phase disturbances faithfully and attenuates fast ones above the loop bandwidth. Measured from the VCO to the output, the loop is a high-pass filter: feedback corrects slow VCO drift and cannot act on fast VCO noise, which therefore reaches the output unattenuated. The reference, the phase detector, the charge pump, and the feedback divider all sit on the low-pass side. The VCO alone sits on the high-pass side.

• Reference noise: Phase noise from the reference oscillator passes through the low-pass response and is multiplied by the ratio between the output frequency and the comparison frequency. Together with the detector, it sets the output noise at offsets below the loop bandwidth.
• Phase detector and charge pump noise: The noise of the comparison process is multiplied by the same ratio and shaped by the same low-pass response. In a synthesizer with a large division ratio it, rather than the reference, usually sets the noise floor inside the loop bandwidth. Vendors normalize this contribution to a division ratio of one and a comparison frequency of one hertz; the in-band floor then follows by adding 20 log₁₀(N) and 10 log₁₀ of the comparison frequency in hertz.
• Divider noise: The feedback divider adds phase noise on the low-pass side. In a fractional-N part the divider is also where the delta-sigma modulator injects its shaped quantization noise, which is treated below.
• VCO noise: The VCO's own phase noise reaches the output through the high-pass response. Inside the loop bandwidth the feedback suppresses it, at 40 dB per decade in the type-II loop that charge-pump synthesizers use; outside it, the VCO's free-running phase noise appears essentially unaltered and dominates the output.

The consequence of the first frequency relation is usually left unsaid, and it is the most important fact about frequency multiplication. Multiplying a frequency multiplies its phase, so a division ratio N multiplies the phase deviation by N and the phase-noise power by N², raising the phase-noise density inside the loop bandwidth by 20 log₁₀(N) decibels. The factor is 20 rather than 10 because the ratio scales the phase deviation and noise power follows its square: 10 log₁₀(N²) is 20 log₁₀(N). The rise is 6 dB for every doubling of N. A 10 MHz reference driving a 2.5 GHz output implies N = 250 and a penalty of about 48 dB, so a reference specified at −150 dBc/Hz at a 1 kHz offset cannot yield better than roughly −102 dBc/Hz at that offset at the output, whatever the rest of the design achieves.

That arithmetic also settles how to pick the comparison frequency. Doubling it halves N, which removes 6 dB, while the detector contribution grows by 3 dB because the comparison happens twice as often. The net gain of about 3 dB per doubling of comparison frequency is the most effective single lever on in-band phase noise, and it is the practical reason fractional-N synthesis earns its complications.

The correct loop bandwidth is therefore not a matter of taste. It is the offset at which the two curves cross. Plot the reference-side contribution, flat inside the band at the reference and detector noise raised by 20 log₁₀(N), against the free-running VCO phase noise, which falls steeply with offset. Below the crossover the reference side is the quieter of the two, so the loop should track and deliver it; above the crossover the free-running VCO is the quieter, so the loop should stop correcting and let the VCO stand on its own. Placing the loop bandwidth at the crossover therefore takes the lower of the two curves at every offset, which is what minimizes the integrated phase jitter. A narrower loop admits VCO noise over a wider range of offsets; a wider loop admits multiplied reference and detector noise over a wider range. This is why a clock generator fed by a superb reference wants a wide loop, and one built around a quiet LC VCO and a mediocre reference wants a narrow one.

Near the crossover the two contributions add, and a loop with modest damping shows gain slightly above unity in its reference-to-output response, so the phase-noise plot of a real synthesizer usually carries a small bump at the loop bandwidth. The bump is not merely cosmetic. Loops in cascade multiply their peaking, so a chain of equipment each containing a PLL of similar bandwidth accumulates it, which is why the jitter-transfer templates for chained transport equipment cap peaking at a small fraction of a decibel, a limit met by constraining the loop's damping.

What all of this optimization is worth depends on the load. For a data converter the governing figure is the RMS phase jitter obtained by integrating the output phase-noise spectrum over a stated offset band, and the ceiling it imposes is SNR_jitter = −20 log₁₀(2π f_in t_jitter), with f_in the analog input frequency. That integral, the choice of integration band, the difference between integrated phase jitter and period or cycle-to-cycle jitter, and the rules for combining independent contributions are set out in Clock and Reference Distribution. This page assumes those definitions rather than restating them.

Fractional-N Synthesis

An integer-N PLL produces only integer multiples of its comparison frequency, so fine resolution forces the comparison frequency down and the division ratio up, incurring the 20 log₁₀(N) penalty in full. Fractional-N synthesis breaks that coupling, letting the comparison frequency stay high while the average division ratio becomes fractional.

The mechanism has to be stated plainly, because the equation on its own misleads. No divider divides by a fraction. An accumulator makes the divider alternate between the adjacent integers N and N + 1, and only the average over many comparison cycles is fractional:

f_out = (N + k/m) f_ref

where the loop divides by N + 1 on k of every m comparison cycles and by N on the remaining m − k. The average output frequency is the intended one, but the instantaneous phase is not. Between corrections the feedback edge runs ahead of or behind the reference edge by up to a full VCO period, and the phase detector sees that error on every comparison. What the divider actually produces, then, is not a fractional ratio but a large periodic phase error, and that error is the whole difficulty of the technique.

In a simple accumulator-based divider the disturbance is periodic at the fractional part of the comparison frequency, (k/m) f_ref, with harmonics above it, and it appears at the output as discrete fractional spurs. The spurs are worst where the offset is smallest, which is to say when the requested channel sits close to an integer multiple of the comparison frequency, because then the disturbance falls deep inside the loop bandwidth where the filter cannot touch it. These integer-boundary spurs are the characteristic failure of early fractional-N parts, and the analog cancellation schemes built to suppress them held up poorly over process and temperature.

The modern answer is to make the divider sequence noise-like instead of periodic. A delta-sigma modulator chooses the instantaneous divider value so that its average equals the requested fraction while its quantization error is randomized and high-pass shaped. The discrete spurs become a noise pedestal, and the pedestal is pushed out to offsets where the loop filter removes it. That shaping is what makes the technique work, and it constrains the rest of the design:

• Modulator order: Because the divider quantizes frequency while the loop responds to phase, a modulator of order L shapes the resulting phase noise upward at 20(L − 1) decibels per decade of offset. A third-order modulator therefore produces a pedestal rising at 40 dB per decade, which must be well clear of the loop bandwidth before the loop filter can dispose of it.
• Loop bandwidth: The shaped noise rises with offset while the loop response falls, so a fractional-N loop has a maximum usable bandwidth that an integer-N loop of the same output frequency does not. Wideband fractional-N designs commonly add a filter pole purely to steepen the attenuation of the shaped noise.
• Divider range: A higher-order modulator needs the multi-modulus divider to swing across several consecutive integers rather than just two, which the divider architecture must support.
• Charge-pump linearity: Any nonlinearity in the phase detector and charge pump folds the shaped high-offset noise back down to low offsets, undoing the shaping. In practice a fractional-N synthesizer's in-band noise is often limited by charge-pump linearity rather than by the modulator, which is why up and down current matching receives such attention in these parts.

The reward is substantial and is frequently misstated. Because the comparison frequency no longer sets the frequency step, a fractional-N synthesizer runs its comparison at or near the full reference rate and keeps N small, worth roughly 3 dB of in-band phase noise for every doubling of comparison frequency. A well-designed fractional-N part therefore reaches better in-band phase noise than an integer-N part of the same output frequency and the same resolution, not worse. What it gives up is freedom from spurs: residual fractional spurs, and the shaped pedestal itself, remain the things to look for on a spectrum analyzer.

PLL Applications in Clock Generation

PLLs serve numerous clock-related functions:

• Frequency synthesis: Generating precise frequencies from a crystal reference for processor clocks, communication systems, and data converters.
• Clock multiplication: Producing high-frequency internal clocks from lower-frequency external references in microprocessors and FPGAs.
• Jitter cleaning: Filtering high-frequency jitter from degraded clock signals by leveraging the loop's low-pass response to VCO noise.
• Clock recovery: Extracting timing information from data streams in serial communication links.
• Spread-spectrum clocking: Modulating the output frequency to reduce electromagnetic interference peaks.

DLL Architecture and Operation

A basic DLL consists of a voltage-controlled delay line, a phase detector, and a loop filter. The delay line receives the input clock and produces a delayed version. The phase detector compares this delayed clock (or a derived signal) with the reference, producing an error signal that adjusts the delay to achieve the desired phase relationship.

Unlike a VCO, which produces arbitrary frequencies, a delay line merely shifts the phase of its input. The output frequency precisely equals the input frequency; only the phase changes. This characteristic eliminates the frequency multiplication jitter peaking that can occur in PLLs.

Common DLL configurations include:

• Edge-aligned DLL: Adjusts delay until the output edge aligns with the next input edge, providing one full period of delay.
• Phase-aligned DLL: Maintains a specific phase relationship (such as zero phase difference) between input and output.
• Multi-phase DLL: Uses a delay line with multiple taps to generate several clock phases at precise intervals.

DLL Versus PLL Trade-offs

The choice between DLL and PLL depends on application requirements:

• Jitter transfer: DLLs exhibit first-order low-pass jitter transfer without peaking, while PLLs show second-order response with potential jitter peaking. DLLs never amplify input jitter, making them preferable for jitter-sensitive applications.
• Frequency synthesis: PLLs can multiply, divide, and synthesize arbitrary frequencies. DLLs cannot change frequency, only phase.
• Lock range: PLLs can acquire lock from any initial frequency within their capture range. DLLs have limited phase adjustment range (typically one clock period) and may falsely lock to harmonics.
• Accumulated jitter: DLL output jitter does not accumulate from cycle to cycle as it can with PLLs, since the delay line references the input directly rather than generating free-running oscillation.
• Phase noise: DLLs pass through input phase noise, while PLLs filter it based on loop bandwidth. For clean reference sources, this makes little difference, but for noisy sources, PLLs may provide superior cleaning.

Multi-Phase Clock Generation with DLLs

One of the most valuable DLL applications is generating multiple evenly spaced clock phases. A delay line with multiple taps, locked to provide exactly one period of total delay, automatically produces phases spaced by equal fractions of the period:

For an N-stage delay line locked to one period, each tap provides a phase offset of 360/N degrees. This technique appears extensively in:

• DDR memory interfaces: DLLs generate the 90-degree shifted clocks needed for center-aligned data capture.
• High-speed serial interfaces: Multi-phase clocks enable oversampling receivers and phase interpolation for data recovery.
• Interleaved ADCs: Multiple converter cores operating on offset phases increase effective sample rate.

Delay Line Implementations

The voltage-controlled delay line can be implemented in several ways:

• Current-starved inverters: A chain of inverters with controllable supply current adjusts propagation delay through voltage-controlled current sources. Simple and compact but with moderate delay range and sensitivity to supply noise.
• Shunt capacitor tuning: Varactors or switched capacitors at delay cell outputs vary the load capacitance and thus the delay. Provides good linearity but limited range.
• Differential delay cells: Differential buffers with variable load or tail current offer improved noise immunity and common-mode rejection, preferred for high-performance applications.
• Digitally-controlled delay: Switched banks of delay elements provide discrete delay steps. Eliminates analog control line but requires fine granularity for adequate resolution.

DLL Design Considerations

Practical DLL design addresses several challenges:

• Harmonic locking: A DLL with excessive delay range may lock with multiple periods of delay instead of one, producing incorrect phase relationships. Limiting delay range or using harmonic detection circuits prevents this.
• Start-up conditions: Initial delay may be anywhere within the adjustment range. The loop must be designed to acquire lock reliably from any starting point.
• Duty cycle distortion: Unequal rise and fall times in delay elements can accumulate along the delay line, distorting the output duty cycle. Differential designs and duty cycle correction circuits address this.
• Power supply sensitivity: Delay elements are sensitive to supply voltage variations, which can cause jitter. Supply filtering and differential techniques improve immunity.

CDR Fundamentals

Unlike a clock signal with regular transitions, data signals exhibit transitions only when bits change state. A long run of identical bits produces no transitions, yet the CDR must maintain correct timing throughout. This creates the fundamental CDR challenge: extracting phase information from sparse, irregular transitions while maintaining low jitter during data patterns with few transitions.

The basic CDR approach uses a phase-locked loop structure where the phase detector operates on data transitions rather than clock edges. When a transition occurs, the detector measures whether the recovered clock is early or late relative to the transition. When no transition occurs, the detector produces no correction, and the loop holds its previous state.

CDR Architectures

Several CDR architectures address different requirements:

• Linear CDR: Uses analog phase detectors (such as a Hogge detector or Alexander detector) that produce output proportional to phase error. The analog error signal drives a VCO through a loop filter. Offers good tracking bandwidth but requires careful analog design.
• Bang-bang CDR: Uses a binary phase detector that produces only early or late indications. Simpler to implement at high speeds where analog phase measurement is impractical. The digital output modulates a VCO or digitally controlled oscillator through a digital loop filter.
• Oversampling CDR: Samples the incoming data at multiple phases per bit period, then digitally selects or interpolates to find the optimal sampling point. Avoids analog VCO control loops but requires higher-speed sampling circuits.
• Injection-locked CDR: Uses an oscillator that injection-locks to the data transitions, inherently filtering jitter while maintaining phase alignment. Effective for applications with dense transition patterns.

Jitter Tolerance and Transfer

CDR performance is characterized by two key metrics:

• Jitter tolerance: The amount of input jitter (as a function of jitter frequency) that the CDR can track without bit errors. At low frequencies, the loop can track large phase excursions. At high frequencies, tracking ability diminishes, and tolerance is limited to some fraction of a unit interval.
• Jitter transfer: How input jitter appears on the recovered clock. A narrow-bandwidth CDR filters high-frequency jitter but tracks low-frequency wander. A wide-bandwidth CDR passes more jitter but tolerates larger high-frequency excursions.

These metrics often conflict: applications requiring good jitter filtering need narrow bandwidth, which reduces tolerance. Those requiring tolerance of large jitter need wider bandwidth, which passes more jitter to the output. System design must balance these requirements based on the expected jitter environment.

Run-Length Considerations

Long runs of identical bits without transitions challenge CDR circuits by starving the phase detector of correction opportunities. During a long run, the recovered clock frequency and phase depend entirely on VCO stability and loop filter memory.

Line coding schemes limit maximum run length:

• 8b/10b encoding: Maps 8-bit data words to 10-bit symbols with guaranteed transition density. Provides DC balance and limits run length to 5 bits.
• 64b/66b encoding: Higher-efficiency coding that prepends a 2-bit synchronization header for block alignment and scrambles the 64-bit payload to guarantee frequent transitions. Used in 10 Gigabit Ethernet and later Ethernet rates; PCI Express generations 3 through 5 use a closely related 128b/130b scheme with lower overhead.
• Scrambling: XORs data with a pseudo-random sequence to randomize bit patterns, ensuring adequate transition density statistically. Used where encoding overhead is unacceptable.

CDR loop bandwidth must be low enough to coast through the maximum run length without excessive drift, yet high enough to track the data rate variations caused by reference frequency differences between transmitter and receiver.

Reference-Based Versus Referenceless CDR

Some CDR architectures incorporate a local reference oscillator:

• Referenceless CDR: A VCO free-runs at approximately the data rate and locks to the incoming transitions. Simple but with frequency that can drift significantly without transitions, and may have difficulty acquiring lock on power-up or after loss of signal.
• Reference-based CDR: A PLL locks the VCO to a local reference oscillator, providing a stable center frequency. A second loop or phase interpolator tracks the data phase. Offers faster acquisition and better frequency stability but adds complexity and the requirement for a reference.

Modern high-speed transceivers typically use reference-based architectures with digitally controlled phase interpolators, combining the frequency stability of a PLL with the phase tracking capability needed for CDR.

EMI Reduction Mechanism

A fixed-frequency clock produces a line spectrum with energy concentrated at the fundamental and harmonic frequencies. A measuring receiver reports the power falling inside its resolution bandwidth, which for radiated measurements between 30 MHz and 1 GHz is 120 kHz. Spreading the clock across a band wider than that resolution bandwidth distributes the energy, so less of it lands inside the receiver at any one moment. The approximate reduction in the measured peak is:

Reduction = 10 log₁₀(spread bandwidth / resolution bandwidth)

where the spread bandwidth is the total peak-to-peak frequency excursion, that is, the spread percentage multiplied by the carrier frequency. For a 100 MHz clock spread over ±0.5% (1 MHz in total), the reduction against a 120 kHz resolution bandwidth is approximately 9 dB, which is often the difference between passing and failing a compliance test.

That expression repays careful reading, because it does not say what it is commonly taken to say. Both of its terms describe the measurement rather than the emission. Spread-spectrum clocking removes no energy whatever: the total radiated power is exactly what it was, merely redistributed in frequency. What falls is the power inside one resolution bandwidth. The benefit to a real victim therefore depends on the victim's own bandwidth. A narrowband receiver tuned near the clock harmonic collects only a fraction of the spread energy and genuinely suffers less. A victim whose bandwidth exceeds the spread collects all of it and gains nothing at all. Spread-spectrum clocking is a legitimate and effective compliance tool, but treating it as a reduction in emitted energy produces designs that pass the chamber and still interfere.

Three further details govern how much reduction appears on the test receiver:

• Harmonics spread further. The nth harmonic of a clock spread by a fixed percentage occupies n times the absolute bandwidth, so the reduction improves with harmonic number, ideally by a further 10 log₁₀(n) decibels. Measurements follow that trend without matching it closely.
• The resolution bandwidth changes at 1 GHz. Radiated measurements above 1 GHz use a 1 MHz resolution bandwidth rather than 120 kHz, which by itself removes about 9 dB from the predicted benefit. The wider absolute spread of the high harmonics involved roughly offsets it, so the figure is neither dramatically better nor dramatically worse above 1 GHz. It simply has to be recomputed for that band rather than carried across.
• The detector matters. The expression describes what a peak detector reads. Regulatory limits between 30 MHz and 1 GHz are quasi-peak limits, and a quasi-peak detector weights its reading by how often the disturbance recurs, so the improvement recorded in a compliance measurement frequently differs from the prediction. Confirm the benefit using the instrument configuration the compliance test will use.

Modulation Profiles

The frequency modulation pattern affects both EMI reduction and system compatibility:

• Triangular modulation: Frequency sweeps linearly up and down, spending equal time at all frequencies within the spread range. Simple to generate and provides uniform spectral spreading.
• Hershey Kiss profile: A shaped sweep, neither triangular nor sinusoidal, chosen to flatten the resulting spectral envelope. A pure sinusoidal sweep lingers at its turning points and raises horns at the edges of the spread band; the shaped profile suppresses them and typically buys a decibel or two over a triangular sweep.
• Down-spread: Frequency modulates only below the nominal value, never exceeding it. Critical for timing-critical applications where exceeding the nominal frequency might cause timing violations. Common in computer applications.
• Center-spread: Frequency modulates equally above and below nominal. Provides greater spreading range for the same peak deviation but may cause setup timing problems if nominal frequency is already at the maximum the system can tolerate.

Implementation Techniques

Spread-spectrum clocking can be implemented at various points in the clock generation chain:

• Modulated VCO: Superimposing a low-frequency modulation signal on the PLL control voltage varies the VCO frequency. It is simple, but the loop treats the modulation as an error and suppresses whatever part of it falls inside the loop bandwidth, so the method works only where the loop bandwidth sits below the modulation rate.
• Fractional-N modulation: Varying the feedback divider ratio in a fractional-N PLL produces precise frequency modulation under digital control, and the modulation enters on the low-pass side of the loop where it is faithfully reproduced. This is the most common approach in modern clock generators.
• Delta-sigma modulation: High-order delta-sigma modulators shape the dithering pattern to minimize spurious tones while achieving the desired frequency spreading.

Modulation rates sit in the tens of kilohertz. Link specifications fix the figure narrowly, PCI Express at 30 to 33 kHz, and general-purpose clock generators work in the same region. The lower bound keeps the modulation above the audio band and ensures that many modulation cycles occur while the measuring receiver dwells on each frequency. The upper bound keeps the modulation slow enough for downstream PLLs and clock recovery loops to track it.

System Considerations

Spread-spectrum clocking affects system timing and must be considered in timing analysis:

• Timing margins: Down-spread never exceeds the nominal frequency, so setup timing is no worse than it was at the nominal rate, which is precisely why computer systems favor it. What it costs is throughput: with a triangular profile the average frequency falls by about half the spread, so a 0.5% down-spread surrenders roughly 0.25% of the clock cycles. Center-spread makes the opposite trade, keeping the average frequency but requiring the timing analysis to close at the upper extreme of the spread rather than at nominal.
• Clock-to-clock relationships: All clocks derived from the same spread-spectrum source track together, maintaining their relative timing. However, if clocks from different sources are used together, the spreading causes their relative timing to vary by the full modulation amount.
• Data converters: A spread clock is a deliberate phase modulation, and its timing excursion is larger than intuition suggests. The peak phase deviation equals the frequency deviation divided by the modulation rate, so a slower modulation produces a larger timing excursion rather than a smaller one. A 100 MHz clock modulated sinusoidally with 0.5 MHz of peak deviation at 32 kHz departs from an unmodulated ideal by roughly 25 nanoseconds at the extremes of the sweep, about two and a half clock periods. The modulation also lies at tens of kilohertz, inside the 12 kHz to 20 MHz band over which converter clock jitter is conventionally integrated, so it counts in full. Sampling clocks for precision converters are not spread.
• Serial links: Clock recovery in the receiver must track the modulation, so link specifications bound its depth and its rate together. PCI Express permits up to 5000 ppm (0.5%) of down-spread at a modulation rate of 30 to 33 kHz, and receiver clock recovery must tolerate the resulting phase excursion. A link whose two ends derive from the same spread source, or that forwards its clock alongside the data, tracks the modulation on both ends and is unaffected; a receiver locked to an independent reference must absorb the whole excursion in its recovery loop and its elastic buffer.
• Where spreading is unacceptable: A clock that times a synchronous interface whose far end does not share the modulation must not be spread, because the two ends then disagree about time by the full excursion, and a synchronous interface, unlike a serial link, has no elastic buffer in which to absorb it. The same prohibition covers sampling clocks for data converters, any clock serving as a frequency or time reference, and clocks feeding measurement instruments. Spreading is a deliberate frequency error, and wherever frequency accuracy is the point, a deliberate error is still an error.

Jitter Sources and Types

Understanding jitter sources is essential for effective cleaning:

• Random jitter: Unbounded Gaussian-distributed timing variations from thermal noise, shot noise, and other random processes. Characterized by RMS value but with long-term extremes that can extend indefinitely.
• Deterministic jitter: Bounded timing variations with identifiable causes including periodic jitter (from power supply coupling or crosstalk), data-dependent jitter (from intersymbol interference), and duty cycle distortion.
• Wander: Very low-frequency phase variations, typically below 10 Hz, caused by temperature changes, reference aging, and other slow effects.

Different jitter types respond differently to cleaning. Periodic jitter at a discrete frequency is filtered if that frequency lies above the loop bandwidth and is tracked, unchanged, if it lies below. Random jitter is attenuated across the whole band above the loop bandwidth, at the cost of substituting the loop's own oscillator noise there. Wander is normally tracked rather than filtered, because a synchronization application requires the output to follow the network's long-term frequency.

Those three categories describe where jitter comes from. They are not the same thing as the four numbers by which a clock's jitter is measured, and the two sets are frequently confused. Time interval error, period jitter, cycle-to-cycle jitter, and accumulated jitter over N cycles each answer a different question, and a converter's aperture budget requires none of them but rather the RMS phase jitter integrated from a phase-noise spectrum over a stated offset band. Those distinctions, and the reason substituting one for another can overstate a degradation by an order of magnitude, are set out in Clock and Reference Distribution, with the instrumentation in Jitter Measurement.

PLL-Based Jitter Cleaning

A PLL cleans jitter for exactly the reason set out earlier: the loop is low-pass to its input and high-pass to its own oscillator. Taking input jitter components at offset frequency f_j against a loop bandwidth f_BW:

• f_j ≪ f_BW: the loop tracks the input, and the jitter reaches the output with little attenuation.
• f_j ≫ f_BW: the loop cannot follow, and the jitter is attenuated, at 20 dB per decade for a single-pole response and more steeply where the filter adds poles.

The oscillator obeys the complementary rule, and forgetting it is how jitter cleaners get designed backwards. VCO phase noise below f_BW is suppressed by the loop; VCO phase noise above f_BW is not. Narrowing the loop therefore does not clean the output in any general sense. It replaces the input's high-offset noise with the local oscillator's own, which is an improvement only when the local oscillator is the quieter of the two, and a degradation when it is not.

Choosing the bandwidth is the crossover argument made earlier, with the input phase noise standing in for the reference. Where the input carries substantial high-offset jitter and the local oscillator is quiet, the loop should be narrow, and a cleaner built around a crystal-based oscillator can be very narrow indeed, with bandwidths from a few hertz to a few hundred hertz. Where the input is already clean and the local oscillator is an ordinary integrated VCO, the loop should be wide. Wander below the loop bandwidth is tracked rather than filtered, which is what a synchronization application requires.

Cascaded PLL Architectures

Multiple PLLs in cascade can achieve greater jitter attenuation than a single stage:

• First stage: A narrow-bandwidth PLL attenuates high-frequency input jitter and produces a cleaner clock at the same or multiplied frequency.
• Second stage: Another PLL further attenuates residual jitter while potentially providing additional frequency synthesis.

Cascading provides multiplicative jitter attenuation, with each stage contributing its own filtering. However, each stage also adds its own noise contributions, so diminishing returns eventually occur. Practical jitter cleaners typically use one or two stages.

VCXO-Based Jitter Cleaning

Where the output must be quieter than any integrated oscillator can manage, the cleaning loop is built around a crystal rather than an LC or ring VCO:

• Voltage-controlled crystal oscillator (VCXO): A crystal oscillator with a limited electrical tuning range, commonly ±50 to ±100 parts per million and rarely beyond a few hundred. The crystal's high quality factor yields phase noise far below that of an integrated VCO, so the loop can be narrow without the output degrading at high offsets.
• The tuning range is the trade: The same high quality factor that makes the crystal quiet is what makes it hard to pull, and the two cannot be separated. A narrow pull range restricts the frequencies the loop can synthesize and demands close frequency agreement between the input and the crystal, which is the price paid for the noise performance.
• Holdover: When the input disappears, a crystal-based loop coasts on an oscillator whose free-running accuracy is measured in parts per million rather than percent, so the output frequency stays usable for far longer. This is why network synchronization equipment uses crystal-based cleaners almost universally.

Digital Jitter Attenuation

Digital techniques offer an alternative to analog jitter cleaning:

• Digital phase-locked loops: Measure phase error digitally, filter in the digital domain, and control a digitally controlled oscillator (DCO). Enable sophisticated filtering algorithms and eliminate analog component variations.
• Timestamp-based approaches: Precisely measure input edge timing, apply digital filtering to the timestamp sequence, and regenerate edges at the filtered times. Separates jitter measurement from output generation.
• FIFO-based dejitter: Buffer data (or clock edges) in a FIFO and read out at a locally generated clean clock rate. Effective for packetized data but requires elastic storage to accommodate rate variations.

Jitter Cleaner ICs

Integrated jitter cleaner devices provide optimized solutions for various applications:

• Network synchronization: Devices built against Telcordia GR-1244-CORE, which defines the clock stratum levels for the synchronized network, or against ITU-T G.8262, which defines the Synchronous Ethernet equipment clock, provide specified jitter filtering, jitter transfer, and holdover behavior rather than a single jitter number.
• Data converter clocking: Cleaners intended for converter clocking reach RMS phase jitter below 100 femtoseconds, and the better parts well below it. The figure is meaningless without its band, which for these devices is conventionally 12 kHz to 20 MHz, and comparing two parts integrated over different bands compares nothing.
• General-purpose cleaning: Flexible devices with programmable loop bandwidth and multiple output formats serve a variety of clock conditioning needs.

Sources of Duty Cycle Distortion

Duty cycle deviations arise from several sources:

• Unbalanced drive strength: Different pull-up and pull-down transistor sizes or drive currents cause unequal rise and fall times, shifting the crossing point.
• Threshold variations: If subsequent stages have input thresholds that differ from the signal's midpoint, duty cycle shifts.
• Capacitive loading asymmetry: Unequal capacitance on rising versus falling edges causes differential delay.
• Power supply droop: Varying supply voltage during clock transitions can affect rise and fall times differently.
• Cumulative effects: Duty cycle errors from multiple buffer stages accumulate through a distribution network.

Feedback-Based Correction

Feedback duty cycle correction circuits measure the actual duty cycle and adjust circuit parameters to achieve 50%:

• Integrator approach: Integrate the clock signal over many cycles. A 50% duty cycle produces zero average DC value. Any deviation from 50% creates a non-zero average that drives a correction circuit.
• Pulse width comparison: Compare the widths of positive and negative half-cycles using delay-matched paths. The difference drives a correction loop.
• Phase detector approach: Use a delay line to shift the clock by exactly half a period (verified by comparing with the inverted clock). The delay control signal adjusts buffer timing to correct duty cycle.

Feedback correction converges to 50% duty cycle regardless of initial distortion, making it robust against process and temperature variations.

Open-Loop Correction

Some applications use open-loop techniques that balance rise and fall times without direct duty cycle measurement:

• Matched differential buffers: Fully differential signal paths with matched loads inherently maintain duty cycle through symmetry.
• Complementary drivers: Carefully sized PMOS and NMOS output stages with matched current capability produce equal rise and fall times.
• Current-mode logic (CML): Differential circuits with constant tail current avoid the supply-dependent delays of rail-to-rail CMOS.

Open-loop approaches are simpler but rely on component matching that may degrade with process variations and temperature changes.

Integration with Clock Distribution

Duty cycle correction is often incorporated into clock distribution systems:

• DLL-based distribution: Multi-phase DLLs can detect and correct duty cycle by comparing phase spacing between rising and falling edges.
• Clock buffer ICs: Commercial clock buffers increasingly include duty cycle correction to guarantee output quality regardless of input distortion.
• Receiver-side correction: High-speed interfaces often include duty cycle correction at the receiver, compensating for distortion accumulated during transmission.

Applications of Multi-Phase Clocks

Multi-phase clocking enables numerous important techniques:

• Interleaved ADCs: Multiple ADC cores operating on offset phases sample at N times the rate of a single converter, with outputs combined to form a single high-speed data stream.
• Time-interleaved sample-and-hold: Successive sample phases capture the input at different times, enabling effective sample rates beyond single-stage limitations.
• DDR and multi-rate interfaces: Data transfer on multiple clock phases increases effective bandwidth without increasing the fundamental clock frequency.
• Phase interpolation: Multiple phases provide reference points for interpolating arbitrary intermediate phases, used in CDR circuits and precision timing applications.
• Polyphase filtering: Decomposing a filter across multiple clock phases reduces individual component requirements while maintaining filter performance.

DLL-Based Phase Generation

Delay-locked loops naturally produce multiple clock phases when the delay line includes intermediate taps:

• Uniform phase spacing: When a DLL locks with one period of total delay, N equally spaced taps produce phases at 0, 360/N, and 2 × 360/N degrees, and so on around the cycle.
• Inherent matching: All phases derive from the same delay line, ensuring matched characteristics and minimal phase noise between phases.
• Limited phase count: Practical delay lines support perhaps 4 to 16 phases; finer resolution requires phase interpolation between taps.

Ring Oscillator Phase Generation

A ring oscillator inherently produces multiple phases, one at each stage:

• Built-in phases: An N-stage differential ring oscillator produces 2N equally-spaced phases, 180/N degrees apart, because each stage contributes half a phase step and the loop inverts once per traversal. A single-ended ring requires an odd number of stages to oscillate and yields the same 2N phases once the inverted node outputs are included.
• PLL integration: When the ring oscillator serves as the VCO in a PLL, all phases are frequency-locked to the reference with good relative phase accuracy.
• Phase noise correlation: Noise from the common oscillator affects all phases similarly, reducing relative phase noise between adjacent phases while maintaining absolute phase noise.

Phase Interpolation

Phase interpolation generates arbitrary phases between two reference phases:

• Weighted summing: Combining two phase-offset clocks with variable weights produces an output at an intermediate phase. The phase shifts continuously as the weight ratio changes.
• Digital control: Digital weight selection enables precise, programmable phase adjustment with resolution limited by the number of control bits.
• Rotary phase selection: In multi-phase systems, selecting which pair of phases to interpolate between allows full 360-degree phase coverage.

Phase interpolators appear extensively in high-speed transceivers, where they provide the fine phase adjustment needed for clock and data recovery circuits to track incoming data edges precisely.

Phase Accuracy and Mismatch

Multi-phase systems require careful attention to phase accuracy:

• Systematic errors: Consistent phase spacing errors (such as from layout asymmetry) can be calibrated out through one-time or periodic measurement.
• Random mismatch: Manufacturing variations cause random phase errors between nominally identical stages. Careful matching and averaging techniques minimize these effects.
• Interleaving spurs: In interleaved ADCs, timing mismatch between channels creates spurious tones offset from the input tone, at k f_s/N ± f_in for integer k, where N is the interleave factor and f_s the aggregate sampling rate. Offset mismatch between channels produces a separate family of tones at multiples of f_s/N that sit at fixed frequencies regardless of the input. The timing spurs grow with input frequency while the offset spurs do not, which is how the two are told apart on a spectrum. Calibration is essential for high-performance interleaved converters.

The Metastability Problem

Digital flip-flops require data to be stable during a setup time before and hold time after the clock edge. When a signal crosses between unrelated clock domains, violations of these timing requirements are inevitable. Violating timing constraints puts the flip-flop into metastability, a condition where the output may hover at an intermediate voltage for an indeterminate time before eventually resolving to a valid logic level.

Metastability cannot be prevented in truly asynchronous systems, but its effects can be managed:

• Resolution time: Given sufficient time, a metastable flip-flop will resolve to a valid state with high probability. The probability of remaining metastable decreases exponentially with available resolution time.
• Mean time between failures (MTBF): The expected time between metastability-induced system failures, calculated from clock frequency, data transition rate, and flip-flop metastability parameters.
• Synchronizer design: Multiple flip-flop stages provide additional resolution time, increasing MTBF exponentially with each stage.

Two-Flop Synchronizers

The basic synchronizer uses two flip-flops in series, both clocked by the destination domain clock:

• The first flip-flop captures the asynchronous input and may go metastable
• The full clock period before the second flip-flop samples provides resolution time
• The second flip-flop's output is synchronous to the destination clock

Key design considerations include:

• Flip-flop selection: Use flip-flops with good metastability characteristics (fast resolution time constant). Avoid using standard cells without verified metastability data.
• Placement: Minimize routing between the two synchronizer flip-flops to maximize available resolution time.
• Operating conditions: Metastability behavior degrades at low voltage and high temperature. Design for worst-case conditions.

Single-Bit Versus Multi-Bit Crossing

Single-bit signals (such as status flags or request signals) can use simple two-flop synchronizers. Multi-bit values require additional care:

• Multi-bit problem: If multiple bits change simultaneously and are captured at different times due to metastability, the destination sees an incorrect intermediate value.
• Gray coding: Encoding multi-bit values so only one bit changes per transition eliminates the multi-bit problem. If the single changing bit is captured on either side of its transition, the decoded value is either the old or new value, never an invalid intermediate.
• Handshake protocols: Passing data with request/acknowledge handshaking ensures the data is stable before the receiver samples it. Adds latency but guarantees correctness for arbitrary data widths.

Asynchronous FIFOs

First-in-first-out (FIFO) buffers provide the most flexible solution for clock domain crossing of data streams:

• Operation: The write side pushes data at the source clock rate; the read side pulls data at the destination clock rate. The buffer absorbs timing differences between the domains.
• Pointer synchronization: Write and read pointers must be synchronized across domains to generate full and empty status signals. Gray-coded pointers enable safe synchronization.
• Depth requirements: The FIFO must be deep enough to absorb worst-case rate differences and bursts. For plesiochronous clocks with a known maximum frequency offset, the required depth depends on the offset and the maximum time between opportunities to transfer data.

Asynchronous FIFOs are fundamental building blocks in mixed-signal systems, network interfaces, and any system with multiple clock domains.

Pulse Synchronization

Transferring event pulses (single-cycle signals) requires special handling:

• Pulse width problem: If the source clock is faster than the destination, a single-cycle pulse may be entirely between destination clock edges and never captured.
• Pulse stretching: Hold the pulse high until acknowledged by the destination domain, guaranteeing capture.
• Toggle synchronization: Convert the pulse to a level toggle, synchronize the toggle, and detect edges on the synchronized signal to regenerate pulses in the destination domain.

CDC Verification

Verifying correct clock domain crossing is critical:

• Static analysis tools: Automated CDC checking tools identify crossing points and verify proper synchronization structures. These tools are essential for complex designs with many clock domains.
• Formal verification: Mathematical proof techniques can verify that CDC structures maintain data integrity under all possible timing relationships.
• Simulation limitations: Standard RTL simulation cannot model metastability effects. Special techniques or tools that inject metastability-like behavior are needed to stress-test CDC designs.