Electronics Guide

Differential Nonlinearity (DNL)

Differential nonlinearity measures the deviation of each code transition width from the ideal value of one least significant bit (LSB). In an ideal converter, each digital code corresponds to exactly the same analog range, and incrementing the code by one always represents the same analog change. Real converters exhibit variations in step sizes.

DNL is expressed as:

DNL(k) = [V(k + 1) − V(k)] / V_LSB − 1

where V(k) is the code transition level at code k and V_LSB is the ideal step size. The measurement is made after static gain and offset have been removed, so DNL describes step-to-step behavior alone. A DNL of zero indicates a perfect step; positive DNL means the step is wider than ideal, and negative DNL means it is narrower. Note that the widths of the top and bottom bins are undefined, because each is bounded on one side by the end of the input range rather than by a transition.

Key characteristics of DNL:

• Missing codes: an ADC code bin cannot have negative width, so ADC DNL cannot fall below −1 LSB. A DNL of exactly −1 LSB means the bin has zero width and the code never appears, which is a missing code. Because an exact −1 is unmeasurable in the presence of noise, IEEE Std 1241 declares code k missing when DNL(k) ≤ −0.9 LSB. A DAC behaves differently: its DNL can go below −1 LSB, and when it does the output steps backwards
• Monotonicity guarantee: DNL greater than −1 LSB at every code guarantees that a DAC is monotonic and that an ADC has no missing codes, so the output always increases, or at worst stays the same, as the input increases
• Histogram testing: DNL is measured efficiently by histogram methods, using either a linear ramp or a sine wave; the two stimuli demand different normalization, as the section on histogram testing below explains
• Major code transitions: The largest DNL errors typically occur at major code transitions (powers of two) where the most significant internal elements switch

For a 16-bit converter with 2 V full-scale range, one LSB equals approximately 30.5 microvolts. A DNL specification of ±0.5 LSB means each step width falls between 15.3 and 45.8 microvolts.

Integral Nonlinearity (INL)

Integral nonlinearity quantifies the cumulative deviation of the actual transfer function from an ideal straight line. While DNL describes local step-to-step variations, INL captures the overall shape of the transfer function.

INL at code k can be calculated as the running sum of the DNL values below that code:

INL(k) = Σ DNL(i), summed over i = 1 to k, with INL(0) = 0

An INL figure means nothing without the fitting convention that produced it, and there are two. The endpoint, or terminal-based, convention draws the reference line through the first and last code transitions, which forces INL to zero at both ends. That is precisely what the running sum above produces once gain and offset have been removed, so the sum and the endpoint definition agree by construction. The best-fit, or independently based, convention instead fits a least-squares line through the whole transfer curve, optimizing position and slope together.

The two conventions give materially different numbers for the same silicon. Best-fit almost always reports the smaller value, because it absorbs part of the curvature into the fitted slope, and for a strongly bowed transfer curve the gap approaches a factor of two. Compare two converters only when both are quoted on the same basis, and expect a datasheet to say which it used.

INL characteristics:

• Bow shape: INL often exhibits a characteristic bow shape, accumulating through the code range and returning toward zero at full scale
• Architecture dependence: Different converter architectures produce characteristic INL patterns; pipeline ADCs may show discontinuities at stage boundaries
• Temperature sensitivity: INL often varies with temperature as internal component matching changes
• Relationship to accuracy: INL directly limits the absolute accuracy of the conversion; a 10-LSB INL error means the digital output could be wrong by up to 10 counts

Offset Error

Offset error represents a constant shift in the transfer function, displacing all codes by the same amount. An ideal converter produces its first code transition at exactly 0.5 LSB above analog zero; offset error shifts this transition point.

Sources of offset error include:

• Comparator offset: Input offset voltage of the comparison circuits
• Reference offset: Errors in the reference voltage generation or distribution
• Input stage offset: DC errors in buffer amplifiers or input networks
• Leakage currents: Offset-inducing currents in high-impedance nodes

Offset error is typically specified in LSBs or as a percentage of full scale. Unlike INL and DNL, offset error can often be calibrated out by subtracting a stored correction value from each conversion result.

Gain Error

Gain error describes the deviation of the transfer function slope from the ideal value. An ideal converter spans exactly the specified full-scale range; gain error causes the span to be slightly larger or smaller.

Gain error is typically measured after offset correction and is expressed as:

Gain error = (Actual span / Ideal span − 1) × 100%

or equivalently in LSBs at full scale.

Sources of gain error:

• Reference voltage error: The primary source; reference accuracy directly determines gain accuracy
• Resistor ratio errors: In resistive divider-based converters, matching errors affect gain
• Temperature drift: Reference and resistor temperature coefficients cause gain drift
• Loading effects: External loading on reference or output stages can alter gain

Like offset, gain error can often be calibrated by scaling the digital output. Many precision applications perform both offset and gain calibration using known reference inputs.

Monotonicity

A monotonic converter guarantees that the output always increases (or at least stays the same) as the input increases. For ADCs, this means larger analog inputs always produce equal or larger digital codes. For DACs, higher digital codes always produce equal or higher analog outputs.

Monotonicity is guaranteed when DNL exceeds −1 LSB at every code. For an ADC the equivalent guarantee is stated as "no missing codes," and it is often specified at a lower resolution than the converter's word width: a 16-bit ADC may be guaranteed no missing codes only to 14 bits. Non-monotonic behavior causes serious problems in feedback control systems, where a controller can oscillate between codes that do not maintain proper ordering.

Some converter architectures inherently guarantee monotonicity:

• Thermometer-coded DACs: Always monotonic because elements are only added, never subtracted
• Integrating ADCs: Inherently monotonic due to their integration-based conversion
• Delta-sigma converters: Generally monotonic due to their oversampled, noise-shaped operation

Signal-to-Noise Ratio (SNR)

Signal-to-noise ratio measures the ratio of signal power to noise power within the Nyquist bandwidth, excluding harmonic distortion components. It captures the fundamental noise limitation of the converter.

SNR = 10 log₁₀(P_signal / P_noise) dB

For an ideal converter, quantization noise sets the SNR limit. The theoretical maximum SNR for an ideal N-bit converter is:

SNR_ideal = 6.02N + 1.76 dB

The figure follows from two RMS values. A full-scale sinusoid in an N-bit converter of step size q has peak amplitude 2^Nq/2, so its RMS value is 2^Nq/(2√2). A quantization error spread uniformly across one step has RMS value q/√12. The ratio is 2^N√12/(2√2), which is 2^N√1.5, and 20 log₁₀ of that is 6.0206N + 1.7609 dB.

Three conditions travel with the number, and dropping any of them invalidates it. The input is a sinusoid at full scale, so a signal backed off by 6 dB yields 6 dB less SNR without the converter being any worse. The quantization error is assumed uniformly distributed over one LSB and uncorrelated with the signal, an assumption that fails for very small or exactly periodic inputs, where the error collapses into discrete tones rather than a smooth noise floor; dither restores it. Finally, the noise is integrated over the entire Nyquist band, from DC to f_s/2.

That last condition is what makes the formula useful in practice. Total quantization noise power does not depend on the sampling rate, so spreading it across a wider Nyquist band leaves less of it inside a narrower signal band. Sampling at f_s and then filtering to a signal bandwidth B yields a processing gain:

SNR = 6.02N + 1.76 + 10 log₁₀(f_s / 2B) dB

Every factor of four in oversampling ratio buys about 6 dB, which is one bit. A delta-sigma modulator does considerably better than this, because noise shaping pushes quantization noise out of the signal band rather than merely diluting it.

Each additional bit of resolution therefore adds approximately 6 dB. A 16-bit converter theoretically achieves 98.1 dB SNR and a 24-bit converter 146.2 dB, but the second figure is arithmetic rather than engineering. No practical signal chain approaches it: thermal noise in the reference, the input buffer, and the converter's own front end arrives long before quantization noise becomes the limit, and datasheet dynamic range for 24-bit parts falls tens of decibels short of 146 dB.

Real converters achieve lower SNR due to:

• Thermal noise: From resistors, transistors, and other components in the signal path
• Quantization noise: The fundamental noise from amplitude discretization
• Reference noise: Noise on the voltage reference appears directly in the output
• Clock jitter: Timing uncertainty converts to amplitude uncertainty (discussed separately)
• Power supply noise: Coupling from supply rails into the analog signal path

Signal-to-Noise and Distortion Ratio (SINAD)

SINAD combines noise and distortion into a single figure of merit, measuring the ratio of signal power to the sum of all noise and distortion power:

SINAD = 10 log₁₀(P_signal / (P_noise + P_distortion)) dB

SINAD provides the most complete single-number characterization of converter dynamic performance because it captures all error sources that degrade signal quality. It directly relates to the effective number of bits (ENOB) specification.

SINAD is always less than or equal to SNR, with equality only when distortion is negligible. Because noise and distortion are uncorrelated, their power adds, so the noise-to-signal and distortion-to-signal ratios combine in root-sum-square fashion. In decibel form, SINAD relates to SNR and THD by:

SINAD = −10 log₁₀(10^−SNR/10 + 10^−|THD|/10) dB

The sign convention decides whether this expression works at all. SNR enters as a positive number of decibels, and THD must enter as its positive magnitude, which is why the absolute-value bars appear. Datasheets almost always print THD as a negative dB figure such as −85 dB, and substituting that value unchanged makes the second exponent positive, inflates the term by many orders of magnitude, and returns nonsense. Read each exponential as a ratio of error power to signal power, a quantity smaller than one. When SNR and |THD| are comparable, SINAD falls roughly 3 dB below either one; otherwise the larger error source dominates and SINAD tracks it closely.

Total Harmonic Distortion (THD)

Total harmonic distortion compares the harmonic content of the output against the fundamental. It is the root-sum-of-squares of the harmonic amplitudes divided by the amplitude of the fundamental:

THD = √(V₂² + V₃² + V₄² + …) / V₁

where V₁ is the fundamental amplitude and V₂, V₃, and so on are the harmonic amplitudes. How many harmonics enter the sum is a choice that must be stated, because the answer depends on it. IEEE Std 1241 takes the second through the tenth harmonics inclusive unless another set is specified; audio practice frequently stops at the fifth, and some datasheets report only the largest few.

Sampling introduces a complication that does not arise in purely analog distortion measurement. Harmonics above f_s/2 do not vanish; they alias back into the Nyquist band and appear at |nf_in − mf_s|, frequently nowhere near a multiple of the input frequency. A harmonic sum computed by inspecting only the bins at 2f_in, 3f_in, and so on therefore misses real distortion energy, and an unexpected spur in a converter spectrum is more often an aliased harmonic than an independent spurious tone. The standard definition of THD includes the aliases for this reason.

Because the expression above is a ratio of amplitudes rather than powers, converting it to decibels uses the factor of 20:

THD(dB) = 20 log₁₀(THD ratio)

Use 10 log₁₀ only when the quantity being converted is already a power ratio. The result is a negative dB figure, or equivalently a percentage: −60 dB corresponds to 0.1 percent, and −100 dB to 0.001 percent.

Sources of harmonic distortion in converters:

• INL errors: Nonlinearity in the transfer function generates harmonics of the input signal
• Comparator nonlinearity: Nonlinear behavior of internal comparators
• Capacitor nonlinearity: Voltage-dependent capacitance in switched-capacitor circuits
• Amplifier distortion: Nonlinearity in internal or external buffer amplifiers
• Reference nonlinearity: Load-dependent reference voltage variations

THD typically worsens at higher frequencies and larger signal amplitudes. Datasheets often specify THD versus frequency curves to capture this behavior.

THD+N is a different measurement, and the two are easy to confuse. THD counts only the identified harmonic bins, whereas THD+N counts everything that remains once the fundamental is notched out: harmonics and broadband noise together. THD+N and SINAD are consequently the same quantity under opposite sign conventions, the first usually quoted as a negative dB number or a percentage and the second as a positive dB number. A converter can show excellent THD and poor THD+N when its noise floor dominates, which is common at small signal amplitudes, where the harmonics shrink with the signal but the noise does not.

Spurious-Free Dynamic Range (SFDR)

Spurious-free dynamic range measures the ratio of signal power to the largest spurious spectral component, whether that component is a harmonic, intermodulation product, or other spur:

SFDR = 10 log₁₀(P_signal / P_spur) dB

SFDR carries two different references, and confusing them is the most common way to misread the specification. Measured in dBc, the spur is compared against the carrier actually applied, so the number describes the converter at that input level. Measured in dBFS, the spur is compared against a full-scale sine wave instead. The two agree only when the input sits at full scale; otherwise the dBFS figure exceeds the dBc figure by the amount of backoff. A tone 10 dB below full scale whose worst spur lies 75 dB below it measures 75 dBc and 85 dBFS, so a datasheet that quotes the dBFS number without naming the input level has said very little. IEEE Std 1241 defines SFDR against the applied signal level, which is the dBc form.

SFDR is particularly important in communication and spectroscopy applications where any spurious signal might be mistaken for a real signal. Unlike THD, which sums multiple harmonics, SFDR reports the single worst offender.

SFDR can be limited by:

• Harmonic distortion: Often the second or third harmonic is the largest spur
• Intermodulation products: With multi-tone inputs, mixing products may exceed harmonics
• Clock feedthrough: Coupling of sampling clock harmonics into the output spectrum
• Digital feedthrough: Coupling from digital output switching
• Power supply spurs: Mixing between supply noise and signal

High-performance ADCs for software-defined radio and instrumentation require SFDR exceeding 80 or 90 dB to distinguish weak signals from conversion artifacts.

Noise Power Ratio (NPR)

Noise power ratio characterizes converter performance with wideband signals by using a notched-noise stimulus. The converter is driven with band-limited noise containing a narrow spectral notch, and NPR compares the noise power in the passband to the residual power that intermodulation and noise deposit at the bottom of the notch:

NPR = 10 log₁₀(S_out / S_in) dB

where S_out and S_in are the average power spectral densities outside and inside the notched band. Densities are the correct quantity, not total powers: the passband is far wider than the notch, so a ratio of total powers would largely report the bandwidth ratio rather than the converter's linearity. For the measurement to mean anything, the notch in the source must be at least 10 dB deeper than the NPR being measured, and narrow compared with the overall noise bandwidth.

A converter with good large-signal linearity leaves the notch nearly empty, giving a high NPR; nonlinearity and noise fill the notch and lower the figure. NPR represents performance with complex wideband signals better than single-tone testing does, because it captures intermodulation among many frequency components simultaneously. NPR peaks at an optimum loading level: too little input power buries the notch floor in the converter's own noise, while too much drives the converter into clipping, so NPR is always reported at a stated loading, usually as a curve of NPR against input level relative to full scale.

The multi-carrier counterpart is multi-tone power ratio (MTPR), which replaces the shaped noise with a comb of equally spaced tones, omits one of them, and measures how much power the converter's nonlinearity deposits into the empty slot. MTPR is the figure quoted for discrete multi-tone and OFDM systems, where the signal genuinely is a comb of carriers rather than noise.

ENOB Calculation

ENOB is calculated from SINAD using the inverse of the ideal converter SNR formula:

ENOB = (SINAD − 1.76) / 6.02 bits

For example, a converter with 72 dB SINAD has ENOB = (72 − 1.76) / 6.02 = 11.67 bits. Despite potentially being marketed as a 14-bit or 16-bit converter, its actual dynamic performance matches that of an ideal 11.67-bit device.

This form presumes that SINAD was measured with a full-scale sinusoid, because it inverts a formula derived on that assumption. Real test signals are backed off, often to about 1 dB below full scale, to keep the converter clear of clipping, and the backoff must be added back before the division. With an applied amplitude A against a full-scale amplitude A_FS:

ENOB = (SINAD − 1.76 + 20 log₁₀(A_FS / A)) / 6.02 bits

Omitting the correction understates the converter by roughly one bit for every 6 dB of backoff. A part characterized at 6 dB below full scale and reported without correction appears to have lost a whole effective bit that it never lost, which is why an ENOB figure cannot be interpreted without the amplitude and the frequency at which it was taken. IEEE Std 1241 builds the full-scale reference into its own definition of ENOB for exactly this reason.

ENOB provides an intuitive interpretation of dynamic performance. A 16-bit converter with 12-bit ENOB has four bits of resolution degraded by noise and distortion, delivering only 4096 distinguishable levels rather than the theoretical 65,536.

Factors Affecting ENOB

ENOB varies with operating conditions:

• Input frequency: ENOB typically decreases at higher input frequencies as distortion increases and jitter effects grow
• Sampling rate: Some converters show improved ENOB at lower sampling rates due to reduced settling-related errors
• Input amplitude: ENOB may peak below full scale where distortion is minimized
• Temperature: Thermal noise increases with temperature, reducing ENOB
• Clock quality: Jitter degrades ENOB, especially at high input frequencies

Datasheets typically specify ENOB at specific test conditions (input frequency, sampling rate, amplitude). Performance at other conditions may differ significantly, so testing under actual application conditions is important for critical applications.

ENOB vs. Resolution

The marketing resolution of a converter, for example "16-bit ADC," indicates the digital word width but says nothing about actual conversion accuracy. ENOB provides the reality check:

• High-speed converters: A 14-bit pipeline ADC at 100 MSPS might achieve 11.5 ENOB at Nyquist input frequency
• Precision converters: A 24-bit delta-sigma ADC at 10 SPS might achieve 20 ENOB or better
• Audio converters: Good 24-bit audio ADCs reach roughly 18 to 20 ENOB in the audio band; the larger dynamic-range numbers on audio datasheets are usually A-weighted and taken with a small signal, which is a different and more flattering test than SINAD at full scale
• High-frequency limits: ENOB often drops by several bits as input frequency approaches the Nyquist limit

When comparing converters, ENOB at the actual application conditions provides a more meaningful comparison than resolution alone.

Jitter-Induced Noise

A sinusoid V(t) = V_p sin(2πf_int) slews fastest at its zero crossing, where the slope is 2πf_inV_p. Sampling that instant slightly early or late turns the timing error into a voltage error, and the worst case is:

V_error = 2π f_in V_p t_j

where f_in is the input frequency, V_p is the peak amplitude of the sinusoid, and t_j is the RMS jitter, which IEEE Std 1241 defines as the standard deviation of the aperture delay. The expression gives the maximum error, not the average: over a full cycle the slew rate is lower, and the RMS error works out to 1/√2 of the value above. Keeping the distinction between RMS and peak jitter straight matters, because the two differ by a large factor. Peak-to-peak jitter for a Gaussian process has no fixed value at all and is quoted only against a stated probability, commonly around 14 times the RMS value at a bit error rate of 10⁻¹², so substituting a peak-to-peak number into an RMS formula can overstate the degradation by an order of magnitude.

Carrying the averaging through gives a useful cancellation. The RMS error is 2πf_inV_pt_j/√2 and the RMS signal is V_p/√2, so both the factor of √2 and the amplitude drop out, leaving a jitter-limited SNR that depends only on frequency and jitter:

SNR_jitter = −20 log₁₀(2π f_in t_j)

For example, with 1 ps RMS jitter and a 100 MHz input, 2π × 10⁸ × 10⁻¹² equals 6.28 × 10⁻⁴, and −20 log₁₀ of that is 64 dB. This is a ceiling no amount of converter resolution can lift: a 16-bit part whose quantization noise alone would permit 98 dB still delivers 64 dB under that clock, equivalent to about 10.3 effective bits. Because the ceiling falls 6 dB for every doubling of input frequency, jitter overtakes quantization noise as the limiting impairment somewhere in the tens of megahertz for high-resolution parts.

Jitter Sources

Total jitter in a sampling system comes from multiple sources:

• Converter aperture jitter: Internal timing uncertainty in the sample-and-hold circuit, typically specified in datasheets
• Clock source phase noise: Random phase fluctuations in the sampling clock oscillator
• Clock distribution jitter: Added jitter from clock buffers, transmission lines, and noise coupling in the clock path
• Power supply noise: Supply variations that modulate internal delay paths

For high-frequency applications, external clock quality often dominates over internal aperture jitter. A low-jitter clock source with clean distribution becomes essential. Oscillator vendors specify phase noise rather than jitter, and the two connect by integration: the RMS phase deviation in radians is the square root of twice the single-sideband phase noise integrated across the band of interest, and dividing that by the angular carrier frequency gives RMS jitter in seconds. The integration limits are part of the specification, because a clock that looks quiet close to the carrier can still carry substantial broadband noise far out, and it is that far-out noise which a bandpass filter in the clock path removes.

Clock Requirements

To prevent jitter from limiting ENOB, the total jitter must satisfy:

t_j < 1 / (2π f_in × 10^6.02N/20)

where N is the desired ENOB. The criterion targets a jitter-limited SNR of 6.02N dB, asking jitter alone to be no worse than the quantization floor of an N-bit converter; demanding the full 6.02N + 1.76 dB tightens the budget by about a further 20 percent. For a 14-bit target at 100 MHz, 6.02N is 84.3 dB, so 10^84.3/20 is about 1.64 × 10⁴, and the requirement becomes:

t_j < 97 femtoseconds

The real budget is tighter still, because the converter's own aperture jitter, the oscillator, and every buffer in the clock path add in root-sum-square fashion, and it is the total that must meet the figure above. This explains why high-speed, high-resolution conversion demands exceptional clock quality. Strategies to meet these requirements include:

• Low-noise crystal oscillators: Fundamental mode crystals in optimized oscillator circuits
• Dedicated clock generators: Specialized ICs designed for low jitter
• Short clock paths: Minimize jitter-adding elements between clock source and converter
• Filtered clock: Bandpass filtering near the clock frequency removes broadband noise
• Isolated clock power: Separate, low-noise power supply for clock circuitry

Two-Tone Testing

The standard two-tone test applies two equal-amplitude sinusoids at closely spaced frequencies f1 and f2. Each tone is set slightly more than 6 dB below full scale so that the two tones do not drive the converter into clipping when they add in phase, which would otherwise produce gross distortion unrelated to small-signal linearity. Nonlinearity generates intermodulation products at frequencies:

• Second-order intermodulation products: f1 + f2 and f2 - f1 (the second harmonics 2f1 and 2f2 also arise from second-order nonlinearity but are harmonic, not intermodulation, products)
• Third-order intermodulation products: 2f1 - f2, 2f2 - f1, 2f1 + f2, and 2f2 + f1
• Higher-order products: nf1 +/- mf2 for various integers n and m

The second-order products and the higher third-order sum terms fall far from the input tones and are readily removed by filtering. The third-order difference products at 2f1 - f2 and 2f2 - f1, however, fall immediately adjacent to the original tones, making them effectively impossible to filter and therefore the dominant concern in receiver design.

Third-Order Intercept Point

The third-order intercept point (IP3 or TOI) characterizes third-order intermodulation strength. It is the extrapolated level at which the third-order products would equal the fundamental, a level never actually reached because the converter saturates first. The extrapolation can be referred to either port, giving an input-referred IIP3 or an output-referred OIP3. The two differ by the stage gain, and quoting one while meaning the other is the classic error: every variable in an intercept-point expression must be referred to the same side.

Higher IP3 indicates better linearity and lower intermodulation. Third-order products rise 3 dB for every 1 dB rise in the fundamental, so, writing everything output-referred, the absolute power of a third-order product is:

P_IM3 = 3P_out − 2 × OIP3

which rearranges to the suppression of the products below the tones, the quantity actually read off a spectrum analyzer:

IMD3 = P_out − P_IM3 = 2(OIP3 − P_out) = 2(IIP3 − P_in)

The two right-hand forms are equal because gain shifts OIP3 and P_out by the same amount, so the suppression in dBc is independent of gain and may be computed on whichever side the data are quoted. The practical consequence is that the products drop 2 dB further below the tones for every 1 dB of backoff, and climb 2 dB closer for every 1 dB of additional drive.

Applied to converters, the intercept point deserves a caution. It is an RF concept that presumes a smooth cubic nonlinearity, and a converter does not behave that way. Near full scale its distortion is dominated by clipping and by code-dependent errors that break the 3 dB per dB law outright, while at small amplitudes it is dominated by DNL, which produces distortion that does not scale with amplitude in any simple fashion. IEEE Std 1241 accordingly defines the intermodulation products themselves and not an intercept point, and converter datasheets mostly quote IMD3 in dBc or dBFS at a stated two-tone level. An IP3 figure extrapolated from a single measurement should be treated as indicative rather than predictive.

IMD in Communication Systems

Intermodulation distortion is critical in communication receivers where signals at different frequencies must be processed simultaneously without creating interfering products. Key considerations include:

• Adjacent channel interference: IMD products falling in adjacent communication channels
• Desense: Strong signals generating IMD products that mask weak desired signals
• Spurious response: IMD products appearing as false signals
• Dynamic range: The range between the weakest detectable signal and the strongest signal that can be processed without excessive IMD

Software-defined radio applications require converters with high IP3 to handle the diverse signal environment without generating spurious responses.

Power Supply Rejection Ratio

Power supply rejection ratio (PSRR) quantifies the converter's immunity to supply variations:

PSRR = 20 log₁₀(ΔV_DD / ΔV_out) dB

Here ΔV_DD is the supply perturbation and ΔV_out is the resulting shift referred to the converter's signal path, so the factor of 20 is the right one for a ratio of voltages. Converter datasheets often express the same property in other units: as an offset shift in LSBs per volt of supply change for the DC case, or, for the AC case, as the level in dBc of the spur that appears in the output spectrum when a sinusoid of known amplitude is deliberately injected onto the supply rail. Compare parts only across the same definition.

Higher PSRR values indicate better rejection of supply variations. PSRR typically varies with frequency, often degrading at higher frequencies where internal bypass capacitors become less effective.

Different supply pins may have different PSRR values:

• Analog supply: Directly affects the analog signal path; high PSRR critical
• Digital supply: Primarily affects digital logic; noise couples through substrate and ground
• Reference supply: Often the most sensitive; reference noise appears directly in output
• I/O supply: Affects digital output drivers; can couple back to analog circuitry

Supply Noise Effects

Power supply noise affects converter performance through several mechanisms:

• Reference modulation: Supply noise on reference circuits directly modulates conversion gain
• Comparator threshold modulation: Supply variations shift comparator switching points
• Timing modulation: Supply-dependent delays cause jitter
• Substrate coupling: Noise injected through the substrate affects sensitive analog nodes
• Ground bounce: Current transients cause local ground potential variations

The frequency relationship between supply noise and signal frequency determines whether the corruption appears as gain modulation, added noise, or spurious tones. Low-frequency supply variations modulate the gain, while supply noise near the signal frequency creates sidebands.

Decoupling Strategies

Effective power supply decoupling is essential for achieving datasheet performance:

• Multiple capacitor values: Use parallel capacitors covering different frequency ranges (10 microfarads, 100 nanofarads, 10 nanofarads)
• Close placement: Place decoupling capacitors as close as possible to power pins
• Low-ESR capacitors: Ceramic capacitors provide low impedance at high frequencies
• Ferrite beads: Isolate noisy digital supplies from sensitive analog supplies
• Separate regulators: Use dedicated low-noise regulators for analog and reference supplies
• Ground plane design: Solid ground planes with strategic split to separate analog and digital currents

Offset and Gain Drift

Offset and gain drift are typically specified in ppm per degree Celsius or LSB per degree Celsius:

• Offset drift: Caused by temperature coefficients of amplifier offset voltages, mismatched resistor temperature coefficients, and thermoelectric effects
• Gain drift: Primarily determined by reference voltage temperature coefficient and resistor ratio temperature tracking

For a 16-bit converter with a 2 V span (30.5 microvolts/LSB) and 1 ppm per degree Celsius of gain drift, the gain changes by 2 microvolts or about 0.066 LSB per degree Celsius. Over a 50-degree temperature range, this accumulates to 3.3 LSB of gain error.

Precision applications require:

• Low-drift voltage references: References with temperature coefficients below 5 ppm per degree Celsius
• Matched resistor networks: Thin-film networks with tracking temperature coefficients
• Temperature-stable amplifiers: Chopper or auto-zero amplifiers to eliminate offset drift
• Temperature compensation: Active compensation using temperature sensors and calibration tables

Reference Voltage Drift

The voltage reference is often the dominant source of temperature-dependent gain error. Different reference types offer different temperature performance:

• Bandgap references: Basic parts exhibit temperature coefficients of roughly 25 to 100 ppm per degree Celsius; precision, curvature-corrected types reach below 10 ppm per degree Celsius, with the best near 2 to 3 ppm per degree Celsius
• Buried zener references: Excellent stability, commonly 1 to 2 ppm per degree Celsius and lower still in oven-stabilized parts, but they require a higher supply voltage (typically above 6 V) and draw more power
• XFET references: Reach roughly 3 ppm per degree Celsius; their distinction is less absolute drift than an exceptionally flat, linear temperature characteristic and low noise, which eases calibration

External reference temperature coefficient directly multiplies the converter's effective gain drift, so reference selection is critical for temperature-sensitive applications.

Dynamic Parameter Drift

Dynamic specifications also vary with temperature:

• Noise: Thermal noise increases as the square root of absolute temperature; a 20% temperature increase raises noise by about 10%
• Bandwidth: Amplifier bandwidth and slew rate typically decrease at temperature extremes
• INL and DNL: Internal component matching degrades with temperature, often worsening linearity
• THD: Distortion may increase at temperature extremes due to amplifier and comparator degradation

Datasheet specifications are usually given at 25 degrees Celsius; performance at temperature extremes may be significantly worse. Critical applications require characterization over the full operating temperature range.

Histogram Testing

Histogram testing, also called code-density testing, measures DNL and INL by applying a known input signal and counting how many times each output code occurs. The count in a bin is proportional to the bin's width multiplied by the time the stimulus spends at that voltage, so the stimulus sets the normalization. Choosing the wrong normalization is the standard trap in converter testing.

A linear ramp covering the full input range has a uniform amplitude density: it spends equal time at every voltage. An ideal converter therefore returns a flat histogram, each code count is proportional to that code's width alone, and DNL falls straight out of the counts:

DNL(k) = Count(k) / Average count − 1

A sine wave does not behave this way. A sinusoid lingers near its peaks and races through its zero crossing, so its amplitude density is the arcsine, or bathtub, distribution, weighted heavily toward the extremes. An ideal converter driven by a sine wave returns a deeply U-shaped histogram, and dividing those counts by a flat average would report enormous false DNL at both ends of the range. The counts must be normalized against the ideal arcsine counts instead. For a sinusoid of amplitude A about an offset C, the fraction of samples expected in the bin for code k is the arcsine of (V(k + 1) − C)/A minus the arcsine of (V(k) − C)/A, divided by π. Equivalently, and this is the form IEEE Std 1241 adopts, the transition levels are recovered directly from the cumulative histogram:

V(k) = C − A cos(π H_c(k − 1) / S)

where H_c(k − 1) is the running total of samples in all bins below code k and S is the total number of samples. DNL and INL then follow from the recovered transition levels in the usual way. This route has a convenient property: errors in the assumed A and C appear only as gain and offset errors in the recovered transition levels, and gain and offset cancel out of DNL and of corrected INL, so the sine amplitude does not have to be known precisely.

Either stimulus must slightly overdrive the converter so that the end bins fill, and the source must be more linear than the device under test, because source distortion is indistinguishable from converter nonlinearity. The sine method additionally requires an integer number of cycles in the record, with the cycle count and the sample count relatively prime, so that samples distribute uniformly in phase. The ramp method is the more efficient measure of static behavior; the sine method is preferred when the converter must be characterized at speed.

Histogram test advantages:

• Speed: Tests all codes simultaneously rather than sequentially
• Statistical accuracy: Averaging over many samples reduces measurement uncertainty
• Choice of stimulus: Works with a linear ramp for static characterization or a sine wave for testing at speed, each with its own normalization
• Self-calibrating: Uses the converter's own output to determine code statistics

The number of samples required depends on the DNL resolution sought. Because the statistical uncertainty in each code's measured width falls only as the inverse square root of its sample count, production go/no-go screening may use tens of samples per code, whereas fine-grained characterization requires hundreds to thousands per code.

FFT-Based Testing

Fast Fourier transform analysis efficiently extracts multiple dynamic specifications from a single test waveform. A sinusoidal input is digitized, and FFT analysis reveals the signal, noise floor, harmonics, and spurious components.

From a single coherent FFT acquisition, the following specifications can be calculated:

• SNR: Signal power divided by total noise power (excluding harmonics)
• THD: Harmonic power divided by signal power
• SINAD: Signal power divided by noise plus distortion power
• SFDR: Signal power divided by largest spur power
• ENOB: Calculated from SINAD

Coherent sampling (integer number of input cycles in the acquisition window) eliminates spectral leakage that would corrupt measurements. This requires precise frequency relationships between the sampling clock and signal generator.

Reduced Test Coverage

Full specification testing at every code and condition would require impractical test times. Production testing typically uses reduced coverage strategies:

• Correlation: Test a subset of parameters that correlate with others; passing the subset implies passing the full set
• Major code testing: Test only at major code transitions (powers of two) where errors typically peak
• Spot frequency testing: Test dynamic specifications at a few representative frequencies rather than full sweeps
• Room temperature testing: Test at 25 degrees Celsius only, using characterization data to guarantee temperature extremes
• Built-in self-test: Use on-chip circuitry to perform basic tests without external equipment

Automatic Test Equipment

Production testing requires specialized automatic test equipment (ATE) capable of generating precision signals and accurately measuring converter outputs:

• Source requirements: Low-distortion, low-noise signal generators with better linearity than the device under test
• Timing accuracy: Low-jitter clocks and precise phase control for coherent sampling
• Measurement accuracy: ADC testers need DACs better than the device under test, and vice versa
• Throughput: Parallel testing of multiple devices to reduce cost per device
• Temperature control: Capability to test at temperature extremes for characterization

ATE systems for high-resolution converter testing represent significant investments, and test methodology directly affects manufacturing cost. Optimizing the trade-off between test coverage and test time is an ongoing engineering challenge.

Specification Selection

Different applications prioritize different specifications:

• Precision measurement: INL, DNL, offset and gain accuracy, temperature drift
• Audio: THD, SNR, SINAD within the audio band (20 Hz to 20 kHz)
• Communication: SFDR, IMD, IP3, noise power ratio at the operating frequency
• High-speed data acquisition: ENOB vs. frequency, aperture jitter, input bandwidth
• Control systems: Monotonicity, settling time, latency

Testing vs. Datasheet Conditions

Datasheet specifications are measured under optimized conditions that may differ from application conditions:

• Input signal: Pure sinusoids vs. complex application signals
• Power supplies: Clean laboratory supplies vs. noisy system supplies
• Clock source: Low-jitter laboratory generators vs. system clocks
• Layout: Evaluation board vs. application PCB
• Temperature: 25 degrees Celsius against the actual operating temperature

Application testing under actual conditions often reveals performance gaps that require design improvements or specification derating.

Margin and Guard Bands

Robust system design includes margin for specification variation:

• Production variation: Datasheet specifications represent limits; typical values are usually better
• Temperature variation: Allow for drift over the operating temperature range
• Aging: Some specifications drift over time, particularly precision references
• Application conditions: Real systems rarely achieve evaluation board performance

A common approach allocates performance budget with margin, targeting application requirements that are comfortably better than minimum datasheet specifications.