Electronics Guide

Operating Principle

A SAR ADC operates by comparing the input signal against successively refined reference voltages generated by an internal digital-to-analog converter (DAC). The conversion process begins by sampling and holding the input voltage, then systematically testing each bit position from most significant to least significant:

1. The input is sampled and held constant during conversion
2. The MSB is set to 1, producing a DAC output of half the reference voltage
3. A comparator determines whether the input exceeds this value
4. If the input is higher, the bit remains set; otherwise, it is cleared
5. The process repeats for each subsequent bit with progressively smaller weights
6. After N comparisons for an N-bit converter, the digital output is complete

Because each bit costs one comparator decision, an N-bit conversion takes at least N internal clock cycles after the acquisition phase. In most CMOS SAR converters the DAC is a binary-weighted capacitor array that also samples the input, so one structure serves as both the sample-and-hold and the DAC.

Key Characteristics

SAR ADCs offer several distinctive advantages:

• Resolution Range: Typically 8 to 20 bits, with 16-bit converters common in precision applications
• Sample Rates: From a few kilosamples per second to tens of megasamples per second in the fastest single-channel parts; SAR cores also serve as the channel converters in many time-interleaved designs
• Power Efficiency: Among the best energy efficiency of any architecture, because the converter needs no continuously biased amplifier
• No Pipeline Delay: Each result is available at the end of its own conversion, with no latency from previous samples, which suits control loops and multiplexed channels
• Low Power Scaling: Because most of the power is dynamic, consumption scales nearly linearly with sample rate

Energy efficiency is usually compared with the Walden figure of merit, which divides power by the number of effective conversion steps delivered each second:

FoM_W = P / (2^ENOB × f_s)

A precision converter that delivers 14.5 effective bits at 1 MS/s while dissipating 5 mW scores 5 × 10⁻³ W / (23,170 × 10⁶ s⁻¹), about 216 femtojoules per conversion step. Research designs go much further: a 10-bit, 1 MS/s charge-redistribution SAR converter presented at ISSCC 2008 dissipated 1.9 microwatts and reported 4.4 femtojoules per step, which implies about 8.75 effective bits. SAR designs account for many of the most efficient converters in published surveys, while commercial parts, which also power references, input drivers, and interfaces, generally score far higher. The Walden figure also favors low-resolution designs: once thermal noise dominates, each additional bit costs about four times the power rather than two, so high-resolution converters are usually compared with the Schreier figure of merit instead.

Applications

SAR ADCs excel in applications requiring moderate speed with high precision:

• Data acquisition systems and multiplexed sensor interfaces
• Battery-powered portable instruments
• Industrial process control and monitoring
• Medical devices including patient monitors and diagnostic equipment
• Automotive sensor interfaces and control systems

Architecture

A flash ADC uses 2^N − 1 comparators for an N-bit converter, each with a unique threshold voltage set by a resistor ladder divider, so an 8-bit flash needs 255 comparators and a 10-bit flash 1,023. When the input is applied, all comparators simultaneously determine whether the input exceeds their respective thresholds. The resulting thermometer code is then encoded into a standard binary output:

• Resistor Ladder: Precision divider chain establishes reference thresholds spaced one LSB apart
• Comparator Array: Parallel comparators provide simultaneous decisions
• Encoder Logic: Converts thermometer code to binary, typically through a ROM or priority encoder preceded by logic that suppresses isolated "bubble" errors in the thermometer code
• Output Registers: Pipeline registers synchronize the digital output

Performance Considerations

Flash ADCs present distinct trade-offs:

• Speed Advantage: Single-step conversion enables sampling rates of several gigasamples per second
• Resolution Limitation: Comparator count roughly doubles with each additional bit, and power, area, and input capacitance grow with it, practically limiting resolution to about 6 to 8 bits
• Power Consumption: High static power from the resistor ladder and numerous comparators
• Input Capacitance: Large comparator array presents significant loading to the signal source
• Metastability: Comparator decisions near threshold can produce indeterminate outputs requiring careful handling

Applications

Flash ADCs serve applications demanding maximum speed:

• Digital oscilloscopes and high-speed data acquisition
• Radar and electronic warfare systems
• High-speed serial communication receivers
• Video digitization and display systems
• First stages of pipelined and folding architectures

Stage Operation

Each pipeline stage performs a complete conversion cycle:

1. Sample and Hold: Captures the incoming signal for processing
2. Flash Conversion: A low-resolution (typically 1.5 to 4 bit) flash ADC digitizes the signal
3. DAC Reconstruction: The digital result drives an internal DAC
4. Subtraction: The DAC output is subtracted from the held input
5. Amplification: The residue is amplified to span the full range for the next stage

The 1.5-bit stage is the classic choice. Two comparators set at plus and minus a quarter of the reference produce three decision levels, and the redundancy lets digital correction absorb comparator offsets as large as a quarter of the reference. Redundancy does not correct the interstage gain, however: the residue amplifier's gain, and the capacitor matching that sets it, must still be accurate to the resolution of the stages that follow, which is why high-resolution pipelines commonly calibrate interstage gain, often in the background.

Key Features

Pipeline ADCs offer a compelling combination of characteristics:

• High Throughput: All stages operate simultaneously on different samples, achieving high sustained sample rates
• Digital Correction: Redundant stage codes let digital logic correct sub-ADC comparator errors, while interstage gain errors need separate calibration
• Latency: Output data appears several clock cycles after input sampling, requiring consideration in feedback systems
• Linearity: Performance depends critically on amplifier and capacitor matching
• Power Efficiency: Moderate power consumption at high speeds compared to full parallel approaches

Applications

Pipeline ADCs dominate high-speed, high-resolution applications:

• Software-defined radio and cellular base stations
• Medical imaging systems including ultrasound and MRI
• Cable modem and broadband communication receivers
• Professional video and broadcast equipment
• Spectrum analyzers and test instrumentation

Operating Principles

A delta-sigma ADC consists of an analog modulator followed by a digital decimation filter:

• Oversampling: The input is sampled at many times the Nyquist rate, spreading quantization noise across a wider bandwidth
• Noise Shaping: A loop filter of one or more integrators inside the feedback loop shapes the quantization noise spectrum, moving most noise power to high frequencies
• Low-Resolution Quantizer: Often a simple 1-bit comparator provides the quantized output
• Digital Filter: A decimation filter removes out-of-band noise and reduces the data rate to the final output rate

Modulator Orders

The modulator order sets the slope of the noise-shaping transfer function. An L-th-order loop suppresses in-band quantization noise with a slope of 6L decibels per octave, and the in-band signal-to-noise ratio then improves with each doubling of the oversampling ratio by:

ΔSNR = (6L + 3) dB per doubling of the oversampling ratio

Six decibels per order come from the steeper shaping, and three from spreading the fixed quantization noise power over a band twice as wide. Setting L = 0, no shaping at all, leaves only the 3 dB, half a bit, per doubling of plain oversampling described below. The shaping also carries a fixed penalty that grows with order, about 12.9 dB at second order, so a higher order pays off only once the oversampling ratio is high enough. The common choices compare as follows:

• First-Order: A single integrator shapes noise at 6 dB per octave, yielding roughly 9 dB of SNR improvement per octave of oversampling; simple and unconditionally stable, but modest in performance
• Second-Order: Two integrators shape noise at 12 dB per octave (about 15 dB of SNR improvement per octave), striking a strong balance between stability and resolution
• Higher-Order: Additional integrators steepen the noise-shaping slope further, to about 21 dB of SNR improvement per octave at third order, but can become conditionally stable, requiring feedforward or feedback coefficient scaling to keep the loop well behaved
• MASH (Multi-Stage Noise Shaping): Cascaded lower-order loops combine the guaranteed stability of first- and second-order stages with the steep noise shaping of a high-order modulator, at the cost of sensitivity to interstage matching

Advantages

Delta-sigma converters offer unique benefits:

• High Resolution: Nominal output word lengths of 16 to 32 bits, achievable with practical component tolerances; the noise-limited effective resolution is several bits lower, and it falls as the output data rate rises and admits more noise
• Relaxed Anti-Aliasing: Oversampling moves the first band that can alias into the signal up to near the modulator sampling rate, so a simple low-order analog filter suffices; continuous-time modulators add inherent anti-aliasing through the loop filter itself
• Low Component Sensitivity: In switched-capacitor (discrete-time) modulators, performance depends on capacitor ratios rather than absolute values; continuous-time modulators depend on absolute RC or C/G_m time constants relative to the clock period and usually need tuning
• Digital Filtering: The decimation filter provides a sharp, linear-phase cutoff that would be impractical in analog form
• Excellent Linearity: A single-bit feedback DAC is inherently linear, because two output levels always define a straight line; multi-bit designs recover that linearity with dynamic element matching

The costs are latency through the decimation filter, a signal bandwidth limited to a small fraction of the modulator clock, and a settling time of several output periods after a step, which makes multiplexing many channels through one delta-sigma converter slower than through a SAR converter.

Applications

Delta-sigma ADCs excel where resolution trumps speed:

• Precision weigh scales and load cells
• Temperature and pressure measurement systems
• Audio recording and playback equipment
• Seismic and geophysical instrumentation
• Power metering and energy monitoring

Dual-Slope Conversion

The dual-slope technique operates in two phases:

1. Integration Phase: The unknown input voltage is integrated for a fixed time T₁, counted as N₁ clock periods, producing a ramp whose final value is proportional to the input
2. De-Integration Phase: A known reference voltage V_ref of opposite polarity is integrated until the output returns to zero; a counter measures the time required, T₂, as N₂ clock periods

The integrator output falls by exactly as much as it rose, so V_inT₁/RC = V_refT₂/RC, and because one clock counts both intervals, the result reduces to:

V_in = V_ref × N₂ / N₁

The integrator resistor and capacitor cancel, and so does the clock frequency; provided they hold steady through one conversion, only the reference and the two counts remain. With N₁ = 10,000 and V_ref = 1.000 V, a de-integration count of 4,321 reads 0.4321 V. Offsets in the integrator and comparator do not cancel, which is why practical converters add an auto-zero phase that measures and stores them before each conversion.

Integration also filters. Averaging over T₁ has a sin(πfT₁)/(πfT₁) response with a null at every multiple of 1/T₁, so choosing T₁ as a whole number of line cycles rejects power line interference. A 100 ms integration spans five cycles of 50 Hz and six of 60 Hz, nulling both; clocked at 100 kHz, it also supplies the 10,000 counts of the example above.

Multi-Slope Variants

Enhanced integrating architectures improve speed, resolution, and accuracy:

• Triple-Slope: Splits the de-integration into a fast phase at the full reference current and a slow phase at a much smaller current, resolving the final residue finely without a long count and so shortening conversion for a given resolution
• Quad-Slope: Adds integrate and de-integrate cycles on known inputs, such as zero, and uses their counts to correct the measurement digitally, cancelling integrator and comparator offsets and bias-current errors without a stored analog correction
• Multi-Slope Run-Up: Keeps the input connected throughout the run-up while switching positive and negative reference currents in and out to hold the integrator within its range, so resolution rises without a large integrator swing; high-end digital multimeters use this technique
• Multi-Slope Run-Down: Uses several successively smaller reference currents, each typically a power of ten below the last, so that four digits of residue resolve in roughly 40 clock periods rather than 10,000
• Charge-Balancing: Injects fixed packets of reference charge whenever the integrator crosses a threshold, so the packet count over a gate time measures the input; the structure is closely related to a first-order delta-sigma modulator

Applications

Integrating ADCs serve low-speed, high-precision requirements:

• Digital multimeters and bench instruments
• Panel meters and industrial displays
• Thermocouple and RTD temperature measurement
• Battery voltage monitoring
• Strain gauge and bridge sensor interfaces

Architecture Concept

A time-interleaved ADC employs M parallel converter channels, each sampling at f_s/M, where f_s is the aggregate rate, with successive channels staggered in time by 1/f_s:

• Clock Distribution: Precision clock generation creates M phases with exact spacing
• Channel Converters: Individual ADCs operate at reduced speed with relaxed requirements
• Digital Multiplexing: Outputs are combined in proper sequence to reconstruct the high-speed data stream
• Calibration System: Background or foreground calibration corrects channel mismatches

Mismatch Challenges

Channel mismatches create spurious tones that limit dynamic range:

• Offset Mismatch: Channel offset differences form a pattern that repeats every M samples, producing fixed tones at multiples of f_s/M regardless of the input
• Gain Mismatch: Gain differences amplitude-modulate the signal, creating image spurs at k f_s/M ± f_in for integer k
• Timing Skew: Sample-time errors convert to amplitude errors proportional to the signal's slew rate, producing images at the same frequencies as gain mismatch but growing with input frequency
• Bandwidth Mismatch: Different analog bandwidths cause frequency-dependent gain and phase errors

With four channels and f_s = 4 GS/s, for example, offset tones sit at 1 GHz and 2 GHz, and a 100 MHz input acquires gain and timing images at 900 MHz, 1.1 GHz, and 1.9 GHz. Modern designs employ digital calibration algorithms, often running in the background, to measure and correct these mismatches continuously.

Applications

Time-interleaved ADCs enable extreme-bandwidth digitization:

• Real-time oscilloscopes with bandwidths above 10 GHz
• Direct RF sampling receivers for radar and communications
• Particle physics detector readout
• High-speed serial link analysis
• 5G and advanced wireless infrastructure

Folding Principle

A folding circuit creates a periodic transfer function that maps the full input range onto a smaller output range:

• Coarse Conversion: A few comparators determine which fold the input occupies, providing the MSBs
• Folding Amplifiers: Analog preprocessing creates the folded waveform
• Fine Conversion: A small flash ADC resolves the position within the fold, providing LSBs
• Digital Reconstruction: Coarse and fine results are combined with proper zero-crossing detection

Interpolation Techniques

Interpolation further reduces comparator count by generating intermediate threshold crossings:

• Resistive Interpolation: Simple resistor dividers between comparator outputs create intermediate levels
• Active Interpolation: Amplifier-based interpolators provide better speed and accuracy
• Cascaded Folding-Interpolating: Multiple stages of folding and interpolation achieve high resolution efficiently

Applications

Folding and interpolating ADCs fill the gap between flash and pipeline converters:

• Video digitizers and digital video systems
• Disk drive read channels
• Wireless communication receivers
• High-definition television processing
• Medical ultrasound front ends

Theoretical Basis

Oversampling provides resolution enhancement through noise averaging:

• Noise Spreading: The fixed quantization noise power spreads across a Nyquist band that widens with the sampling rate
• Filtering Benefit: A digital low-pass filter removes noise above the signal bandwidth
• Resolution Gain: Each quadrupling of the oversampling ratio yields approximately one additional bit of resolution
• Anti-Aliasing Relaxation: Higher sample rates allow simpler analog anti-aliasing filters

The resolution gain follows from the quantization limit. For an ideal N-bit quantizer driven by a full-scale sine wave, with its error spread uniformly from DC to half the sampling rate, quantization alone limits the signal-to-noise ratio to:

SNR = 6.02N + 1.76 dB

The total quantization noise power does not depend on the sampling rate, so sampling at f_s and filtering digitally to a signal bandwidth B keeps only the fraction 2B/f_s of it:

SNR = 6.02N + 1.76 + 10 log₁₀(f_s / 2B) dB

The ratio f_s/2B is the oversampling ratio. Each doubling adds 3 dB, the L = 0 case of the noise-shaping relation above, and each quadrupling adds 6.02 dB, or one bit. An ideal 12-bit converter, at 74.0 dB, therefore needs an oversampling ratio of 256 to reach the 98.1 dB of an ideal 16-bit converter, a slow return that noise shaping improves on greatly.

Implementation Considerations

Practical oversampling systems must address several factors:

• Decimation Filter Design: Digital filters must provide adequate stopband rejection while meeting latency requirements
• Power Trade-offs: Higher sample rates increase analog power consumption
• Signal Bandwidth: The technique works best for bandwidth-limited signals
• Noise as a Prerequisite: Averaging gains resolution only if the quantization error changes from sample to sample, so the input must carry noise or dither comparable to one LSB or larger; a noiseless DC input averages to the code it started with
• Noise Floor Requirements: The analog noise that remains inside the final bandwidth still sets the floor, so it must be low enough to realize the resolution benefit

Dithering Mechanisms

A dither is either subtracted after conversion or left in the output, and its amplitude distribution decides what it achieves. Writing q for one LSB, undithered quantization noise has a power of q²/12:

• Subtractive Dither: A known pseudo-random dither is added before conversion and subtracted digitally afterward. With a uniform dither one LSB wide, the remaining error is uniform, independent of the signal, and of the same q²/12 power as undithered quantization noise; the cost is generating a dither that can be subtracted exactly
• Non-Subtractive Dither: The dither stays in the output, so its own power adds to the noise floor in exchange for linearity
• Rectangular PDF (RPDF) Dither: A uniform dither one LSB peak-to-peak makes the mean of the error independent of the signal, which removes distortion, but the error power still varies with the signal between zero and q²/4, an effect heard in audio as noise modulation. The average error power doubles to q²/6, a 3 dB penalty, and widening a rectangular dither does not remove the modulation entirely
• Triangular PDF (TPDF) Dither: The sum of two independent RPDF sources, two LSB peak-to-peak, makes both the mean and the power of the error independent of the signal. It is the lowest-power non-subtractive dither that does so, and the total error power triples to a constant q²/4, a 4.8 dB penalty

Benefits

Dithering provides several advantages:

• Spurious Tone Elimination: Converts discrete spurious tones into broadband noise floor
• Improved Small-Signal Linearity: Enables detection of signals smaller than one LSB through averaging
• DNL Improvement: A larger dither spanning many codes, often placed outside the signal band so that filtering removes it, spreads each wide, narrow, or missing code over many input levels, so the averaged transfer function is smoother than any single step
• Spectral Purity: Critical for spectral analysis where spurious tones could be mistaken for signals

Applications

Dithering proves essential in demanding measurement scenarios:

• Audio mastering and professional recording
• Spectrum analyzers and signal analyzers
• Radar signal processing
• Scientific instrumentation
• Telecommunications test equipment