Advanced Packaging and Integration
Advanced packaging and integration replace the single monolithic die with a modular assembly of several specialized dies joined inside one package. As transistor scaling slows and the cost of each new process node rises, packaging has become the principal lever for improving system performance, and the interconnect between dies now carries much of the burden that on-chip wiring once carried alone.
The approach lets architects fabricate each functional block on the process best suited to it, then combine those blocks: high-performance logic on a leading-edge node, input/output and analog circuits on a mature and cheaper node, dense memory on a DRAM process, and photonics or microelectromechanical system (MEMS) sensors on their own specialized processes. Disaggregating a design this way improves silicon yield, shortens development schedules through die reuse, and allows product variants to be assembled from a common inventory of dies. It also introduces costs of its own, in interface area, link power, assembly steps, and test complexity, so the trade-off must be evaluated product by product.
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Why Packaging Became the Scaling Lever
Semiconductor packaging began as protection and connection: a die sealed in plastic or ceramic, wire-bonded to a lead frame, and soldered to a board. Modern advanced packages are active participants in system performance. They distribute hundreds of amperes of current at sub-volt supply rails, carry multi-terabit-per-second die-to-die traffic, conduct kilowatts of heat, and increasingly define the boundary of what counts as a "chip."
Three pressures drove the change. First, the economics of transistor scaling deteriorated: mask sets and design costs at leading-edge nodes rose steeply, and analog, input/output, and SRAM circuits stopped shrinking at the rate of logic, so migrating an entire design to the newest node wastes money on blocks that gain nothing. Second, photolithography imposes a hard ceiling on die size. A standard reticle field measures roughly 26 by 33 millimeters, capping a single die at about 858 square millimeters, and yield falls sharply as die area approaches that limit. Third, data-intensive workloads in artificial intelligence, graphics, and networking demand memory bandwidth that no board-level interface can supply.
Advanced packaging answers all three. Splitting a design into chiplets lets each block use the process node that suits it, keeps individual die areas small enough to yield well, and lifts the effective silicon budget far above the reticle limit by placing several dies on a common carrier. The bandwidth follows from proximity: interconnect a few millimeters long inside a package needs far less drive energy than a centimeters-long trace on a printed circuit board.
Integration Architectures
Advanced packaging is usually described by how dies are arranged relative to one another and to their carrier.
2D and 2.1D assemblies place dies side by side on an organic substrate. Multi-chip modules of this kind are decades old, but modern build-up and embedded-trace substrates support far finer routing than earlier generations, making side-by-side integration viable for moderate-bandwidth links.
2.5D integration inserts a high-density routing layer between the dies and the substrate. A silicon interposer, patterned with back-end-of-line metal at wafer fabrication resolution, carries thousands of parallel traces between neighboring dies; TSMC's chip-on-wafer-on-substrate (CoWoS) family is the best-known implementation. A lower-cost variant embeds small silicon bridges only where dense connections are needed, leaving the rest of the routing to the organic substrate. Intel's embedded multi-die interconnect bridge (EMIB) uses this approach. Fan-out wafer-level packaging offers a third path, reconstituting dies in molding compound and building redistribution layers directly over them without any interposer; TSMC's integrated fan-out (InFO) technology has shipped in mobile application processors since 2016.
3D integration stacks dies vertically. Through-silicon vias, copper conductors a few micrometers across etched through a wafer thinned to tens of micrometers, carry signals and power from one tier to the next. High-bandwidth memory is the canonical example: DRAM dies stacked eight to sixteen high over a base logic die. Logic-on-logic stacking is now in volume production as well, most visibly in cache dies bonded face-to-face onto processor compute dies and in accelerator designs that stack compute tiles on an active base die containing cache and fabric.
Monolithic and sequential 3D represent the frontier, fabricating successive device tiers on the same wafer rather than bonding finished dies. This eliminates bonding interfaces entirely, but the thermal budget of the upper tiers must not damage the transistors and interconnect beneath them, which remains a difficult process constraint.
Key Technology Enablers
Interconnect pitch sets the ceiling on die-to-die bandwidth, and it is the metric along which the field has advanced fastest. Solder micro-bumps in volume production span roughly 40 micrometers down to about 10 micrometers of pitch. Hybrid bonding removes the solder altogether, joining dielectric to dielectric and copper pad to copper pad in a direct, permanent bond; production implementations operate near 9 micrometers of pitch, and research has demonstrated sub-micrometer pitches. Reducing pitch by a factor of ten raises the achievable connection density by roughly a factor of one hundred, which is why hybrid bonding underpins the highest-bandwidth stacked products.
Carrier size matters as much as pitch. Silicon interposers now span several reticle fields stitched together, and the industry roadmap has pushed steadily upward: TSMC's CoWoS line has progressed from interposers of roughly three reticle fields to about five and a half, with larger formats in qualification. Larger interposers permit more high-bandwidth memory stacks alongside each compute die, but they aggravate warpage and handling problems and consume scarce packaging capacity.
Memory standards evolve in lockstep with the packaging that carries them. JEDEC published the HBM4 standard, JESD270-4, in April 2025. It doubles the interface width from 1,024 to 2,048 bits, doubles the channel count from sixteen to thirty-two per stack with two pseudo-channels each, and supports transfer rates that yield up to roughly two terabytes per second per stack. Notably, HBM4 remains attainable with micro-bump assembly, which deferred the industry-wide transition to hybrid bonding in memory to a later generation.
Beneath the dies, substrate technology is advancing along its own track. Organic build-up substrates dominate today, but their coefficient of thermal expansion and dimensional stability limit both package size and line width. Glass cores offer better flatness, tighter via pitch, and thermal expansion closer to silicon; Intel disclosed a glass-core substrate program in 2023 and has since demonstrated glass cores combined with EMIB bridges, with data-center packages expected to lead adoption. Panel-level processing, which handles large rectangular panels instead of round wafers, promises better area utilization and lower cost per package for the same reason that flat-panel display manufacturing outgrew wafer formats.
Standards and the Chiplet Ecosystem
A modular die is useful only if it can talk to dies from other suppliers. Universal Chiplet Interconnect Express (UCIe) has become the leading open die-to-die standard, defining a physical layer, a die-to-die adapter, and protocol mappings for PCI Express and Compute Express Link, together with a raw mode for custom traffic. The specification has advanced quickly: UCIe 3.0, released in August 2025, raised the maximum signaling rate to 48 and 64 gigatransfers per second for standard-package and advanced-package configurations, doubling the 32 gigatransfers per second of the prior generation, and added runtime transmitter recalibration, improved idle-state power management, and manageability features for complex systems in package. The Open Compute Project's Bunch of Wires specification serves a complementary role as a simpler, lower-overhead parallel interface.
Test discipline is the other precondition for a chiplet market. Because a multi-die package is scrapped or reworked at the cost of every die it contains, each die must be qualified as a known good die before assembly, and the assembled stack must remain testable afterward. IEEE 1838 defines a test access architecture for three-dimensional stacked integrated circuits, extending familiar boundary-scan concepts across die boundaries. Design-for-test structures, on-die instrumentation, and repair mechanisms such as spare through-silicon vias all serve to protect assembly yield.
Commercial practice still lags the standards. Most shipping chiplet products combine dies designed by a single company for a single package, because interoperability requires agreement not only on the electrical interface but on thermal envelopes, mechanical stack-up, test hooks, bump maps, and liability when an assembled package fails. An open marketplace in third-party chiplets remains an aspiration rather than an established business model.
Design Challenges and Trade-Offs
Thermal management is the dominant constraint. Stacking dies places heat sources on top of one another and buries the hottest tier farthest from the heat sink, while high-performance accelerator packages now dissipate well beyond one kilowatt. Mitigations include placing cache or memory rather than high-power logic on upper tiers, thinning dies to shorten the conduction path, using thermally conductive underfills and lids, and adopting direct liquid cooling. Thermal design and floorplanning can no longer be separated.
Power delivery is a parallel problem. Supplying hundreds of amperes at under a volt through a package demands very low impedance from the voltage regulator to the die, which motivates integrated voltage regulators, deep trench capacitors within the interposer, and backside power delivery networks that route supply rails on the reverse side of the wafer.
Mechanical stress arises from materials that expand at different rates. Silicon expands at roughly 3 parts per million per kelvin, while organic substrates expand several times faster. Across reflow and thermal cycling, that mismatch warps large packages and stresses micro-bumps and low-dielectric-constant layers. Underfills, stiffeners, and careful selection of substrate materials manage the effect, and glass cores are attractive partly because they narrow the mismatch.
Finally, the economics cut both ways. Disaggregation improves silicon yield and enables node-optimized blocks, but it adds interface area, die-to-die link power, assembly steps, and test insertions. Each interface consumes perimeter and beachfront area that a monolithic design would not need. Whether chiplets are cheaper than a single die depends on die size, node cost, volume, and product-line reuse, and the answer is not the same for a mobile processor as for a data-center accelerator.
Industry Impact and Future Directions
Advanced packaging has become a competitive differentiator in its own right. Foundry packaging capacity is now a gating factor in the supply of artificial intelligence accelerators, and outsourced assembly and test providers, foundries, and substrate makers all compete for a role that was once treated as commodity back-end work. Companies that command these technologies gain sourcing flexibility, faster time to market through die reuse, and the ability to derive product variants without a full custom design.
Co-packaged optics illustrates where the field is heading. Moving the optical engine from a pluggable faceplate module onto the switch package shortens the electrical path from tens of centimeters to a few, cutting interconnect energy per bit by roughly a factor of three and, by vendor accounts, reducing optical interconnect power substantially at the system level. Switch platforms combining multi-terabit ASICs with co-packaged optical engines have moved into production, though fiber attach, laser reliability, serviceability, and optical-engine yield remain the practical obstacles to broad deployment.
Other trajectories are equally consequential: hybrid bonding at ever finer pitch, panel-level and glass-core substrates, deeper integration of power delivery into the package, and the extension of these methods to domains such as cryogenic control electronics for quantum processors and sensor fusion at the edge. What unites them is a shift in the unit of design. The package, not the die, is becoming the system boundary, and packaging choices increasingly determine what a product can achieve.