Electronics Guide

Laminate Materials and Construction

Organic substrates are constructed from layers of copper foil laminated with organic dielectric materials, primarily epoxy-based resins reinforced with glass fibers or other strengthening materials. The most common materials include FR-4 for standard applications, BT (bismaleimide triazine) resin for enhanced thermal and electrical performance, and ABF (Ajinomoto Build-up Film) for high-density build-up layers.

The lamination process involves stacking multiple layers of prepreg (pre-impregnated fiber sheets) with patterned copper foils, then applying heat and pressure to cure the resin and bond the layers. Through-holes and microvias connect layers, creating three-dimensional routing networks. Mechanical drilling of through-holes and laser drilling of microvias enable increasingly fine interconnect features.

Electrical Considerations

Organic dielectrics exhibit frequency-dependent properties that become increasingly important at higher operating speeds. The dielectric constant (Dk) and dissipation factor (Df) determine signal propagation velocity and losses. Low-loss materials with Df values below 0.005 are essential for high-frequency applications such as 5G communications and high-speed data centers. Material selection must also consider dielectric constant stability across temperature and frequency ranges.

Signal integrity in organic substrates requires careful attention to impedance control, achieved through precise management of trace width, dielectric thickness, and copper weight. Differential pair routing, ground plane design, and via stub management minimize crosstalk and reflections in high-speed designs.

Conductor surface roughness contributes an additional loss term that grows with frequency, because current crowds into a skin depth that becomes comparable to the profile of the copper. Substrate makers therefore specify low-profile and very-low-profile copper foils, and bond dielectric to copper using alternative adhesion chemistries rather than the heavy oxide roughening once used for laminates.

Surface Finishes

Exposed copper pads require a surface finish that preserves solderability or wire-bondability through storage and assembly. Organic solderability preservative (OSP) is the lowest-cost option and adds negligible thickness, but it offers limited protection through multiple reflow cycles. Electroless nickel immersion gold (ENIG) provides a flat, durable, wire-bondable surface, at the cost of a nickel layer whose resistivity and magnetic behavior degrade high-frequency conductor loss.

Electroless nickel electroless palladium immersion gold (ENEPIG) adds a palladium barrier that supports both gold wire bonding and soldering, making it a common choice for mixed-assembly packages. Immersion silver and immersion tin serve as nickel-free alternatives where high-frequency loss matters. Finish selection interacts directly with assembly: the intermetallic compounds formed at the solder joint, and therefore joint reliability, differ from one finish to the next.

Thermal and Mechanical Properties

The coefficient of thermal expansion (CTE) mismatch between organic substrates (typically 15 to 18 parts per million per degree Celsius) and silicon die (approximately 3 parts per million per degree Celsius) creates stress during thermal cycling. This mismatch drives the need for careful design of underfill materials and bump structures in flip-chip packages to ensure long-term reliability.

Glass transition temperature (Tg) defines the upper operating limit where the polymer transitions from rigid to rubbery behavior. High-Tg materials exceeding 180 degrees Celsius are required for lead-free soldering processes and demanding thermal environments. Moisture absorption can reduce Tg and cause delamination, making moisture management critical during manufacturing and storage.

Material Advantages

Glass provides exceptional dimensional stability with near-zero moisture absorption and low thermal expansion coefficients that can be tailored to match silicon. This stability enables tighter tolerances in high-density interconnects and reduces the warpage that complicates large organic substrates. The smooth surface finish achievable with glass supports finer lithographic patterning than the rough surfaces of woven glass reinforcement in organic laminates.

The electrical properties of glass are excellent for high-frequency applications, with low and stable dielectric constants and very low loss tangents. The absence of woven reinforcement eliminates the fiber weave effect that causes impedance variations in organic substrates, improving signal integrity consistency.

Through-Glass Vias

Through-glass vias (TGVs) represent a key enabling technology for glass substrates, providing vertical interconnections with electrical characteristics superior to through-silicon vias. TGVs can be formed using laser drilling, sandblasting, or photosensitive glass processes, then metallized with copper or other conductors. Because glass is an insulator, TGVs do not require the dielectric liner that through-silicon vias need to isolate the conductor from the silicon, which simplifies fabrication and reduces parasitic capacitance.

High-aspect-ratio TGVs with depths exceeding 300 micrometers and pitches below 100 micrometers are achievable, supporting high-density interconnects in glass interposers. The mechanical strength of glass allows thin substrates below 100 micrometers while maintaining structural integrity.

Manufacturing Challenges

Glass substrate fabrication requires specialized equipment and processes different from organic substrate manufacturing. Handling brittle glass panels without breakage demands careful attention to edge finishing and support during processing, because surface flaws and edge chips can propagate into fractures under thermal or mechanical stress. Metallization adhesion requires surface treatment and specialized seed-layer deposition, since copper does not bond to a pristine glass surface the way it bonds to a roughened or chemically treated polymer.

Crack propagation is the central reliability question. A single edge chip or a via-sidewall flaw can grow under thermal cycling into a fracture that destroys the whole substrate, so process development concentrates on via-formation damage, edge strengthening, and stress management at the copper-to-glass interface. Assembly equipment, inspection methods, and known-good-substrate test flows all require adaptation from the organic baseline. Despite these challenges, several substrate suppliers and integrated device manufacturers have moved glass-core technology from laboratory demonstration into pilot and qualification lines aimed at large processor, accelerator, and interposer packages.

Alumina Ceramics

Alumina (aluminum oxide, Al₂O₃) substrates represent the most widely used ceramic substrate technology, available in purities ranging from 92 to 99.6 percent. Higher-purity alumina provides better thermal conductivity (roughly 25 to 30 watts per meter-kelvin) and lower dielectric loss, while lower-purity grades offer cost advantages for less demanding applications. The dielectric constant of alumina is approximately 9 to 10, which remains stable across a wide frequency range.

Thick-film and thin-film metallization processes create conductors on alumina surfaces. Thick-film techniques screen-print conductive pastes followed by firing at high temperatures, while thin-film processes deposit and pattern metals using semiconductor-style photolithography. Thin-film achieves finer features and better line definition, but at higher cost.

Aluminum Nitride

Aluminum nitride (AlN) ceramics provide thermal conductivity exceeding 170 watts per meter-kelvin, approaching that of metals while maintaining electrical insulation. This exceptional thermal performance makes aluminum nitride ideal for power semiconductor packages where efficient heat removal is critical. The thermal expansion coefficient of aluminum nitride closely matches silicon, reducing thermal stress in die-attach applications.

Manufacturing aluminum nitride substrates requires careful control of the sintering atmosphere and the use of sintering aids to achieve maximum thermal conductivity. Cost premiums over alumina limit aluminum nitride to applications where its superior thermal performance justifies the expense. Aluminum nitride is also comparatively brittle, which limits its tolerance for the aggressive power cycling seen in traction and industrial drives.

Silicon Nitride

Silicon nitride (Si₃N₄) trades peak thermal conductivity for mechanical robustness. Its thermal conductivity of roughly 70 to 90 watts per meter-kelvin falls well below aluminum nitride, but its fracture toughness is several times that of alumina and noticeably higher than that of aluminum nitride. That toughness allows thicker copper metallization and survives far more deep power cycles before the ceramic cracks or the copper delaminates.

Silicon nitride has become the substrate of choice for silicon carbide power modules in electric-vehicle traction inverters and rail traction, where high junction temperatures and aggressive thermal cycling would fracture a more brittle ceramic. Its coefficient of thermal expansion, near 3 parts per million per degree Celsius, sits close to that of silicon and silicon carbide, further reducing thermo-mechanical stress at the die attach.

Ceramic Metallization: DBC and AMB

Power-electronics ceramics are metallized with thick copper rather than printed pastes. Direct bonded copper (DBC) bonds copper foil to alumina or aluminum nitride by heating to just below the melting point of copper in a controlled oxygen atmosphere, forming a copper-oxide eutectic at the interface. Active metal brazing (AMB) instead uses a braze alloy containing an active element, typically titanium, that reacts chemically with the ceramic.

The distinction matters because silicon nitride has too little surface reactivity for reliable direct bonding, so silicon nitride substrates are almost always active-metal-brazed. AMB joints also tend to survive more thermal cycles than DBC joints on the same ceramic, which is why AMB dominates high-reliability and wide-bandgap power modules despite its higher cost.

Low-Temperature Co-fired Ceramics

Low-temperature co-fired ceramics (LTCC) enable multilayer ceramic substrates with embedded passive components and complex three-dimensional routing. The low firing temperature (below 900 degrees Celsius) permits co-firing with high-conductivity silver or gold conductors, which would melt at the higher temperatures required for alumina. This technology supports integration of capacitors, inductors, and resistors within the substrate, reducing component count and board area.

LTCC modules find extensive use in RF and microwave applications, where the excellent high-frequency properties of ceramic dielectrics and the ability to create three-dimensional structures with controlled-impedance lines provide performance advantages. Cavity structures within LTCC packages protect sensitive die while maintaining excellent electrical isolation.

High-Temperature Co-fired Ceramics

High-temperature co-fired ceramics (HTCC) based on alumina fired at temperatures exceeding 1500 degrees Celsius provide robust mechanical and hermetic performance, but require refractory metallization (tungsten or molybdenum) that has higher resistance than precious metals. HTCC remains important for high-reliability applications in aerospace and military systems, where hermeticity and long-term stability take precedence over cost.

Polyimide Films

Polyimide films, particularly Kapton and similar materials, dominate flexible substrate applications because of their exceptional combination of flexibility, thermal stability, and chemical resistance. These films retain their properties from cryogenic temperatures to above 300 degrees Celsius, enabling use in extreme environments from spacecraft to engine compartments.

Copper-clad polyimide laminates form the basis of flexible printed circuits, with copper foils bonded to polyimide using adhesive layers or applied directly without adhesive for enhanced flexibility and reliability. The thin profile of flexible circuits (typically 25 to 125 micrometers total thickness) contributes to the weight savings critical in portable electronics and aerospace applications.

Liquid Crystal Polymer Substrates

Liquid crystal polymer (LCP) substrates offer lower moisture absorption than polyimide along with excellent high-frequency electrical properties. The low water uptake (less than 0.04 percent) maintains stable dielectric properties in humid environments, where the higher absorption of polyimide (in the range of a few percent) can cause dimensional and electrical changes. The low loss tangent of LCP (around 0.002) supports millimeter-wave applications including 5G antenna modules and automotive radar.

Stretchable Substrates

Stretchable electronics extend beyond flexibility to enable substrates that elongate under strain while maintaining electrical connectivity. Elastomeric substrates based on silicone (PDMS) or thermoplastic polyurethane accommodate strains exceeding 100 percent through careful design of conductor patterns. Serpentine, mesh, and fractal conductor geometries distribute strain to prevent conductor failure during stretching.

Applications for stretchable substrates include skin-mounted biomedical sensors, conformable electronics for robotics, and stretchable displays. Challenges include maintaining consistent electrical performance under repeated strain cycles and integrating rigid components such as integrated circuits with stretchable interconnects.

Process Technology

The ETS process begins with creating copper traces on a carrier using conventional patterning. A dielectric layer is then laminated over the traces, embedding them within the material. After carrier removal, the exposed trace surfaces provide flat, coplanar bond pads ideal for fine-pitch flip-chip assembly. The process eliminates the trace-height variations that can cause yield issues in conventional substrates.

Performance Benefits

The flat surface topology of ETS improves bump coplanarity control during flip-chip assembly, reducing defects related to non-contact opens and shorts. Fine-pitch capability extends to bump pitches below 100 micrometers, supporting advanced package designs. The embedded traces also benefit from reduced high-frequency losses, because their smoother surfaces lessen the conductor-roughness contribution to loss compared with etched traces.

Applications

High-performance processors, graphics units, and application processors increasingly use ETS technology to enable the fine-pitch bumps required for growing die sizes and I/O counts. Mobile device packages particularly benefit from ETS, because the technology supports the thin package profiles demanded by smartphone designs.

Cavity Formation Methods

Cavities in organic substrates can be formed through selective material removal using routing, laser machining, or chemical etching. Alternatively, build-up processes can create cavities by selectively omitting material in certain regions during layer fabrication. Each method offers trade-offs in cavity wall quality, dimensional control, and cost.

Component Integration

Embedding components within substrate cavities reduces overall package height while providing mechanical protection and improved thermal pathways. Passive components such as capacitors and inductors can be integrated close to the die, reducing parasitic inductance and improving power delivery. Active devices embedded in cavities benefit from shorter interconnect paths and potential performance improvements.

Die Stacking Applications

Cavity substrates enable innovative die-stacking configurations where dies mount at multiple levels within the package. The cavity provides clearance for wire bonds or allows face-to-face die mounting with reduced package height. Multi-die packages using cavity substrates can achieve higher integration density than side-by-side die placement.

Construction and Materials

Metal core printed circuit boards (MCPCBs) consist of a metal base layer (typically 0.5 to 3.0 millimeters thick) bonded to a thin dielectric layer and copper circuitry. The metal core conducts heat laterally to spreading regions and vertically to heat sinks. Aluminum cores offer good thermal performance at low cost, while copper cores provide roughly twice the thermal conductivity for demanding applications.

The dielectric layer between the metal core and circuitry must provide electrical isolation while minimizing thermal resistance. Thermally conductive dielectrics using ceramic fillers achieve thermal conductivities of 1 to 3 watts per meter-kelvin, significantly better than standard FR-4 at roughly 0.3 watts per meter-kelvin.

Thermal Management Advantages

Metal core substrates can reduce junction-to-ambient thermal resistance by 50 percent or more compared with conventional FR-4 substrates. This improvement enables higher power dissipation from components, longer lifetime through reduced operating temperatures, or smaller heat-sink requirements. The excellent thermal spreading in the metal core also improves temperature uniformity across the substrate.

LED Lighting Applications

High-brightness LED modules extensively use metal core substrates to manage the significant heat generated by power LEDs. The substrate provides both the electrical interconnect and the primary thermal path from LED junctions to heat sinks. White-LED efficacy and lifetime depend strongly on junction temperature, making effective thermal management through metal core substrates critical for lighting-product performance.

Power Electronics Applications

Power conversion modules, motor drivers, and power supplies use metal core substrates when power dissipation exceeds the capability of conventional organic substrates. Direct-bonded copper (DBC) on ceramic substrates provides even higher thermal performance for the most demanding power electronics, but metal core substrates offer a cost-effective solution for moderate power levels.

Build-up Film Materials

Ajinomoto Build-up Film (ABF) dominates the high-performance organic substrate market, providing thin dielectric layers (roughly 10 to 40 micrometers) that support laser-drilled microvias with diameters below 50 micrometers. The unreinforced resin film achieves smooth surfaces suitable for fine-line patterning and low loss at high frequencies. Alternative build-up materials include photo-imageable dielectrics and spin-on materials for specific applications.

Semi-additive Patterning

Semi-additive processing (SAP) enables the fine lines and spaces (below 15 micrometers) required for advanced substrates. The process deposits a thin seed layer, patterns photoresist, electroplates copper in the exposed areas, strips the resist, and removes the seed layer by flash etching. This approach creates conductors with controlled geometry and smooth surfaces, unlike subtractive etching, where undercut limits feature resolution.

Modified semi-additive processing (mSAP) achieves even finer features by using ultra-thin copper foil (less than 5 micrometers) as the seed layer. The reduced etching required to remove the thinner seed layer minimizes undercutting and line loss, enabling lines and spaces below 10 micrometers.

Layer Count Considerations

Substrate stack-ups are described by a build-up notation such as 6-2-6 or 10-2-10, giving the number of build-up layers above the core, the core layers, and the build-up layers below. Large processor and accelerator packages sit at the upper end of that range, with ten or more build-up layers per side and total layer counts above twenty. Each additional layer adds material cost, process time, and another opportunity for yield loss, so layer count is optimized against routing density rather than maximized.

Layer count is not purely a routing question. Power delivery competes with signal escape for metal, and thicker stacks worsen warpage, because every additional asymmetric layer pair adds stored stress that appears as bow at reflow temperature. Design tools assign layers and manage via utilization to hold layer count down while meeting impedance, escape-routing, and power-integrity targets.

Coreless and Thin-Core Substrates

Coreless substrates omit the rigid glass-reinforced core entirely and build the whole stack from build-up layers on a sacrificial carrier that is removed at the end. Eliminating the core removes the long, high-inductance plated through-holes that dominate the vertical path in a cored substrate, which shortens power-delivery loops and improves high-speed signal paths. It also cuts overall package thickness, which matters in mobile and stacked packages.

The penalty is stiffness. Without a core, the substrate warps more readily during assembly, so coreless designs demand tight symmetry in the stack-up, stiffening rings or lids in large packages, and carefully tuned reflow profiles. Thin-core substrates, which keep a much-reduced core, occupy the middle ground and are common where full coreless construction cannot meet warpage limits.

Microvia Technology

IPC-T-50 defines a microvia as a blind structure with a maximum aspect ratio of one to one and a total depth no greater than 0.25 millimeters, measured from the capture land to the target land. In practice, printed boards use microvia diameters between roughly 50 and 150 micrometers, while package substrates work well below that, with build-up microvias commonly under 50 micrometers. CO₂ laser drilling creates blind vias in organic dielectrics efficiently, while UV lasers achieve smaller diameters for the finest pitches.

Stacked microvias, where vias in successive layers align directly above one another, maximize routing density but require careful copper filling to ensure structural integrity. Stacked structures have a documented history of thermally induced interfacial separation at the via target land, which is why IPC-6012 adds a stacked-microvia reliability provision and many designers prefer staggered microvias where routing allows.

Via-in-pad designs place microvias directly under component pads rather than routing traces to offset vias. This approach reduces trace length and inductance while maximizing component placement density. Filled and planarized microvias provide flat surfaces for reliable component attachment over vias.

Design Rules and Capabilities

Volume flip-chip substrate production using semi-additive processing on build-up film runs at roughly 8 micrometer lines and 8 micrometer spaces, with leading-edge lines pushing toward 5 micrometers using smooth, low-profile copper. Die-to-die chiplet interfaces are the pressure point, since their bump pitches call for routing densities finer still, which is much of the motivation behind glass cores and silicon bridges. IPC-2226 is the sectional design standard covering HDI boards built with microvias, fine lines, and sequential lamination.

Applications in Advanced Packaging

Virtually all high-performance semiconductor packages now use HDI substrate technology. Mobile processor packages, graphics processing units, networking chips, and high-bandwidth memory interfaces all depend on HDI capabilities to connect dense die to the outside world. The substrate has become the limiting factor in many packages, driving ongoing investment in HDI technology advancement.

Technology Transition

SLP technology emerged from the need to route increasingly dense mobile processor packages on main PCBs. Traditional HDI processes with minimum features around 40 micrometers could not efficiently connect advanced packages. By applying substrate-level modified semi-additive processing to board fabrication, SLPs reach line widths and spaces of 30 by 30 or 25 by 25 micrometers in volume production, with the leading edge near 20 micrometers. That places SLP squarely between conventional HDI boards and true IC substrates, both in capability and in cost.

Manufacturing Considerations

Producing SLPs requires investment in substrate-like equipment and processes, including thin-film seed-layer deposition, advanced photolithography, and precise copper plating. Handling large panels (versus smaller substrate strips) presents additional challenges. Nevertheless, major PCB manufacturers have established SLP production for high-volume smartphone applications.

Design Benefits

SLP technology enables thinner, smaller main boards through higher routing density in fewer layers. Reduced board thickness and layer count translate directly to thinner smartphones and other portable devices. The finer features also improve high-speed signal integrity through tighter impedance control and reduced stub effects.

Electrical Requirements

Operating frequency dictates dielectric material selection, with higher frequencies requiring lower-loss materials to maintain signal integrity. High-speed digital designs demand controlled impedance and low crosstalk achieved through careful geometry control. Power delivery requires sufficient copper cross-section and low-inductance routing. Understanding the electrical environment guides appropriate substrate technology and material selection.

Thermal Requirements

Power dissipation levels determine whether organic substrates suffice or ceramic or metal core solutions are necessary. Thermal expansion matching affects long-term reliability, particularly for large die. Operating temperature range influences material selection, with high-temperature applications requiring polyimide or ceramic over standard organic materials.

Mechanical Requirements

Package form factor and application environment drive mechanical considerations. Flexible substrates enable non-planar applications but add complexity. Dimensional stability requirements affect material and process selection. Reliability under thermal cycling, mechanical shock, and vibration depends on appropriate material matching and design.

Warpage deserves separate attention as package body sizes grow. Because the substrate, the die, and the mold compound expand at different rates, a package that is flat at room temperature can bow measurably at reflow temperature, opening joints at the corners or bridging them at the center. Symmetric stack-ups, stiffener rings, lids, and balanced copper distribution are the usual countermeasures, and warpage limits frequently constrain substrate thickness and layer count more tightly than routing does.

Standards and Qualification

Substrate procurement rests on a small set of industry documents. IPC-4101 specifies base materials for rigid and multilayer boards, letting designers call out a laminate by specification sheet rather than by trade name. IPC-6012 covers qualification and performance for rigid printed boards, IPC-6013 covers flexible and rigid-flex constructions, and IPC-2226 provides the sectional design standard for HDI boards. Test methods referenced by these documents live in IPC-TM-650.

Moisture control is governed separately. The joint IPC and JEDEC standard J-STD-020 classifies moisture sensitivity levels for nonhermetic surface-mount devices, and J-STD-033 specifies the handling, packing, and floor-life practices that follow from that classification. These matter for substrates because organic dielectrics absorb water, and trapped moisture flashing to steam during reflow is a classic cause of delamination.

Cost and Volume Considerations

Substrate technology selection must balance performance requirements with economic reality. Organic substrates offer the lowest cost for mainstream applications. Ceramic and glass substrates command premiums justified by performance benefits in specific applications. Production volume affects process selection, with high volumes justifying investment in advanced processes that reduce unit cost.

Ultra-fine Line Substrates

Continued scaling demands substrate features approaching 5 micrometers and below. Advanced lithography, semi-additive processing improvements, and new materials enable this evolution. Direct-pattern techniques that eliminate photoresist may further extend scaling.

Glass Substrate Adoption

Glass-core substrates are transitioning from development toward qualification and early production for high-performance applications. Superior dimensional stability and electrical properties make glass attractive for chiplet-based systems that require precise interconnect alignment over large package areas, which is exactly where organic substrate warpage becomes limiting. Substrate suppliers and integrated device manufacturers in the United States and Korea have built dedicated lines and are sampling glass-core substrates to processor and accelerator customers, with the industry generally framing the late 2020s as the transition to volume use rather than a single switchover date.

Heterogeneous Integration

Advanced substrates increasingly serve as platforms for heterogeneous integration, connecting diverse chiplets in 2.5D and 3D configurations. This drives demand for finer features, embedded components, and novel structures such as silicon bridges and embedded silicon. Substrates evolve from simple interconnects into active integration platforms.

Sustainable Substrates

Environmental considerations are influencing substrate development. Halogen-free materials address flame-retardant concerns. Reduced copper usage lowers environmental impact. Recyclable and biodegradable materials are under investigation for appropriate applications. The substrate industry is working to reduce its environmental footprint while sustaining performance advancement.