Electronics Guide

Why Disaggregation Pays

The case for chiplets begins with a hard physical limit. A lithography scanner exposes one rectangular field at a time, and for current extreme ultraviolet and deep ultraviolet tools that field measures 26 millimeters by 33 millimeters, or 858 square millimeters. A monolithic die cannot exceed that reticle field unless adjacent exposures are stitched together, a technique that adds cost and risk. High-numerical-aperture EUV scanners, which raise the numerical aperture to 0.55 to print finer features, retain the 26-millimeter slit but halve the scan dimension to 16.5 millimeters, cutting the maximum field to roughly 429 square millimeters. The reticle ceiling therefore falls at precisely the moment transistor budgets are rising, leaving partitioning across multiple dies as the only route to larger systems.

Yield economics reinforce the argument. Random manufacturing defects fall across a wafer at a roughly uniform density, so the probability that a die is defect-free declines exponentially with die area. Doubling the area of a die roughly squares its defect-free probability, which turns a comfortable yield into a poor one. Splitting the same function into several smaller dies raises the fraction of usable silicon, and it also allows partial dies to be salvaged: a compute die with one faulty core can be sold into a lower-core-count product rather than scrapped. Reuse compounds the benefit, because a single validated compute die can populate desktop, workstation, and server products that differ only in how many dies the package carries.

These gains are not free. Every signal that crosses a die boundary consumes energy that an on-die wire would not, adds latency measured in nanoseconds rather than picoseconds, and occupies die edge, or shoreline, that could otherwise hold logic. Advanced substrates, interposers, and bridges cost more than a plain organic package. Assembly and test steps multiply, and a defect discovered after assembly destroys several good dies along with the bad one. Chiplet partitioning pays off when the silicon and yield savings exceed the added packaging, interconnect power, and test overhead, which is why the approach appeared first in high-value server processors and accelerators and has reached cost-sensitive segments only gradually.

Universal Chiplet Interconnect Express (UCIe)

Universal Chiplet Interconnect Express represents the semiconductor industry's most significant standardization effort for chiplet interoperability. Version 1.0 was released in 2022 with backing from major companies including AMD, Arm, Google, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC, and the consortium incorporated as an industry body shortly afterward. UCIe defines a layered specification for die-to-die connectivity that allows chiplets from different vendors to communicate within a package.

Successive revisions have extended the standard while preserving backward compatibility. Version 1.1, released in 2023, added compliance testing provisions, simultaneous multiprotocol operation, runtime health monitoring aimed at automotive use, and lower-cost bump maps. Version 2.0, released in August 2024, introduced a standardized system architecture for manageability and for design-for-excellence functions such as test, debug, and telemetry across the lifecycle of a multi-chiplet package, and it defined UCIe-3D for vertically bonded dies at pitches ranging from 25 micrometers down to a micrometer or less. Version 3.0, released in August 2025, doubled the peak signaling rate and added runtime recalibration, extended sideband reach, and firmware-management features.

The UCIe specification encompasses multiple layers of the communication stack. At the physical layer, UCIe defines the electrical interface, bump pitch, and signaling for two packaging classes. The standard package targets cost-sensitive organic substrates with a comparatively coarse bump pitch of roughly 100 to 130 micrometers and reaches of up to about 25 millimeters, while the advanced package targets silicon interposers and embedded bridges with a much finer bump pitch of roughly 25 to 55 micrometers and reaches under 2 millimeters. The die-to-die adapter layer provides packetization, flow control, cyclic redundancy checking, and link-state management. The protocol layer maps upper-layer protocols such as PCIe and Compute Express Link, or a raw streaming mode for custom traffic, onto the physical link.

UCIe's bandwidth capabilities are substantial. Versions through 2.0 define per-lane rates of 4, 8, 12, 16, 24, and 32 GT/s, and version 3.0 adds 48 and 64 GT/s. The interface is organized into modules: a standard-package module carries 16 data lanes, and an advanced-package module carries 64, with one to four modules aggregated per link for more bandwidth. A single standard x16 module running at 32 GT/s therefore carries about 64 gigabytes per second per direction, while an advanced x64 module at the same rate carries roughly 256 gigabytes per second per direction, and four such modules approach a terabyte per second each way. Because the advanced package packs those lanes into a far finer bump pitch, it delivers roughly an order of magnitude more bandwidth per millimeter of die edge than the standard package, which is the figure of merit for designs limited by shoreline rather than by area.

Beyond raw throughput, the specification addresses the practical concerns that determine whether a link survives production. It defines link training and initialization sequences, lane repair through spare lanes that can be substituted for defective ones, low-power link states, a low-speed sideband channel for management and parameter negotiation, and compliance test procedures intended to make interoperability verifiable rather than merely asserted. Energy efficiency is a first-order design target as well: die-to-die links aim for the sub-picojoule-per-bit range, one to two orders of magnitude better than a comparable off-package serial link, since interconnect power would otherwise consume the budget freed by disaggregation.

Die-to-Die Protocols and Interfaces

Beyond UCIe, several die-to-die interfaces serve different market segments and use cases. AMD's Infinity Fabric carries coherent traffic between compute dies, I/O dies, and memory controllers, and it exists in both an on-package variant tuned for short, wide, low-energy links and an off-package variant that connects sockets across a board. Intel pairs its Advanced Interface Bus, a parallel physical-layer interface with a clock-forwarded, source-synchronous design, with packaging technologies such as the embedded multi-die interconnect bridge; the interface and the package are distinct layers, and Intel has since adopted UCIe alongside its own. Bunch of Wires, developed under the Open Compute Project's Open Domain-Specific Architecture effort, offers a deliberately simple, low-overhead parallel interface for organic substrates. Proprietary interfaces can be tuned to a single vendor's architecture, while UCIe trades some of that specialization for cross-vendor interoperability.

Die-to-die interfaces must balance competing requirements. Bandwidth per millimeter of die edge determines how much traffic a partitioned design can sustain, since the interface competes with everything else that needs shoreline. Energy per bit governs how much of the power budget interconnect consumes, and it dominates in systems where hundreds of lanes switch continuously. Latency matters most for cache-coherent traffic, where a memory access that crosses a die boundary stalls execution; architects often accept a modest latency penalty on a coherent link in exchange for a large gain in yield. Reliability and testability affect both manufacturing yield and field failure rates. Successful interfaces optimize across all these dimensions for their target applications rather than maximizing any one of them.

The electrical implementation of die-to-die interfaces has evolved rapidly. Early multi-chip modules used conventional package-level interconnects with relatively wide spacing and limited bandwidth, and they relied on the same drivers and equalization used for board-level signaling. Because an in-package link is short and well controlled, modern designs can discard much of that overhead, using simple single-ended drivers, forwarded clocks, and low signal swings. Micro-bumps with pitches as fine as 25 micrometers allow thousands of connections between adjacent dies. Hybrid bonding, which forms direct copper-to-copper contacts between planarized die surfaces without solder, reaches pitches near 6 micrometers in current high-volume production and continues to scale downward, approaching the connection density of on-chip wiring while preserving the modularity of separate dies.

Known Good Die Testing

Known good die testing is essential for economically viable chiplet-based systems. In a monolithic flow, a defective die is discarded before packaging and costs little more than its share of the wafer. In a chiplet flow, one bad die condemns every other die in the package along with the substrate and the assembly labor. The arithmetic is unforgiving: if each die enters assembly with a small independent probability of being defective, the probability that a package of many dies is entirely good is that figure raised to the number of dies, so escape rates that are tolerable for a single chip become ruinous for a package holding a dozen.

Testing chiplets presents challenges that packaged-part testing does not. Dies must be screened at wafer level, or after singulation but before assembly, which requires probe technology capable of landing on fine-pitch micro-bump arrays without damaging them. The probe interface cannot run at the speeds or lane counts of the final die-to-die link, so at-speed coverage must come from structures on the die itself rather than from the tester. Coverage must be sufficient to catch defects that would surface only at the system level, while avoiding test time that raises cost without improving outgoing quality.

Practical known good die programs therefore lean on design-for-test structures. Built-in self-test engines exercise logic and embedded memory at full speed through a narrow probe interface. Boundary-scan architectures derived from IEEE 1149.1 are extended to die-to-die interfaces, and IEEE 1838 defines a test access architecture for three-dimensional stacked integrated circuits that gives a tester a consistent path into dies buried in a stack. UCIe 2.0 added a complementary manageability and design-for-excellence architecture so that test, debug, and telemetry work across chiplets from different suppliers. Burn-in and voltage or temperature stress screening remove early-life failures, and statistical outlier analysis flags parts that pass every test yet behave unlike their neighbors on the wafer, a technique that has proved effective at catching latent defects.

Multi-Chip Modules and System-in-Package Design

Multi-chip modules integrate multiple dies within a single package, providing a systems-level approach to semiconductor design. Modern modules range from simple combinations of two or three dies to assemblies holding dozens of chiplets alongside stacked memory. The package substrate provides power delivery, signal routing, and a thermal path while establishing the mechanical and environmental protection required for reliable operation. Chiplet architectures are best understood as a disciplined, standardized form of the multi-chip module rather than a break with it: the novelty lies in the interface standards, the partitioning methodology, and the interconnect density, not in the idea of putting several dies in one package.

System-in-package designs extend the concept to encompass complete systems within a single package. These designs may include processors, memory, power management circuits, radio-frequency front ends, and passive devices, eliminating much of the board-level integration that would otherwise be required. The approach is particularly valuable for mobile, wearable, and implantable devices where volume is severely constrained, and for applications that require tight integration between technologies, such as gallium arsenide or gallium nitride radio-frequency devices and silicon logic, that cannot be economically combined on a single die.

The design of multi-chip systems requires careful attention to interactions between dies. Thermal coupling means that heat generated by one die raises the operating temperature of its neighbors, so power and frequency management must be coordinated across the package rather than tuned per die. Power delivery networks must supply the aggregate current of all dies while holding regulation during the fast load steps that modern processors impose, which pushes designers toward on-package capacitance and, increasingly, integrated voltage regulators. Signal integrity analysis must account for crosstalk between the dense parallel links crossing die boundaries, for return-path discontinuities where signals transition between die, bump, and substrate, and for simultaneous switching noise generated by hundreds of drivers changing state together.

Heterogeneous Integration

Heterogeneous integration combines dies fabricated in different process technologies within a unified package, enabling each functional block to use the optimal manufacturing process for its requirements. A high-performance processor might combine leading-edge logic dies for compute cores with mature-node dies for I/O interfaces, specialized memory technologies, and even photonic components for high-bandwidth interconnects. This approach maximizes system performance while optimizing costs by avoiding the use of expensive leading-edge processes for functions that do not require them.

The benefits of heterogeneous integration extend beyond cost optimization. Different functional blocks have fundamentally different technology requirements: high-speed analog circuits often perform better in older process nodes with thicker oxides and lower leakage, while digital logic benefits from the smallest available transistors. Memory technologies have their own optimization curves distinct from logic processes. By enabling independent optimization of each block, heterogeneous integration achieves system-level performance that would be impossible with any single monolithic technology.

Practical heterogeneous integration requires solving numerous technical challenges. Different process technologies may have incompatible voltage levels, requiring level-shifting circuits at die boundaries. Thermal expansion mismatches between dies with different substrate materials can stress interconnections. Design tools must handle the complexity of systems spanning multiple technology libraries with different design rules and characterization data. Despite these challenges, heterogeneous integration is increasingly adopted across market segments from data center processors to automotive systems.

Chiplet Marketplaces and Ecosystem Development

The vision of a chiplet marketplace, where designers can select standardized dies from multiple vendors to assemble custom systems, is driving significant industry investment. Such a marketplace would transform the semiconductor industry's economics by enabling design reuse across companies, reducing the barrier to entry for new products, and fostering innovation through specialization. Companies could focus on their core competencies, developing best-in-class chiplets in their areas of expertise while sourcing other functions from specialized suppliers.

Realizing this vision requires overcoming substantial technical and business challenges. Technical interoperability demands standardized interfaces, but also compatible voltage levels, thermal characteristics, and reliability specifications. Business models must address intellectual property concerns, liability allocation, and quality assurance across complex supply chains. The industry is experimenting with various approaches, from consortium-based development to commercial chiplet offerings to internal reuse programs within large companies.

Early examples of chiplet commerce are emerging. Memory manufacturers supply known good die versions of their products for integration into multi-chip packages, and stacked high-bandwidth memory is already a merchant chiplet in everything but name. Intellectual property vendors are extending their business models from synthesizable design IP to hardened, physically implemented chiplets. Foundries publish reference flows, assembly design kits, and integration services that lower the effort of adopting advanced packaging.

Progress should nonetheless be read carefully. Almost every chiplet product shipping today combines dies from a single company, or from two companies working in close coordination, because a chiplet's electrical, thermal, and reliability behavior is meaningful only in the context of a particular package. A truly interchangeable chiplet would have to arrive with a characterized thermal profile, a defined power delivery contract, a known test escape rate, and clear liability terms, and the industry has not yet settled how those obligations are described or enforced. Standardized interfaces are a necessary condition for a marketplace, not a sufficient one, and the fully realized vision remains some years away.

Standardization Efforts

Beyond UCIe, multiple standardization initiatives address different aspects of chiplet technology. The Open Compute Project's Open Domain-Specific Architecture work produced the Bunch of Wires interface and continues to pursue open chiplet specifications and business frameworks for data center hardware. The Heterogeneous Integration Roadmap, coordinated through the IEEE Electronics Packaging Society with partner organizations, publishes industry consensus on how packaging technology is expected to evolve and where the gaps lie. JEDEC standards define the memory interfaces, notably the high-bandwidth memory family, that make stacked memory a drop-in element of a chiplet package. Together these complementary efforts supply the technical foundation that broad chiplet adoption requires.

Standardization extends beyond electrical interfaces to encompass design methodologies, testing procedures, and quality specifications. Common frameworks for describing chiplet capabilities enable automated design tools to evaluate compatibility and optimize system configurations. Standardized test protocols ensure consistent quality assessment across suppliers. Reliability standards define stress testing requirements and field failure rate expectations. This comprehensive standardization infrastructure is essential for the commercial viability of chiplet marketplaces.

The standardization process itself involves careful balancing of competing interests. Established players may prefer standards that leverage their existing investments, while newcomers benefit from more open approaches. Technical optimality must be weighed against practical implementability and backward compatibility. The success of standards ultimately depends on broad adoption, requiring sufficient technical merit and business value to motivate industry participants to align their development efforts.

Thermal Management Challenges

Thermal management is among the most significant challenges in chiplet-based systems. Dense integration concentrates heat generation within compact packages, while die boundaries and packaging materials impede heat flow compared to monolithic silicon. The thermal coupling between adjacent dies means that power management strategies must coordinate across the entire package rather than optimizing individual dies in isolation. Failure to adequately address thermal challenges can limit performance, reduce reliability, and constrain design options.

Several approaches address chiplet thermal management. Package-level solutions include advanced thermal interface materials, integrated heat spreaders, and sophisticated heatsink designs optimized for non-uniform heat distribution. Die-level approaches incorporate thermal sensors and dynamic voltage and frequency scaling that respond to local temperature conditions. Some designs include dedicated thermal management dies with embedded cooling channels or thermoelectric cooling elements. The most effective solutions combine multiple techniques in coordinated thermal management systems.

Thermal simulation and modeling tools are essential for chiplet thermal design. These tools must accurately capture heat generation distributions within each die, thermal resistance of bump arrays and package materials, and convective and radiative heat transfer to the ambient environment. Multi-physics simulation combining thermal, electrical, and mechanical analysis reveals interactions that single-domain analysis would miss. Accurate modeling early in the design process prevents costly iterations when thermal problems emerge in physical prototypes.

Design Tools and Methodologies

Electronic design automation for chiplet-based systems is evolving rapidly to address the unique challenges of multi-die design. Traditional EDA tools optimized for monolithic designs require extension to handle the additional complexity of die partitioning, inter-die interface design, and package-level integration. New tools and methodologies are emerging to support chiplet architecture exploration, interface optimization, and system-level verification.

Design partitioning decisions significantly impact chiplet system success. Determining which functions should be combined on each die involves trade-offs between manufacturing cost, interconnect overhead, thermal constraints, and design complexity. These decisions must be made early in the design process but depend on information about die sizes, yields, and interface characteristics that may not be fully known. Design space exploration tools help architects evaluate alternatives and identify optimal partitioning strategies.

Verification of chiplet-based systems presents particular challenges. Each die must be verified independently, while system-level verification must confirm correct operation across die boundaries. Mixed-signal simulations may be required when dies with different electrical characteristics interact. Emulation and prototyping become more complex when the system spans multiple physical dies. The industry is developing hierarchical verification methodologies that manage this complexity while ensuring complete coverage of inter-die interactions.

Packaging Technologies for Chiplets

The physical packaging technologies enabling chiplet integration continue to advance rapidly. In 2.5D integration, multiple dies sit side by side on a silicon interposer that provides high-density routing between them. The approach was pioneered for high-bandwidth memory integration and now supports diverse chiplet configurations; TSMC's chip-on-wafer-on-substrate family and Samsung's I-Cube are widely used examples. The interposer's silicon substrate enables interconnect density approaching that of back-end-of-line wiring on the dies themselves, supporting the thousands of connections required for wide die-to-die interfaces. Because interposers are themselves subject to the reticle limit, suppliers have moved to stitched and multi-reticle interposers to accommodate packages that now exceed several times the reticle area.

True 3D integration stacks dies vertically, connecting them with through-silicon vias, micro-bumps, or hybrid bonds. Stacking minimizes lateral footprint and shortens latency-critical paths, and hybrid bonding in particular removes the solder joint entirely, permitting far finer pitch and lower parasitic capacitance. It also intensifies thermal challenges, because heat from a buried die must travel through the dies above it. Production 3D designs therefore favor pairings that tolerate the constraint: memory stacked over logic, where the memory's lower power density limits the added heat, or cache stacked over a processor die, as in AMD's 3D V-Cache products, where the added silicon sits over a comparatively cool region of the core complex.

Embedded bridge technologies offer an intermediate approach, placing small silicon bridges inside an organic package substrate to provide high-density routing only where dies meet, while lower-cost organic routing carries everything else. Intel's embedded multi-die interconnect bridge exemplifies the method, delivering interposer-class connection density between adjacent dies without the cost and reticle constraints of a full interposer. Fan-out packaging provides another option, embedding dies in a molded panel or wafer and building a redistribution layer over them, which relaxes pitch requirements at the board interface while keeping package dimensions compact. In practice these techniques combine: a modern accelerator may use hybrid bonding within a stack, an interposer or bridge between stacks, and fan-out or flip-chip routing to the board.

Industry Applications and Case Studies

AMD's chiplet-based processors demonstrate the commercial success of disaggregated design. Beginning with the second generation of its Zen architecture, the company separated compute cores into core complex dies and moved memory controllers and external interfaces onto a separate I/O die. The same validated compute die then populates desktop, workstation, and server products that differ chiefly in how many dies the package holds; the fifth-generation EPYC server processors, code-named Turin, place as many as sixteen compute dies around a single I/O die to reach 192 cores in the density-optimized configuration. Because the compute die and the I/O die have different needs, the compute die can use the most advanced available process while the I/O die stays on a mature, cheaper node. The strategy's success has influenced the direction of the entire processor industry.

Other vendors have converged on similar structures by different routes. Intel builds client processors from separate compute, graphics, system-on-chip, and I/O tiles assembled on its Foveros stacking technology. Apple's UltraFusion packaging joins two large processor dies through a silicon interposer so that software sees a single chip. Leading AI accelerators pair one or two reticle-limited compute dies with several stacks of high-bandwidth memory on an interposer, a configuration that no monolithic die could reach at any price.

Data center applications continue to drive adoption. Network switches combine multiple dies for high-bandwidth packet processing, and some now co-package optical engines at the package edge to escape the reach limits of electrical serial links. Custom silicon for hyperscale operators uses chiplets to hit design points that monolithic integration cannot. The economics of data center deployment, with high unit value, large volumes, and stringent performance requirements, make the engineering investment in chiplet integration particularly attractive.

Emerging applications extend chiplet concepts to new domains. Automotive systems can combine safety-certified chiplets with advanced driver assistance functions on common platforms. Aerospace and defense applications benefit from chiplet modularity for system customization and technology refresh. Consumer electronics increasingly adopt system-in-package approaches that share chiplet technologies. As the ecosystem matures, chiplet architectures are becoming accessible to a broader range of applications and market segments.

Future Directions

The trajectory of chiplet technology points toward increasingly sophisticated integration and broader ecosystem development. Continued advances in interconnect technology will push bandwidth density higher while reducing power consumption. Novel packaging approaches including photonic interconnects and advanced cooling technologies will address current limitations. The standardization infrastructure will mature, enabling the marketplace vision where diverse chiplets from multiple sources can be readily combined.

Emerging applications will drive chiplet technology in new directions. Quantum computing systems may adopt chiplet approaches to integrate classical control electronics with quantum processors. Neuromorphic computing could benefit from heterogeneous integration of analog and digital processing elements. Photonic computing demands integration of optical and electronic components that chiplet packaging is uniquely positioned to enable. These applications will both benefit from and drive advancement of chiplet technologies.

The broader implications of chiplet architectures extend beyond technical performance to reshape industry structure. The disaggregation of system design enables new business models and competitive dynamics. Companies can specialize in specific chiplet types, creating value through focused excellence rather than attempting to master all aspects of system design. This specialization may accelerate innovation by enabling more participants to contribute to the semiconductor ecosystem while reducing the barriers to bringing new products to market.

Chiplet architectures are best understood not as a replacement for monolithic integration but as an additional degree of freedom. Where a design fits comfortably within a reticle, yields well, and gains nothing from mixing process technologies, a single die remains simpler, cheaper, and faster. Where it does not, partitioning converts an impossible design into a manufacturable one, at the price of interface power, packaging cost, and test complexity that the architect must budget for from the outset. The standards, packaging technologies, and test methodologies described above exist to make that price predictable, and their steady maturation is what has moved chiplets from a technique of last resort to a mainstream architectural choice.

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