Electronics Guide

Architecture Overview

The CT-DS modulator architecture comprises several essential blocks:

• Continuous-Time Loop Filter: Active RC, Gm-C, or LC-based filter that provides the integrating and shaping functions
• Quantizer: Comparator (single-bit) or flash ADC (multi-bit) that samples the loop filter output at the clock frequency
• Feedback DAC: Converts the digital output back to an analog signal for subtraction from the input
• Clock Generation: Provides the sampling clock that determines the oversampling ratio

The absence of an explicit sample-and-hold circuit at the input distinguishes CT modulators from their discrete-time relatives. This seemingly subtle difference has profound implications for system performance, particularly regarding anti-aliasing and power consumption.

Advantages Over Discrete-Time Implementations

CT-DS modulators offer several compelling advantages:

• Inherent Anti-Aliasing: The continuous-time loop filter attenuates high-frequency signals before sampling occurs, providing built-in anti-aliasing that relaxes or eliminates the need for explicit input filtering
• Higher Bandwidth Capability: Without the settling time constraints of switched-capacitor circuits, CT modulators can achieve higher sampling frequencies and signal bandwidths
• Lower Power Consumption: A continuous-time integrator never has to settle within a clock phase, so its amplifier needs a unity-gain bandwidth of the order of the sampling rate rather than several times it, and no sampling capacitor must be charged at every clock edge. At a given sampling rate this usually lowers amplifier power.
• Reduced Thermal Noise: With no sampling switch at the input, there is no kT/C sampling noise and no aliasing of wideband thermal noise into the signal band, so continuous-time integrators can reach lower noise floors than switched-capacitor implementations at equivalent power
• Process Scalability: CT circuits can take advantage of faster transistors in advanced CMOS nodes more readily than switched-capacitor designs

Design Challenges

Despite their advantages, CT-DS modulators present unique design challenges:

• RC Time Constant Variation: Process, voltage, and temperature (PVT) variations affect the absolute values of resistors and capacitors, requiring calibration or tuning
• Excess Loop Delay: Propagation delays through the quantizer and feedback DAC degrade phase margin and must be compensated
• DAC Non-Idealities: The feedback DAC directly affects modulator linearity, making its implementation critical
• Clock Jitter Sensitivity: The feedback DAC output is sensitive to clock timing errors, which convert to noise in the signal band

Loop Filter Topologies

Several circuit topologies can implement CT loop filters:

• Active RC Integrators: Use operational amplifiers with resistive input and capacitive feedback. These provide excellent linearity and are well-suited for low to moderate frequencies. The transfer function is H(s) = −1/(sRC), with the time constant set by passive component values.
• Gm-C Integrators: Employ transconductance amplifiers driving capacitive loads. These offer higher bandwidth potential and better power efficiency at high frequencies. The transfer function is H(s) = G_m/(sC), where G_m is the transconductance.
• LC Resonators: Use inductors and capacitors to create bandpass responses for narrowband applications. These are particularly effective for RF delta-sigma modulators where the signal band is centered at a high intermediate frequency.
• Hybrid Topologies: Combine different integrator types to optimize performance across the frequency range, using active RC for low frequencies and Gm-C for higher frequencies.

Filter Order and Architecture

Higher-order loop filters provide more aggressive noise shaping but require careful stability management:

• First-Order: Single integrator provides 20 dB/decade noise shaping. Its noise transfer function, NTF(z) = 1 − z⁻¹, has a zero at DC and a magnitude of 2 sin(πf/f_s), which rises at 20 dB/decade well below f_s. Simple and inherently stable but offers limited resolution for a given oversampling ratio.
• Second-Order: Two integrators achieve 40 dB/decade shaping, with NTF(z) = (1 − z⁻¹)² in the classic design. Provides good performance with manageable stability considerations.
• Third-Order and Higher: Additional integrators increase noise shaping slope but require careful coefficient design to maintain stability. Feedforward or feedback compensation is typically necessary.

Common loop filter architectures include:

• Chain of Integrators with Distributed Feedback (CIFB): A feedback DAC drives each integrator input, which sets the NTF poles directly. With the input applied only at the first integrator, the STF is inherently low-pass, giving the strongest anti-aliasing, but every integrator carries a scaled copy of the input and internal signal swings are large.
• Chain of Integrators with Feedforward (CIFF): A single feedback DAC drives the first integrator, and weighted paths from each integrator output are summed at the quantizer input. With an added input path straight to that summing node, the integrators process mainly quantization noise, which relaxes their swing and linearity requirements. The price is an STF that tends to peak beyond the signal band, weakening anti-aliasing.
• Resonator-Based Structures: Include resonant sections that place notches in the NTF at specific frequencies, optimizing noise shaping for the signal band

DT-to-CT Transformation

A common design methodology begins with a discrete-time prototype and transforms it to continuous-time. This transformation must account for the sampling process and DAC pulse shape:

• Impulse-Invariant Transformation: The standard mapping. It forces the continuous-time loop filter's impulse response, sampled at the quantizer input, to match that of the discrete-time prototype at every sampling instant. The DAC pulse shape is folded into the calculation, and pulses whose edges align with the sampling grid, such as full-period non-return-to-zero (NRZ), are handled directly.
• Modified Z-Transform: Extends the mapping to account for DAC transitions that fall between sampling instants, as occur with return-to-zero (RZ) or delayed pulses and with fractional excess loop delay.
• Pulse Shape Consideration: Different DAC pulse shapes (NRZ, RZ, half-delayed RZ) require different transformation coefficients

The transformation produces continuous-time coefficients (resistor and capacitor values, or transconductances) that implement the desired discrete-time transfer function when the system is sampled at the clock rate.

Component Sensitivity and Calibration

Unlike discrete-time modulators where performance depends on component ratios, CT modulators are sensitive to absolute component values, because each integrator's RC product (or C/G_m ratio) must stay in proportion to the clock period for the sampled loop to reproduce the intended NTF:

• RC Product Variation: Integrated resistors and capacitors can vary by 20% or more across process corners, directly affecting loop filter coefficients
• Tuning Techniques: On-chip oscillators, PLLs, or replica circuits can provide references for calibration. Digitally controlled resistor or capacitor banks enable coefficient adjustment.
• Background Calibration: Adaptive algorithms can track and correct coefficient drift during normal operation
• Chopping and Dynamic Element Matching: Reduce the impact of component mismatch and offset on modulator performance

Sources of Excess Loop Delay

Multiple components contribute to ELD:

• Quantizer Delay: Comparator regeneration time and flash ADC encoding delay
• DAC Switching Time: Time required for current sources or switches to respond to the digital input
• Logic Delays: Any digital processing between quantizer output and DAC input
• Interconnect Delays: Signal propagation through routing, especially significant at high frequencies

The total ELD is often expressed as a fraction of the sampling period. Even delays of 10 to 20% of the clock period can significantly impact modulator stability and performance.

Effects on Modulator Performance

Excess loop delay modifies the effective transfer function seen by the loop:

• NTF Modification: The noise transfer function changes from its designed shape, potentially increasing in-band noise
• Stability Degradation: Phase margin decreases, moving the system closer to instability
• Out-of-Band Gain Increase: The NTF out-of-band gain may increase, risking quantizer overload
• SNR Loss: Overall signal-to-noise ratio degrades as noise shaping becomes less effective

Compensation Techniques

Several approaches can mitigate excess loop delay effects:

• Direct Feedback Path: The classic remedy adds an extra, fast DAC whose output feeds the quantizer input directly, a path around the quantizer alone that bypasses every integrator. Together with retuned loop coefficients, it restores the loop's high-frequency gain and the intended NTF. Errors in this DAC enter at the same point as quantization noise and are shaped by the loop, so it needs little accuracy.
• Loop Filter Coefficient Adjustment: The DT-to-CT transformation is carried out with the expected delay included, and the feedback coefficients are recomputed accordingly. With a return-to-zero pulse whose off time exceeds the delay, the delayed pulse still ends within its clock period, and retuning the coefficients alone can restore the NTF. With a non-return-to-zero pulse, the delayed pulse spills into the next period, and the extra direct path above is also needed.
• Direct Path Through the Last Integrator: To avoid a separate summing amplifier at the quantizer input, the direct path can be merged into the last integrator, for example by adding a resistor in series with its integrating capacitor, which adds a proportional term, a zero, to that stage's response.
• Deliberate Half-Period Delay: Many designs clock the DAC half a period after the quantizer and include that fixed delay in the loop design from the start. The quantizer then has a known, generous time to resolve, and the loop is designed around a fixed delay rather than an uncertain one.

Practical Design Considerations

When designing ELD compensation:

• Delay Estimation: Accurate estimation or simulation of total loop delay is essential for effective compensation
• Process Variation: Delay varies with process, voltage, and temperature, so compensation must be robust across operating conditions
• Trade-offs: Compensation paths add complexity, power consumption, and potential noise sources
• Verification: Time-domain simulation with realistic delay models is essential to verify stability

DAC Topologies

Several DAC architectures are used in CT-DS modulators:

• Current-Steering DAC: Switches current sources between the integrator input and a dummy load. Provides fast switching and good matching in modern CMOS processes. The output current is integrated directly by the loop filter.
• Resistive DAC: Uses switched resistors to create the feedback signal. Simpler than current steering but may have bandwidth limitations.
• Switched-Capacitor DAC: Employs charge transfer from capacitors to implement the feedback function. Can achieve excellent linearity through capacitor matching.
• Voltage-Mode DAC: Generates a voltage output that drives the input through a resistor. Commonly used in active RC implementations.

Pulse Shape Considerations

The temporal shape of the DAC output pulse significantly affects modulator behavior:

• Non-Return-to-Zero (NRZ): The DAC output maintains its value for the entire clock period. The most common choice, it delivers a given charge with the smallest peak amplitude and switches only when the output code changes, which gives it the lowest jitter sensitivity of the rectangular pulses. Its weakness is intersymbol interference: if the rising and falling edges are not identical, the error in each period depends on the previous code, and the result is signal-dependent distortion.
• Return-to-Zero (RZ): The DAC output returns to zero for part of each clock period. Because every pulse then has one rising and one falling edge whatever the data, unequal edges produce a code-independent error instead of intersymbol interference. The price is greater jitter sensitivity (see below) and, at a 50 percent duty cycle, twice the peak amplitude for the same charge, which raises the slew-rate demand on the first integrator. The duty cycle affects the equivalent gain and loop coefficients.
• Half-Delayed RZ (HRZ): A variant where the pulse occurs in the second half of the clock period. Its built-in half-period delay can be designed into the loop from the start, giving the quantizer up to half a period to resolve before the pulse begins.
• Exponential or Shaped Pulses: Some advanced designs use specifically shaped DAC pulses to optimize the NTF or reduce sensitivity to timing errors.

Multi-Bit DAC Considerations

Multi-bit quantization reduces quantization noise power but places stringent linearity requirements on the DAC:

• Unit Element Matching: Current source or capacitor mismatch directly causes DAC nonlinearity. Achieving 16-bit equivalent linearity requires unit-element matching on the order of 1 part in 2¹⁶ (roughly 0.0015%), which is impractical to obtain through device sizing alone in standard processes.
• Dynamic Element Matching (DEM): Randomizes the selection of unit elements to convert static mismatch into shaped noise. Various algorithms (data-weighted averaging, individual level averaging) offer different noise shaping characteristics.
• Segmentation: Dividing the DAC into coarse and fine segments can reduce the total number of elements while maintaining linearity for small signals.
• Calibration: Digital calibration can measure and compensate for element mismatches, improving static linearity without dynamic element matching overhead.

Clock Jitter Sensitivity

In CT-DS modulators, the feedback DAC is switched by the clock, and the charge it delivers is the integral of a waveform whose edges move with every clock timing error:

• Jitter Mechanism: Timing variations in the DAC switching instant change the charge delivered to the integrator, and the error enters at the input with no loop gain ahead of it to suppress it. For an NRZ DAC, each edge's error is proportional to the timing error multiplied by the step between consecutive output levels, which is why multi-bit feedback, with smaller steps, is far less jitter-sensitive than single-bit feedback. Jitter at the quantizer's sampling instant, by contrast, enters where quantization noise does and is shaped away by the loop.
• SNR Limitation: Clock jitter sets a limit on achievable SNR. Unlike the sampling-jitter limit of a Nyquist-rate converter, which tightens as the input frequency rises, this error is dominated by the large out-of-band quantization noise carried in the feedback waveform, so it depends mainly on the modulator's output spectrum rather than on the input frequency. Discrete-time modulators are less affected, because their switched-capacitor DACs transfer a charge that has settled before the clock edge.
• RZ vs NRZ Sensitivity: RZ DACs have two switching edges in every period (on and off), making them more sensitive to jitter than NRZ DACs, which switch at most once per period and only when the code changes
• Switched-Capacitor-Resistor (SCR) DAC: A switched-capacitor feedback element that reduces jitter sensitivity by defining the delivered charge with a capacitor and reference rather than a rectangular current pulse. Because the charge settles exponentially and is nearly complete before the clock edge, the transferred quantity is largely independent of the exact switching instant. The cost is a high initial current peak, which raises the slew-rate and linearity demands on the first integrator.
• FIR DAC Structures: A multi-tap FIR feedback DAC sums several delayed copies of the output, low-pass filtering the feedback waveform. The steps between consecutive levels shrink, and the jitter-induced error with them, but the FIR's delay and response must be compensated elsewhere in the loop.

Noise Transfer Function Design

The NTF determines how quantization noise is shaped across frequency:

• High-Pass Characteristic: The NTF must have a high-pass shape that attenuates noise in the signal band while allowing noise to pass at higher frequencies
• Aggressive Shaping Trade-offs: Steeper NTF slopes provide more in-band attenuation but increase out-of-band gain, risking quantizer overload
• NTF Zero Placement: Spreading the NTF zeros across the signal band, instead of stacking them all at DC, minimizes in-band integrated noise. For a second-order loop, the optimum pair of zeros sits at f_B/√3 and lowers in-band noise by about 3.5 dB; a third-order loop, with one zero at DC and a pair at f_B√(3/5), gains about 8 dB. In bandpass modulators, the zeros cluster around the center frequency.
• Out-of-Band Gain Constraint: Limiting the maximum NTF magnitude (to roughly 1.5 to 2 for single-bit quantizers) keeps large quantization errors from driving the loop into instability
• Pole Placement: The NTF poles set the out-of-band gain profile. Maximally flat (Butterworth-like) placement is a common default, while an inverse-Chebyshev NTF gives equiripple noise attenuation across the signal band.

Signal Transfer Function Considerations

While the NTF shapes noise, the STF affects how the input signal propagates to the output:

• Unity STF Designs: Many modulators target an STF of unity (0 dB, flat response) across the signal band, providing accurate signal reproduction
• STF Filtering: Some designs intentionally implement STF filtering to provide anti-aliasing or band-limiting as part of the modulator function
• STF Peaking: Feedforward (CIFF) loop filters in particular exhibit STF peaking beyond the edge of the signal band, which amplifies out-of-band interferers and can overload the quantizer
• Input Feed-In Paths: Extra input paths to the integrator inputs set the STF zeros without altering the NTF, which depends only on the loop from quantizer output back to quantizer input. They are the usual way to flatten the STF or tame the peaking of feedforward loops.
• Blocker Tolerance: In wireless receivers, the STF should attenuate strong out-of-band interferers to prevent quantizer overload

Optimization Techniques

Several approaches enable STF/NTF optimization:

• Pole-Zero Placement: Mathematical optimization algorithms can place poles and zeros to minimize in-band noise while respecting stability constraints
• CLANS Methodology: Closed-Loop Analysis of Noise-Shapers, developed by Kenney and Carley for multi-bit modulators, minimizes in-band noise while bounding the sum of the absolute values of the NTF impulse response, which caps the worst-case quantizer input and so guards against overload
• Schreier's Delta-Sigma Toolbox: Richard Schreier's MATLAB toolbox, also ported to Python, enables rapid exploration of NTF designs, coefficient synthesis, and simulation
• Numerical Optimization: Gradient-based or evolutionary algorithms can optimize coefficients for complex, multi-objective specifications

Stability Considerations

Delta-sigma modulators are nonlinear systems, and their stability cannot be guaranteed by linear analysis alone:

• Lee Criterion: An empirical rule for single-bit modulators holds that the loop is likely to be stable if the peak NTF magnitude stays below a limit quoted between 1.5 and 2, with 1.5 the usual design target. Multi-bit quantizers tolerate a considerably larger out-of-band gain.
• Root Locus Analysis: Examining how system poles move with varying quantizer gain provides insight into stability margins
• Describing Function Analysis: Treats the quantizer as a variable-gain element to approximate system behavior
• Time-Domain Simulation: Extensive simulation with various input amplitudes and frequencies remains the most reliable stability verification method

Benefits of Multi-Bit Quantization

Each additional bit of quantizer resolution provides significant advantages:

• 6 dB SNR Improvement per Bit: Each doubling of quantization levels reduces quantization noise power by approximately 6 dB
• Relaxed Loop Filter Requirements: Lower quantization noise power means less aggressive noise shaping is needed, simplifying loop filter design
• Improved Stability: A multi-bit quantizer has a well-defined gain and overloads less readily, so the linear model predicts the loop's behavior more accurately and the NTF can tolerate a larger out-of-band gain
• Lower Oversampling Ratio: Equivalent performance can be achieved at lower clock frequencies, reducing power consumption
• Lower Jitter Sensitivity: Smaller steps between consecutive feedback levels reduce the error that clock jitter causes in the DAC
• Reduced Idle Tones: A finer quantization error behaves more like random noise, which weakens the deterministic patterns that cause idle tones in single-bit modulators

Flash ADC Implementation

The multi-bit quantizer is typically implemented as a flash ADC:

• Comparator Array: 2^N − 1 comparators for an N-bit quantizer, so a 4-bit quantizer needs 15, with thresholds set by a reference ladder
• Speed Requirements: Comparators must resolve within the available time, which may be a small fraction of the clock period after accounting for loop delay
• Offset Tolerance: Comparator offsets enter the loop at the same point as quantization noise and are shaped with it, so the quantizer tolerates offsets that would be unacceptable in a stand-alone flash converter, provided they stay small enough not to disturb loop stability
• Metastability: Comparator decisions near threshold levels can be slow or incorrect, requiring careful design of regeneration time
• Encoding Logic: Commonly the thermometer code drives the unit-element DAC directly, through the DEM logic, so binary encoding sits outside the loop; it may use Gray coding or other bubble-tolerant encoding to guard against sparkle errors

Linearity Requirements

The primary challenge with multi-bit quantization is achieving adequate feedback DAC linearity:

• Direct Error Path: Unlike quantization noise, DAC nonlinearity errors are not shaped by the loop filter and appear directly at the output
• Matching Requirements: For 16-bit equivalent linearity, unit-element matching must be on the order of 1 part in 2¹⁶ (roughly 0.0015%), which is typically not achievable through sizing alone in standard IC processes
• Solutions: Dynamic element matching, digital calibration, or mismatch-shaping techniques are essential for high-resolution multi-bit designs

Basic Principle

DEM works by randomizing or systematically rotating the selection of unit elements used to create each DAC output level:

• Element Selection Problem: For a DAC with M unit elements producing output level K, there are multiple ways to choose which K elements to activate
• Mismatch Effect: If the same elements are always selected for a given code, mismatches cause static nonlinearity
• Randomization: By varying the element selection, mismatch errors are spread across different output codes and times, converting static errors to noise
• Noise Shaping: Advanced DEM algorithms shape the mismatch-induced noise to high frequencies where it is filtered by the decimator

DEM Algorithms

Several DEM algorithms have been developed with different characteristics:

• Random Selection: Elements are chosen randomly for each output code. Simple to implement but provides no noise shaping; mismatch noise has a white spectrum.
• Data-Weighted Averaging (DWA): For a code of K, selects the next K elements after those used in the previous cycle, rotating a pointer through the array so that every element is used equally often; this provides first-order noise shaping of mismatch errors. Highly effective but can exhibit tonal behavior with periodic inputs.
• Individual Level Averaging (ILA): Maintains separate selection pointers for each output level, providing robust noise shaping with reduced tonal artifacts.
• DWA Variants: Bidirectional and rotated forms of DWA alter the rotation pattern to break up the tones that plain DWA can produce.
• Tree-Structured DEM: Organizes elements hierarchically, enabling efficient implementation for large numbers of elements.
• Segmented DEM: Applies different DEM strategies to coarse and fine DAC segments, optimizing for each section's requirements.

Implementation Considerations

Practical DEM implementation requires careful design:

• Logic Delay: The element selection logic adds delay to the feedback path, potentially exacerbating excess loop delay issues
• Power Consumption: DEM logic consumes power proportional to the number of elements and the algorithm complexity
• Memory Requirements: State information for element rotation must be maintained across clock cycles
• Tone Avoidance: Some algorithms add dithering or randomization to prevent tonal artifacts from periodic inputs
• Uniform Errors: DEM does not correct for systematic errors that affect all elements equally

Mismatch Shaping

Advanced DEM algorithms can shape mismatch noise similarly to how the loop filter shapes quantization noise:

• First-Order Shaping: DWA provides first-order (20 dB/decade) high-pass shaping of mismatch noise
• Higher-Order Shaping: More complex algorithms can achieve second-order or higher shaping, further attenuating in-band mismatch noise
• Trade-offs: Higher-order shaping requires more complex logic and may have longer latency
• Dependence on Oversampling: Randomization alone lowers in-band mismatch error power by only 3 dB per doubling of the oversampling ratio, first-order shaping by about 9 dB, and second-order shaping by about 15 dB. The benefit of DEM is therefore large at high oversampling ratios and modest in wideband designs that oversample by 8 to 16.

Coefficient Calibration

CT loop filter coefficients drift with process variations and must be calibrated:

• Replica-Based Tuning: A replica RC or Gm-C circuit is compared against a stable reference (crystal oscillator) to generate correction signals
• Background Calibration: Correlation-based algorithms can detect coefficient errors from the modulator output during normal operation
• LMS Adaptation: Least-mean-squares algorithms can adaptively adjust digital compensation filters to correct for coefficient errors
• Pilot Tone Injection: Small out-of-band test signals can be used to measure and track loop filter response

DAC Mismatch Calibration

Static DAC mismatch can be measured and corrected digitally:

• Foreground Calibration: During a dedicated calibration phase, each DAC element is measured by observing its effect on the modulator output. Correction factors are stored and applied during normal operation.
• Background Calibration: Element errors are estimated during normal operation using statistical techniques, avoiding the need for dedicated calibration time.
• Chopping: Periodically inverting the sign of specific elements allows their errors to be distinguished and corrected.
• Digital Correction: Once element errors are known, digital filtering can remove their effects from the output, or the DEM algorithm can account for them.

ELD Compensation Calibration

Excess loop delay varies with operating conditions and may require adaptive compensation:

• Delay Measurement: The effective loop delay can be estimated by observing the modulator's frequency response or transient behavior
• Adaptive Compensation: Compensation parameters can be adjusted based on delay measurements to maintain optimal stability margins
• Temperature Tracking: Since delay varies with temperature, continuous or periodic recalibration may be necessary

System-Level Calibration

Complete CT-DS ADC systems may employ multiple calibration techniques simultaneously:

• Power-Up Calibration: Initial calibration when the system starts, measuring and correcting major errors
• Continuous Background Calibration: Ongoing correction that tracks slow variations during operation
• Digital Post-Processing: Filters and algorithms in the digital domain that correct residual errors
• Built-In Self-Test: Automated testing capabilities that verify calibration effectiveness

CT/DT Hybrid Modulators

These designs use continuous-time input stages with discrete-time back-end processing:

• CT Front-End Benefits: The continuous-time input stage provides inherent anti-aliasing and low-power operation
• DT Back-End Advantages: Switched-capacitor stages in later positions of the loop are less sensitive to component variations and can provide precise coefficient matching
• Interface Considerations: The transition between CT and DT domains requires careful design to avoid sampling artifacts
• Flexibility: This architecture allows designers to choose the optimal implementation for each stage based on its specific requirements

Delta-Sigma with SAR Quantizer

Replacing the flash quantizer with a successive approximation register (SAR) ADC offers several advantages:

• Power Efficiency: Above a few bits, SAR quantizers typically consume less power than flash ADCs of the same resolution, because they need only one comparator
• Resolution Flexibility: The number of quantization levels can be easily adjusted by changing the number of SAR cycles
• Timing Considerations: The multiple cycles required for SAR conversion must be accommodated within the loop timing budget
• DAC Reuse: The SAR's internal DAC can potentially be shared with the feedback DAC function

VCO-Based Delta-Sigma

Voltage-controlled oscillator (VCO) based modulators use frequency modulation for quantization:

• VCO as Integrator: The VCO's phase integration property provides inherent first-order noise shaping
• Digital Counting: The VCO frequency is measured by counting edges over a sampling period
• Scaling Advantages: VCO-based designs can leverage the improved transistor speed in advanced CMOS nodes
• Linearity Challenges: VCO nonlinearity requires calibration or closed-loop correction
• Multi-Phase Operation: Using multiple VCO phases can improve resolution and reduce quantization noise

Time-Interleaved CT-DS Modulators

Interleaving multiple CT-DS channels extends bandwidth beyond single-modulator limits:

• Bandwidth Extension: N interleaved channels provide N times the effective sampling rate
• Mismatch Sensitivity: Gain, offset, and timing mismatches between channels create spurious tones that must be calibrated
• Complexity: Each channel requires its own modulator, significantly increasing design complexity and area
• Applications: Explored mainly for wideband receivers and instrumentation whose bandwidth a single modulator cannot reach

Incremental Delta-Sigma

Incremental operation resets the modulator between conversions, combining delta-sigma noise shaping with Nyquist-rate conversion characteristics:

• Reset Operation: All integrators are reset to initial conditions before each conversion
• Finite Conversion Time: Each sample is converted independently over a fixed number of clock cycles
• Simplified Digital Filter: Because each conversion starts from a known state, the filter only has to combine a finite block of output samples. For a first-order modulator it reduces to a counter that accumulates the output bits; higher-order incremental converters use a cascade of accumulators or a short sinc filter, cleared together with the modulator at each reset.
• Applications: Particularly suited for multiplexed sensor interfaces where each channel needs independent conversion

System-Level Design

The design process typically begins at the system level:

1. Specification Analysis: Define resolution, bandwidth, power budget, and other requirements
2. Architecture Selection: Choose modulator order, quantizer bits, and oversampling ratio based on specifications
3. NTF Synthesis: Design the noise transfer function to meet in-band noise requirements
4. DT Prototype: Create a discrete-time behavioral model and verify performance
5. DT-to-CT Transformation: Convert to continuous-time with appropriate DAC pulse shape
6. Coefficient Mapping: Translate coefficients to component values (resistors, capacitors, transconductances)

Behavioral Simulation

Behavioral models enable rapid exploration and verification:

• Ideal Simulation: Verify NTF/STF and stability with ideal components
• Non-Ideal Models: Include amplifier finite gain, bandwidth, slew rate, and noise
• Timing Effects: Model excess loop delay, clock jitter, and DAC timing
• DAC Nonlinearity: Include element mismatch and DEM algorithm effects
• Statistical Analysis: Monte Carlo simulation of component variations

Circuit-Level Design

Detailed transistor-level implementation follows behavioral verification:

• Integrator Design: Operational amplifier or transconductor sizing for required bandwidth, gain, and noise
• Quantizer Design: Comparator design for speed and metastability handling
• DAC Design: Current source matching, switching speed, and jitter sensitivity
• Bias and Reference: Stable bias generation and reference voltage distribution
• Layout Considerations: Matching, shielding, and substrate coupling

Verification and Testing

Comprehensive verification ensures design correctness:

• Transient Simulation: Time-domain simulation with realistic stimuli
• Stability Verification: Large signal and corner case analysis
• Noise Analysis: AC noise simulation and integration
• Post-Layout Simulation: Include parasitic effects from physical layout
• Silicon Measurement: Test chip verification with FFT-based SNR/SNDR measurement