Electronics Guide

Thermal Energy and Carrier Statistics

Thermal energy, characterized by the product of Boltzmann's constant and absolute temperature (kT), sets the energy scale for electronic processes in semiconductors. Divided by the electronic charge it becomes the thermal voltage kT/q, which appears throughout semiconductor device equations. The thermal voltage is 25.85 mV at 300 K and 25.69 mV at 298.15 K, which is 25 degrees Celsius. Much of the analog literature rounds the figure to 26 mV; the distinction matters only when a design leans on the absolute value rather than on a ratio.

The intrinsic carrier concentration in a semiconductor follows the relationship:

n_i = √(N_cN_v) exp(−E_g / 2kT)

Where N_c and N_v are the effective densities of states in the conduction and valence bands, and E_g is the bandgap energy. The factor of two in the exponent is not incidental. It follows from the law of mass action, in which the product n_i² carries the full bandgap exponential, so n_i itself carries half of it.

For silicon the result is a remarkably small number. Modern measurements place n_i near 1 × 10¹⁰ per cubic centimeter at 300 K, against roughly 5 × 10²² silicon atoms per cubic centimeter. Older texts quote 1.45 × 10¹⁰, a value later measurements revised downward. The exponential dependence causes the intrinsic carrier concentration to roughly double for every 8 to 10 degrees Celsius of temperature rise near room temperature. While this effect is negligible in heavily doped regions, where the carrier concentration is fixed by the dopants, it becomes significant in lightly doped and depleted regions and governs the temperature behavior of leakage currents.

The Fermi-Dirac distribution function, which governs carrier occupation of energy states, also depends on temperature. Higher temperatures broaden the distribution, allowing carriers to occupy higher energy states and affecting transport properties throughout the device.

Temperature Coefficient Basics

Temperature coefficients quantify how parameters change with temperature. The most common form is the fractional temperature coefficient (TC), expressed in parts per million per degree Celsius:

TC = (1/X)(dX/dT) × 10⁶

Where X is the parameter value at a reference temperature. A resistor with a TC of +100 parts per million per degree Celsius increases by 0.01 percent for each degree Celsius of temperature rise.

For some parameters, particularly semiconductor junction voltages, an absolute temperature coefficient is more appropriate:

TC = dX/dT

Here the units are volts or millivolts per degree Celsius rather than parts per million. The base-emitter voltage of a silicon bipolar transistor, for example, has a temperature coefficient of approximately −2 mV per degree Celsius at constant collector current, largely independent of the initial voltage value. That condition is the usual omission, and it is not a technicality. Held at constant base current instead, the collector current climbs with temperature as the current gain rises, and the measured coefficient becomes noticeably more negative.

Temperature coefficients themselves can vary with temperature, leading to second-order effects that become important over wide temperature ranges. Precision components often specify both first-order (linear) and second-order (parabolic) temperature coefficients.

Junction Voltage Temperature Dependence

The forward voltage of a p-n junction decreases with increasing temperature at a rate of approximately 2 mV per degree Celsius for silicon, again at constant forward current. This behavior arises from the temperature dependence of the saturation current, which climbs steeply, working against the thermal voltage kT/q, which rises only in proportion to absolute temperature.

The diode equation gives the junction current as:

I = I_S[exp(qV / nkT) − 1]

Where I_S is the saturation current and n is the ideality factor. The saturation current is the strongly temperature-dependent term, rising by orders of magnitude across a typical operating range, and it is the reason the forward voltage falls. To sustain a fixed current through a junction that conducts far more readily, less forward bias is needed.

More precisely, the junction voltage temperature coefficient at constant current is:

dV_BE/dT = (V_BE − V_G0 − ηkT/q) / T

Where V_G0 is the bandgap voltage extrapolated to zero temperature, approximately 1.2 V for silicon, and η is the exponent in the power-law prefactor of the saturation current, I_S ∝ T^η exp(−qV_G0 / kT). That exponent gathers the temperature dependence of minority-carrier mobility and of the effective densities of states. It is process dependent and usually falls between about 2.5 and 4. It does not, as is sometimes stated, represent the variation of the bandgap itself, which is already absorbed into V_G0.

Putting numbers to the expression makes the familiar result concrete. At V_BE = 0.65 V, T = 300 K and η = 3, the first term contributes −1.83 mV per degree Celsius and the ηkT/q term a further −0.26 mV per degree Celsius, for a total near −2.09 mV per degree Celsius. Note also that the coefficient depends on V_BE itself, so a junction biased at a lower current drifts faster.

This temperature coefficient has profound implications for analog circuits:

• Transistor biasing: Base-emitter voltages decrease with temperature, changing collector currents in fixed-bias configurations
• Voltage references: Simple diode references drift substantially; compensation techniques are essential
• Current sources: Voltage-programmed current sources exhibit significant temperature variation
• Comparator thresholds: Reference voltages derived from junctions drift with temperature

Bipolar Transistor Parameters

Bipolar transistors exhibit several temperature-dependent parameters beyond the base-emitter voltage:

Current gain (β): Current gain typically increases with temperature at low to moderate collector currents, because emitter injection efficiency improves and recombination in the base and in the emitter-base space-charge region becomes relatively less important. The temperature coefficient is commonly in the range of +0.5 to +1 percent per degree Celsius. At high currents, high-level injection effects can reverse this trend.

Saturation voltage (V_CE(sat)): Increases slightly with temperature, chiefly because the ohmic resistances of the collector and base regions rise as mobility falls.

Transition frequency (f_T): Decreases with temperature because carrier transit times increase as the minority-carrier diffusion constant falls.

Collector-base breakdown voltage: Avalanche breakdown voltage increases with temperature, because stronger lattice scattering shortens the carrier mean free path and suppresses impact ionization. Zener breakdown, which dominates below roughly 5 V, moves the other way, which is why a reverse-biased junction near 5 to 6 V can be made almost temperature independent.

For matched transistor pairs, the difference in base-emitter voltages at unequal collector currents provides a proportional-to-absolute-temperature (PTAT) voltage:

ΔV_BE = (kT/q) ln(I_C1 / I_C2)

This form assumes the two transistors are matched and of equal emitter area. In the general case the argument of the logarithm is the ratio of collector current densities, so an emitter-area ratio serves just as well as a current ratio. The PTAT voltage increases linearly with absolute temperature and forms the basis for bandgap voltage references and temperature sensors. Its great practical merit is that it depends on a ratio and on fundamental constants rather than on absolute device parameters, so it survives process variation.

MOSFET Parameters

MOSFETs exhibit temperature behavior dominated by two competing mechanisms: threshold voltage variation and mobility degradation.

• Threshold voltage: Decreases with temperature at approximately −1 to −4 mV per degree Celsius in silicon MOSFETs, depending on doping levels and oxide thickness. This decrease arises from the temperature dependence of the Fermi potential and the increased intrinsic carrier concentration.
• Carrier mobility: Decreases with temperature as lattice vibrations scatter carriers more strongly. Simple acoustic-phonon theory predicts a dependence of T^−3/2, but measurement shows silicon falling faster than that: the lattice-limited mobility follows roughly T^−2.4 for electrons and T^−2.2 for holes. Inversion-layer mobility in a MOSFET is degraded further by surface scattering and follows a gentler exponent, typically between 1.5 and 2. This mobility reduction is the dominant effect at high gate overdrive voltages.

The drain current in saturation combines these effects:

I_D = (μC_oxW / 2L)(V_GS − V_th)²

At low overdrive voltages, the threshold voltage reduction causes current to increase with temperature. At high overdrive voltages, the mobility reduction dominates, causing current to decrease with temperature. At a specific bias point called the zero-temperature-coefficient (ZTC) point, these effects cancel and the current is temperature independent. Differentiating the square-law expression and setting the result to zero locates it:

V_GS − V_th = 2T |dV_th/dT| / m

Where m is the exponent in μ ∝ T^−m. At 300 K, with a threshold drifting at 2 mV per degree Celsius and m near 2, the ZTC overdrive comes out around 0.6 V, and values from a few hundred millivolts up to about a volt are usual across processes. Discrete power MOSFETs reach the ZTC point at a gate-source voltage of several volts, simply because their thresholds are high. Operating at this point provides first-order temperature stability but requires careful bias design, and the point itself shifts with process corner.

Which side of the ZTC point a device sits on has a direct practical consequence. Above it, drain current falls as the die heats, so paralleled devices share current willingly. Below it, in the low-overdrive region favored by efficiency-driven designs, current rises with temperature and paralleled devices can hog current, the same instability long familiar from bipolar output stages.

Subthreshold operation: In weak inversion, MOSFET current varies exponentially with gate voltage, similar to bipolar transistors. The subthreshold swing, the gate-voltage change required to alter the drain current by one decade, has a lower limit for any device that works by thermionic emission over the source barrier:

S = (kT/q) ln(10)

This evaluates to 59.5 mV per decade at 300 K, the figure usually quoted as 60 mV. Real devices add a body-effect factor of roughly 1.2 to 1.5, giving 70 to 90 mV per decade. Because the limit scales with absolute temperature, it widens to 79 mV per decade at 125 degrees Celsius, so the swing degrades exactly where off-state leakage is already worst.

JFET Characteristics

Junction field-effect transistors (JFETs) offer some advantages for temperature-stable design:

Pinch-off voltage: The JFET pinch-off voltage has a negative temperature coefficient, typically −2 to −3 mV per degree Celsius, since it is set by a reverse-biased gate junction whose built-in potential falls with temperature much as a forward junction voltage does.

Zero-bias drain current (I_DSS): Decreases with temperature due to mobility degradation, typically at −0.5 to −1 percent per degree Celsius.

• Transconductance: Decreases with temperature as mobility decreases.
• Gate leakage: The reverse-biased gate junction leaks, and that leakage doubles for roughly every 10 degrees Celsius. This sets the practical limit on JFET input stages in electrometer service, where a bias current of a few picoamperes at room temperature becomes nanoamperes at 125 degrees Celsius.

Like MOSFETs, JFETs exhibit a ZTC point where drain current is temperature independent. This point occurs where the rising overdrive produced by the falling pinch-off voltage exactly offsets the falling mobility. Operating at the ZTC bias provides excellent temperature stability for current sources and input stages, though it fixes the drain current and so removes one degree of design freedom.

Bandgap Temperature Dependence

The silicon bandgap measures about 1.12 eV at 300 K and 1.17 eV extrapolated to absolute zero. Over the practical temperature range it falls almost linearly:

E_g(T) ≈ E_g(T₀) − a(T − T₀)

Where the local slope a is about 0.25 to 0.27 meV per kelvin near room temperature. One point deserves care: extrapolating that local slope back to zero temperature gives roughly 1.20 eV, not the true zero-temperature gap of 1.17 eV, because the real curve flattens below about 100 K. It is the extrapolated figure, near 1.2 V, that appears as V_G0 in bandgap-reference theory, which is why a bandgap reference settles near 1.2 V rather than 1.17 V.

More accurate models include quadratic and higher-order terms. The Varshni formula is the standard empirical fit:

E_g(T) = E_g(0) − αT² / (T + β)

Where α and β are material-specific constants. For silicon the customary values are E_g(0) = 1.17 eV, α = 4.73 × 10⁻⁴ eV per kelvin and β = 636 K, which return 1.12 eV at 300 K. The formula captures the behavior accurately across wide temperature ranges, particularly at low temperatures where the linear model fails.

The bandgap temperature dependence directly affects junction voltages, leakage currents, and the reference voltage in bandgap circuits. Even well-designed bandgap references exhibit some residual temperature dependence due to bandgap curvature effects.

Bandgap Voltage Reference Principle

Bandgap voltage references exploit the complementary temperature coefficients of junction voltage (negative) and thermal voltage (positive) to achieve temperature stability. The basic principle sums a V_BE voltage, which is complementary to absolute temperature, with a properly scaled PTAT voltage:

V_ref = V_BE + K(kT/q) ln(N)

Where K is a gain factor and N is the ratio of collector current densities in two transistors, obtained from an emitter-area ratio, a current ratio, or both together. Choosing K appropriately makes the positive and negative temperature slopes cancel at the chosen reference temperature.

The required gain follows directly from the numbers. With N = 8, a common array ratio, the PTAT slope is (k/q) ln(8) = 0.179 mV per degree Celsius, so cancelling a V_BE slope of −2 mV per degree Celsius calls for K near 11. The resulting reference voltage is 0.65 V plus about 0.60 V of PTAT, or roughly 1.25 V. That this lands close to the extrapolated bandgap is not coincidental: cancelling the slope of V_BE necessarily drives the sum toward V_G0, which is what the derivative expression above already implies.

The cancellation is first-order only. The two slopes are matched at one temperature, but V_BE is not exactly linear in T, and the residual η(kT/q) ln(T) term leaves a bow of a few millivolts across a wide temperature range. First-order bandgap references therefore achieve temperature coefficients of a few tens of parts per million per degree Celsius, limited by that curvature together with process variation and resistor mismatch. Higher performance requires explicit curvature compensation.

Curvature Compensation Techniques

The residual temperature dependence of bandgap references arises from the nonlinear relationship between V_BE and temperature. Several techniques compensate for this curvature:

• Squared PTAT compensation: Adding a component proportional to T² cancels the curvature term. This is implemented by squaring a PTAT signal using analog multipliers or translinear circuits.
• Piecewise-linear compensation: Different correction slopes are applied in different temperature ranges using temperature-dependent switching circuits.
• Resistor ratio temperature compensation: Using resistors with different temperature coefficients to create a correction term that varies nonlinearly with temperature.
• Base-emitter voltage summation: Combining V_BE voltages from transistors operating at different current densities, or one biased at a PTAT current against one biased at a temperature-independent current, generates a difference that is precisely the curvature term and can be subtracted from the output.

Curvature-compensated references reach temperature coefficients below 10 parts per million per degree Celsius over the military temperature range, −55 to +125 degrees Celsius. The most stable references available, generally buried-Zener rather than bandgap parts, specify a few parts per million per degree Celsius, at the cost of a higher output voltage, a larger supply requirement, and appreciably more current.

Physical Mechanisms

Carrier mobility depends on scattering mechanisms that impede carrier motion. The dominant mechanisms have different temperature dependencies:

• Phonon (lattice) scattering: At and above room temperature, thermal vibrations of the crystal lattice scatter carriers. Acoustic-phonon theory alone predicts a mobility falling as T^−3/2, but measurements on silicon, where optical-phonon and intervalley scattering also contribute, give a steeper T^−2.4 for electrons and T^−2.2 for holes.
• Ionized impurity scattering: Carriers scatter from ionized dopant atoms. This mechanism matters most at low temperatures and in heavily doped regions, and its contribution to mobility rises roughly as T^3/2, because faster-moving carriers are deflected less as they pass each ion. Since the two mechanisms pull in opposite directions, lightly doped silicon shows a mobility maximum at a temperature well below room temperature.
• Surface scattering: In MOSFETs, carriers in the inversion layer scatter from the rough Si-SiO₂ interface. Surface roughness scattering depends strongly on the transverse field but is nearly temperature independent, so at high gate overdrive it dilutes the temperature dependence of the total mobility.

The overall mobility combines these mechanisms according to Matthiessen's rule:

1/μ_total = 1/μ_phonon + 1/μ_impurity + 1/μ_surface

The rule is an approximation that holds only when the mechanisms are independent, but it is accurate enough for design work. At room temperature and above, phonon scattering typically dominates, leading to the familiar inverse-temperature dependence of mobility.

Impact on Device Parameters

Mobility reduction with temperature affects multiple device parameters:

Transconductance (g_m): The two device families behave differently here, and conflating them is a common error. A bipolar transistor has g_m = qI_C/kT, which contains no mobility term at all: at constant collector current it falls in simple inverse proportion to absolute temperature, by about 25 percent from 25 to 125 degrees Celsius. A field-effect transistor at constant drain current has g_m = √(2μC_ox(W/L)I_D), so it follows the square root of mobility and falls more gently than mobility itself. Either way, voltage gain and bandwidth shrink at elevated temperatures.

On-resistance (R_DS(on)): In power MOSFETs, on-resistance is inversely proportional to mobility. For silicon devices it rises by roughly 1.5 to 2 times between 25 and 125 degrees Celsius, and high-voltage parts, whose resistance is dominated by the lightly doped drift region, change the most. Datasheets give a normalized curve for this, and conduction-loss calculations must use the hot value rather than the headline figure at 25 degrees Celsius.

Transit frequency (f_T): Device speed depends on carrier transit times, which increase as the diffusion constant falls. High-frequency performance degrades at elevated temperatures.

Noise: The dominant effect is direct rather than mobility-mediated. Johnson-Nyquist noise power is proportional to absolute temperature, so a resistor's noise voltage, √(4kTRB), grows only as the square root of absolute temperature: about 15 percent from 25 to 125 degrees Celsius. Shot noise in junctions tracks the bias current, and flicker noise, often modeled as mobility fluctuation, varies by process rather than following any general rule.

For analog circuits, the mobility temperature dependence means that gain, bandwidth, and slew rate all decrease at high temperatures. Designs must ensure adequate performance at the maximum operating temperature.

Design Implications

Several design strategies accommodate mobility variations:

• Margin allocation: Specify circuit performance at maximum temperature, accepting overdesign at room temperature
• Bias current scaling: Increase bias current at high temperature to maintain transconductance; PTAT bias currents naturally provide this
• ZTC biasing: Operate MOSFETs and JFETs at the zero-temperature-coefficient point where mobility and threshold variations cancel
• Gain-bandwidth product consideration: Account for reduced bandwidth at elevated temperatures in stability analysis

Physical Origin

MOSFET threshold voltage depends on several temperature-dependent factors:

• Fermi potential: The Fermi level position relative to the intrinsic level sets both the surface potential required for inversion and the depletion charge term. As temperature increases, the intrinsic carrier concentration rises and the Fermi potential falls, which lowers both terms together.
• Work function difference: The work function difference between gate and semiconductor has a weak temperature dependence.
• Fixed oxide charge: Oxide charges are relatively temperature independent, but their effect on threshold voltage changes as other terms vary.

The dominant contribution comes from the Fermi potential variation, giving threshold voltage temperature coefficients typically between −1 and −4 mV per degree Celsius for silicon MOSFETs. The magnitude grows with substrate doping and with oxide thickness, so an older thick-oxide, heavily doped process drifts more than a modern thin-oxide one.

Impact on Circuit Operation

Threshold voltage variation affects circuits in several ways:

• Current source variation: In a simple current mirror with fixed gate bias, the threshold voltage shift changes the gate overdrive and thus the output current. A threshold falling at 2 mV per degree Celsius against a gate overdrive of 200 mV raises the overdrive by 1 percent per degree Celsius and, because saturation current follows the square of the overdrive, raises the current by about 2 percent per degree Celsius. Falling mobility gives back roughly 0.7 percent per degree Celsius, leaving a net rise near 1.3 percent per degree Celsius. Across a 100 degree Celsius span that is not a small correction.
• Amplifier operating points: Bias voltages designed for a specific threshold voltage may leave insufficient headroom or drive transistors into the triode region at temperature extremes.
• Logic thresholds: In analog circuits using MOSFETs as switches or in comparators, threshold variations shift switching points.
• Subthreshold leakage: Below threshold, current increases exponentially as threshold voltage decreases, significantly increasing off-state currents at elevated temperatures.

Compensation Approaches

Several techniques mitigate threshold voltage temperature dependence:

• Self-biased structures: Circuits where the gate voltage tracks threshold variations maintain consistent overdrive across temperature
• Current-source biasing: Forcing a fixed current through the transistor adjusts V_GS automatically to compensate for threshold shifts
• Matched differential pairs: When both transistors in a differential pair experience the same threshold shift, common-mode rejection eliminates the effect on differential operation
• Body biasing: Adjusting substrate bias with temperature can compensate for threshold variations
• ZTC biasing: Operating at the zero-temperature-coefficient point inherently compensates for threshold variations

Junction Leakage

Reverse-biased p-n junctions conduct a small leakage current that increases exponentially with temperature. The dominant mechanisms include:

Diffusion current: Minority carriers generated within a diffusion length of the junction are swept across by the junction field. This component is proportional to the square of the intrinsic carrier concentration, so it rises very steeply with temperature, roughly doubling for every 5 degrees Celsius:

I_diffusion ∝ n_i² ∝ T³ exp(−E_g / kT)

In practice, the reverse leakage of a silicon junction is usually generation-limited near room temperature, so it follows a gentler rule of thumb than the diffusion term alone: it doubles for roughly every 10 degrees Celsius, or about 7 percent per degree.

• Generation current: Carriers thermally generated within the depletion region also contribute to leakage. This component is proportional to n_i rather than to its square, so its temperature dependence is much weaker than that of the diffusion current. Generation current dominates the reverse leakage of silicon junctions at room temperature and below, which is why the practical doubling interval is nearer 10 degrees Celsius than 5. The crossover matters: at high enough temperature the diffusion term overtakes the generation term and the doubling interval tightens toward 5 degrees Celsius.
• Surface leakage: Current flowing along semiconductor surfaces depends on surface condition and contamination, with variable temperature dependence. It is the component most sensitive to package moisture and to ionic residue from assembly, and the one least well predicted by any model.

For a typical small-signal silicon junction, reverse leakage might be about 1 nA at 25 degrees Celsius, rising to roughly 100 nA at 85 degrees Celsius and to the order of 1 microampere at 125 degrees Celsius. This steep increase has profound implications for circuit design at elevated temperatures: a leakage current that is negligible against a 1 microampere signal at room temperature is comparable to it at the top of the range.

MOSFET Subthreshold Leakage

When a MOSFET is nominally off (V_GS < V_th), subthreshold conduction still allows current to flow. This leakage current increases exponentially with temperature due to two effects:

• Threshold voltage reduction: A lower threshold at high temperature means a less negative (V_GS − V_th) in subthreshold, exponentially increasing current.
• Subthreshold slope degradation: The subthreshold swing, in millivolts per decade of current, increases with temperature, so the gate turns the channel off less completely.

Combined, these effects typically increase subthreshold leakage by two to three orders of magnitude between 25 and 125 degrees Celsius, and by more in devices with low thresholds. Modern submicron MOSFETs, whose thresholds are scaled down along with the supply, are particularly susceptible.

For analog circuits, subthreshold leakage can discharge sample-and-hold capacitors, create offset currents in high-impedance nodes, and contribute to standby power dissipation.

Gate Leakage

In modern processes with thin gate oxides, quantum-mechanical tunneling allows current to flow through the gate dielectric. Gate leakage increases with temperature, though far less dramatically than junction leakage, because tunneling is set chiefly by barrier height and oxide thickness rather than by thermal generation:

• Direct tunneling: Dominant in the thinnest oxides, with weak temperature dependence.
• Fowler-Nordheim tunneling: Occurs at higher oxide fields, with stronger temperature dependence.
• Trap-assisted tunneling: Defects in the oxide provide intermediate states for tunneling, and because carriers must be thermally excited into and out of those traps, this component carries the strongest temperature dependence of the three. It also grows as the oxide accumulates damage over service life.

Gate leakage is particularly problematic in analog circuits because it flows directly into high-impedance input nodes, creating offset voltages and discharging integration capacitors. High-permittivity gate dielectrics were introduced in advanced CMOS largely to suppress it.

Design Countermeasures

Several strategies mitigate leakage effects at elevated temperatures:

• Larger bias currents: Ensure signal currents substantially exceed worst-case leakage currents at maximum temperature
• Shorter hold times: Reduce the time that capacitors must hold charge in sample-and-hold circuits
• Leakage compensation: Use matched dummy structures to cancel leakage currents
• Guarding: Surround sensitive nodes with guard rings at the same potential to intercept leakage currents
• Larger transistors: In some cases, using larger transistor geometries reduces leakage density
• Process selection: Choose processes optimized for low leakage when high-temperature operation is required

Thermal Resistance and Temperature Rise

Self-heating is characterized by thermal resistance, the temperature rise per unit power dissipation:

ΔT = P_dissR_th

Where R_th is the thermal resistance from junction to ambient, or to another named reference point, in degrees Celsius per watt. Thermal resistance depends on die size, packaging, heat sinking, and airflow. Datasheet figures for junction-to-ambient resistance are measured on a specified test board and rarely apply unchanged to a real assembly; junction-to-case figures are more transferable.

For integrated circuits, different structures on the same die may have different local temperatures due to power distribution and thermal gradients. A high-power output stage may be significantly hotter than a precision reference circuit on the same chip.

Self-heating is particularly significant in:

• Power devices: High currents create substantial power dissipation in output stages and regulators
• Small packages: Limited thermal paths increase thermal resistance
• SOI devices: The buried oxide layer, whose thermal conductivity is roughly two orders of magnitude below that of silicon, impedes heat flow and raises local temperature
• High-frequency circuits: Dynamic power dissipation adds to static dissipation

Impact on Device Characteristics

Self-heating modifies device behavior in several ways:

• Output characteristics: In a MOSFET, self-heating reduces drain current at high V_DS and high I_D because the temperature rise decreases mobility. The output curves may show negative slope regions where increased V_DS reduces I_D through self-heating.
• Thermal time constants: Self-heating spans a wide range of time scales. The die itself responds in microseconds to milliseconds, while package, board, and heatsink follow over seconds to minutes. Pulsed measurements exploit that separation to extract intrinsic device behavior free of thermal effects.
• Matching: In matched transistor pairs, unequal power dissipation creates temperature differences that degrade matching. A difference of only 0.1 degrees Celsius between the two halves of a bipolar differential pair produces about 200 microvolts of offset, larger than the random offset of a well-laid-out pair. This is why thermal symmetry is a layout requirement rather than a refinement.
• Stability: The delayed response of temperature to power changes introduces phase shifts in feedback loops. In high-power amplifiers this appears as thermal distortion, or memory distortion, at frequencies below a few hundred hertz.

Modeling Self-Heating

Accurate circuit simulation requires models that include self-heating effects:

• Lumped thermal model: A simple thermal resistance and capacitance represent heat flow from junction to ambient. The thermal RC time constant models the dynamics of temperature response.
• Multi-node thermal networks: For more accuracy, multiple thermal nodes represent different parts of the device and package, connected by thermal resistances. Cauer networks mirror the physical structure; Foster networks fit the measured response and are what datasheet transient thermal impedance curves usually encode.
• Electrothermal simulation: Couples electrical and thermal simulation iteratively, allowing accurate prediction of self-heating effects in complex circuits. Compact device models intended for power and SOI work expose a thermal node for exactly this purpose.

Model parameters are extracted from measurements at different power levels and pulse conditions, or from thermal simulations of the physical structure.

Design Strategies

Several approaches mitigate self-heating problems:

• Thermal symmetry: Place matched devices symmetrically relative to heat sources so both experience the same temperature
• Thermal isolation: Physically separate precision circuits from power-dissipating sections
• Distributed power: Spread power dissipation across larger areas to reduce local heating
• Common-centroid layout: Interleave matched devices to average out thermal gradients
• Dummy devices: Add non-functional devices to balance thermal environments
• Adequate heat sinking: Reduce overall thermal resistance to minimize junction temperature rise

Conditions for Thermal Runaway

Thermal runaway sets in when the rate at which dissipation grows with junction temperature exceeds the rate at which the thermal path can carry heat away:

dP/dT > 1/R_th

If power increases faster with temperature than heat can be removed, temperature rises uncontrollably. The criterion also shows why a better heatsink, which lowers R_th and so raises the right-hand side, is a genuine cure rather than a palliative.

Several situations are particularly susceptible:

• Bipolar transistors in common-emitter configuration: With fixed base voltage, collector current increases with temperature as V_BE falls, increasing power. The positive temperature coefficient of current gain compounds the effect. A class AB audio output stage biased from a fixed voltage is the classic example, which is why its bias generator is mounted in thermal contact with the output devices.
• Parallel power devices: A device that runs slightly hotter draws more current, heating further while its neighbors cool and take less. Bipolar transistors do this at any current; MOSFETs do it only below the ZTC point, and above that point they share current stably, which is the main reason paralleling is routine for MOSFETs and delicate for bipolar transistors.
• Voltage regulators: A linear regulator dissipates the product of its input-to-output voltage drop and the load current, so a short-circuited output at high input voltage is the worst case. Foldback current limiting reduces the current limit as the output collapses, precisely to keep that product bounded.

Prevention Techniques

Several circuit techniques prevent thermal runaway:

• Emitter resistors: Adding resistance in the emitter of bipolar transistors provides negative feedback. As current increases, the voltage drop across the emitter resistor reduces the effective base-emitter voltage, limiting further current increase. Even small resistor values, 0.1 to 1 ohm in an audio output stage, dramatically improve thermal stability, since a drop of only 26 mV across the resistor already halves the sensitivity to a shift in V_BE.
• Current-sense feedback: Active circuits that monitor current and reduce drive as current increases prevent thermal runaway. This is standard practice in power supplies and motor drives.
• Thermal sensors: Temperature sensors placed on the same die as the power device, or bonded to its case, can trigger protective action before dangerous temperatures are reached. Placement matters more than sensor accuracy, because a sensor thermally remote from the hot spot reports the wrong temperature at exactly the moment the reading counts.
• Paralleling with ballast resistors: When paralleling power devices, individual source or emitter resistors ensure current sharing by providing negative feedback.
• SOA limiting: Safe operating area protection circuits prevent operation in conditions where thermal runaway is possible.

Safe Operating Area

The safe operating area (SOA) defines the voltage-current region where a device can operate without failure. SOA boundaries arise from several mechanisms:

• Current limit: Maximum current set by bond wire or metal capability.
• Power limit: A hyperbolic boundary, a line of constant current-voltage product, set by maximum junction temperature and thermal resistance.
• Second breakdown (bipolar): Current focusing in bipolar transistors at high voltage leads to localized heating and failure. MOSFETs operated above their ZTC point are free of this mechanism, which is why their SOA plots keep a square corner where a bipolar plot derates steeply.
• Voltage limit: Breakdown voltage sets the maximum voltage.

The power-limited boundary is most relevant for thermal runaway. For pulsed operation, the effective thermal impedance is lower, and higher power is permissible for short pulses. SOA curves therefore show a family of boundaries, one per pulse duration, and the shortest pulses approach the bond-wire and voltage limits instead.

Designers must ensure that under all operating conditions, including startup, fault, and transient conditions, the device operating point remains within the SOA.

Thermal Design Margins

Reliable designs include thermal margins:

• Maximum ambient temperature: Specify the highest expected ambient temperature and design for this worst case
• Derating: Operate devices below their maximum ratings, typically 50 to 80 percent of maximum power
• Safety margin: Ensure that even under worst-case conditions, junction temperature remains well below maximum rated temperature
• Aging allowance: Account for increased thermal resistance as thermal interface materials age

PTAT and CTAT Current Sources

Current sources with specific temperature dependence form the foundation of many compensation schemes:

PTAT (proportional to absolute temperature): Generated by impressing the difference in V_BE between transistors at different current densities across a resistor. The resulting current increases linearly with temperature:

I_PTAT = ΔV_BE / R = (kT/q) ln(N) / R

Strictly, the current is PTAT only if R is temperature independent. Because integrated resistors are not, the current inherits the resistor's temperature coefficient: a positive coefficient flattens the current, a negative one steepens it. Designers exploit this by choosing the resistor type, or by combining two types, to place the coefficient where they want it.

CTAT (complementary to absolute temperature): Generated from a V_BE-based voltage divided by a resistor. The negative temperature coefficient of V_BE creates a current that decreases with temperature.

Combining PTAT and CTAT currents in appropriate proportions yields currents with arbitrary temperature coefficients, including zero for temperature-stable bias. The sum taken in the ratio that zeroes the coefficient is, in current form, exactly the bandgap reference described earlier.

Temperature-Compensated Bias Circuits

Several bias circuit topologies provide temperature compensation:

V_BE multiplier: By adjusting the multiplication factor with temperature-dependent elements, the output voltage temperature coefficient can be controlled. It is standard in class AB power amplifier bias circuits, where the multiplier transistor is mounted on the output-stage heatsink so that its own V_BE tracks the temperature of the devices it biases.

Constant-g_m bias: Also called the beta-multiplier bias, this cell fixes a MOSFET's transconductance against a resistor value rather than against process parameters, giving a g_m proportional to 1/R. Because transconductance follows the square root of mobility, holding it constant requires a bias current that rises with temperature to offset the falling mobility, and the cell generates exactly that current on its own. The transconductance then inherits the resistor's temperature coefficient rather than the mobility's.

• Bandgap-referenced bias: Using a bandgap voltage reference to generate bias voltages provides temperature-stable biasing for precision circuits.
• Self-biased structures: Circuits where bias conditions are determined by device ratios rather than absolute voltage values tend to be inherently temperature stable. They generally need a startup circuit, since the degenerate state in which no current flows also satisfies the bias equations.

Gain Compensation

Temperature-induced gain variations can be compensated by several methods:

• Temperature-dependent feedback: Using thermistors or other temperature-sensitive elements in feedback networks adjusts gain to compensate for amplifier gain variations. A negative-temperature-coefficient thermistor is strongly nonlinear, so it is usually padded with fixed resistors to linearize its response over the range of interest.
• AGC (automatic gain control): Closed-loop systems that monitor output amplitude and adjust gain maintain consistent output level regardless of component variations.
• Matched device ratios: When gain depends on ratios of similar components, temperature effects tend to cancel if both components are at the same temperature. On-chip resistor ratios hold to a few parts per million per degree Celsius even though the absolute values drift by a thousand times that.
• Chopper stabilization: By modulating signals to a higher frequency and demodulating after amplification, chopper techniques move the signal away from the low-frequency region where offset drift and flicker noise live. Chopper-stabilized amplifiers reach offset drifts on the order of tens of nanovolts per degree Celsius, against microvolts per degree Celsius for a good conventional bipolar part.

Digital Temperature Compensation

Modern systems increasingly use digital techniques for temperature compensation:

• Temperature sensor: An on-chip or system temperature sensor measures the actual operating temperature. On-chip sensors are usually PTAT circuits built from the same bipolar devices described above.
• Characterization data: Factory calibration determines how circuit parameters vary with temperature and stores correction data in nonvolatile memory, either as polynomial coefficients or as a lookup table with interpolation.
• Digital correction: A digital processor applies corrections based on measured temperature and stored calibration data.
• DAC adjustment: For analog outputs, DACs can trim bias currents, reference voltages, or gain settings in response to temperature.

Digital compensation can correct for complex, nonlinear temperature dependencies that are difficult to address with analog techniques alone. It also enables post-manufacturing calibration that corrects for individual device variations. Its limits are equally clear: it corrects only repeatable error, so hysteresis, long-term drift, and random noise pass through untouched, and the calibration itself costs test time at multiple temperatures.

Thermal Management Integration

Effective temperature compensation includes thermal management considerations:

• Sensor placement: Temperature sensors should measure the temperature of the circuits they are compensating, not package or ambient temperature
• Thermal equilibrium: Compensation accuracy depends on thermal equilibrium; rapid temperature changes may cause temporary errors
• Power supply stability: Temperature-compensated circuits may be sensitive to supply voltage variations; stable supplies enhance compensation effectiveness
• Matched thermal paths: Components that must match should have matched thermal environments

Resistor Temperature Coefficients

Different resistor types have different temperature characteristics. The figures below describe each class; no single number applies to resistors in general.

• Carbon composition: Large and poorly controlled coefficient, of either sign depending on the resistance value and typically several hundred to a couple of thousand parts per million per degree Celsius, together with a significant voltage coefficient. Obsolete for precision work and retained mainly for pulse-handling ability.
• Carbon film: Negative coefficient, typically −200 to −500 parts per million per degree Celsius. Moderate stability and cost.
• Metal film: Low coefficient, typically ±25 to ±100 parts per million per degree Celsius. Good stability, widely used in precision circuits.
• Wirewound: Low coefficient, typically ±20 to ±50 parts per million per degree Celsius, but with series inductance that limits high-frequency use.
• Thin-film on ceramic: Very low coefficient, ±5 to ±25 parts per million per degree Celsius, excellent stability for precision applications.
• Bulk metal foil: The most stable class available, with coefficients of a few parts per million per degree Celsius or less, achieved by balancing the resistive alloy's own coefficient against the mechanical strain the substrate imposes on it as it expands.
• Integrated resistors: Polysilicon and diffused resistors carry large positive coefficients, on the order of a thousand parts per million per degree Celsius and often more, with the exact value set by doping. On-chip resistor ratios, by contrast, are stable to a few parts per million per degree Celsius, which is why integrated analog design is built on ratios.

The same lesson applies on a board. For precision circuits, the ratio between resistors matters more than the absolute values. Using resistors from the same manufacturing lot, of the same type, and placed close together on a PCB improves ratio stability; a resistor network in a single package does better still, because all elements share one substrate and one temperature.

Capacitor Temperature Effects

Capacitor temperature behavior varies dramatically by dielectric type:

• C0G/NP0 ceramic: Nominally zero temperature coefficient with a tolerance of ±30 parts per million per degree Celsius over −55 to +125 degrees Celsius, the best ceramic dielectric for precision and stability. This Class 1 dielectric is also free of the piezoelectric and voltage-coefficient effects that afflict Class 2 parts.
• X7R ceramic: Capacitance varies by at most ±15 percent over −55 to +125 degrees Celsius. Acceptable for bypass and coupling but not for precision, and its capacitance also falls sharply under applied DC bias.
• Y5V ceramic: Capacitance varies from +22 percent to −82 percent over its rated range of −30 to +85 degrees Celsius, a narrower range as well as a far wider tolerance than X7R. Suitable only for bulk bypass.
• Film capacitors: Polypropylene has a coefficient around −200 parts per million per degree Celsius; polystyrene around −120 parts per million per degree Celsius. Both offer good stability, and the negative coefficient can be set against a positive-coefficient inductor or resistor to stabilize a time constant.
• Aluminum electrolytic: Capacitance increases with temperature while equivalent series resistance falls, so the part performs worst when cold. Electrolyte loss at high temperature is the principal wear-out mechanism, with rated life conventionally doubling for every 10 degrees Celsius of operation below the rated temperature.

For oscillators, filters, and other frequency-determining applications, C0G ceramic or film capacitors are essential for temperature stability.

Inductor Considerations

Inductors exhibit temperature effects primarily through their wire resistance and magnetic core properties:

• Copper wire resistance: Increases by about 0.39 percent per degree Celsius near room temperature, so winding resistance rises by roughly 40 percent between 25 and 125 degrees Celsius and copper loss rises with it.
• Ferrite cores: Permeability is strongly temperature dependent, and not in the direction often assumed. The initial permeability of a manganese-zinc ferrite typically rises with temperature to a peak just below the Curie temperature, then collapses above it. Power ferrites are formulated so that core loss passes through a minimum near normal operating temperature, commonly in the region of 80 to 100 degrees Celsius.
• Air core: No magnetic material temperature dependence, so inductance shifts only with the thermal expansion of the winding form; wire resistance still sets the Q factor.
• Powdered iron cores: The distributed air gap gives much lower permeability than ferrite and, in most mixes, a smaller and better-specified temperature coefficient of inductance. Saturation is gradual rather than abrupt, which is often desirable in a power inductor.

Temperature Testing Methods

Several approaches are used for temperature testing:

• Temperature chambers: Enclose the entire circuit in a temperature-controlled environment. Provides uniform temperature but requires equilibration time and may not represent actual operating conditions.
• Hot plates and cold plates: Heat or cool specific components or circuit sections. Faster response than chambers but creates thermal gradients.
• Forced-air heating and cooling: Temperature-controlled air streams provide rapid temperature changes for thermal cycling tests, and a handheld nozzle is the usual tool for finding which component on a board is responsible for a drift.
• Liquid baths: Immersion in temperature-controlled fluids provides rapid, uniform heating or cooling, though not all circuits can be immersed.
• Self-heating tests: Operating circuits at elevated power levels to induce self-heating reveals thermal design issues.
• Infrared thermography: A thermal camera maps the surface temperature of a powered board and locates hot spots directly. Emissivity varies with surface finish, so absolute readings need calibration, but relative comparisons are immediately useful.

Characterization Procedures

Thorough temperature characterization includes:

• Soak testing: Allow circuits to reach thermal equilibrium at each temperature before measurement
• Multiple temperature points: Test at minimum, room, and maximum temperatures at minimum; additional points reveal nonlinear behavior
• Both sweep directions: Step temperature up and then back down to expose hysteresis, which no single-direction sweep and no calibration can catch
• Thermal cycling: Repeated temperature excursions reveal intermittent failures and mechanical stress effects
• Operating life tests: Extended operation at elevated temperature accelerates aging mechanisms
• Parameter extraction: Measure key parameters at multiple temperatures to determine temperature coefficients

Note that a drift specification quoted in parts per million per degree Celsius may be derived either from the extremes of the range, the box or butterfly method, or from a slope fitted across it. The two definitions can differ substantially for the same part, so datasheet comparisons must confirm which one is in use.

Correlation to Field Conditions

Laboratory testing must correlate to actual field conditions:

• Ambient temperature range: Understand the actual operating environment, not just specification limits
• Internal temperature rise: Account for self-heating and enclosure effects that raise component temperatures above ambient
• Thermal transients: Field conditions may include rapid temperature changes not captured in steady-state testing
• Solar loading: Outdoor equipment may experience solar heating effects
• Altitude effects: Reduced air pressure at altitude impairs convective cooling