Electronics Guide

Physical Mechanism

In a MOSFET operating in saturation, the lateral electric field near the drain can reach several hundred thousand volts per centimeter. Carriers traveling through this high-field region gain kinetic energy from the field faster than they can dissipate it through lattice collisions. These energetic or "hot" carriers can experience several fates:

• Impact ionization: Hot carriers collide with silicon atoms, creating electron-hole pairs that can cause substrate current and potentially latch-up
• Oxide injection: Carriers with sufficient energy surmount the silicon-oxide barrier and enter the gate oxide
• Interface state generation: Energetic carriers break silicon-hydrogen bonds at the interface, creating trap states
• Oxide charge trapping: Injected carriers become trapped at defect sites within the oxide

For NMOS transistors, hot electrons are the primary concern. Electrons gain energy from the field more readily than holes, and the barrier they must surmount at the silicon-oxide interface is lower: roughly 3.1 electron volts for electrons against about 4.8 electron volts for holes. For PMOS transistors, both hot electrons and hot holes can cause damage, though PMOS devices are generally more resistant to hot carrier injection than their NMOS counterparts.

Manifestations in Circuit Parameters

Hot carrier damage manifests through several measurable parameter changes:

• Threshold voltage shift: Trapped charge and interface states shift the threshold voltage, typically in the positive direction for NMOS devices
• Transconductance degradation: Interface states scatter carriers, reducing mobility and lowering transconductance. A 10 percent drift in transconductance or in linear-region drain current is the conventional end-of-life criterion
• Subthreshold swing increase: Interface states increase the gate voltage required to change drain current by a decade in the subthreshold region
• Drain current reduction: The combined effects of threshold shift and transconductance loss reduce the drain current for a given bias

In analog circuits, these changes can cause offset voltage drift in differential pairs, gain reduction in amplifiers, and bias current shifts in current mirrors. The asymmetric nature of HCI damage, concentrated near the drain, can also break the symmetry between nominally matched devices.

Stress Conditions and Acceleration

HCI damage accelerates under specific operating conditions:

• High drain-source voltage: Higher V_DS increases the lateral field and carrier energy
• Moderate gate voltage: Maximum substrate current, and thus maximum hot carrier generation, occurs when V_GS is roughly 40 to 50 percent of V_DS, near V_DS/2. In deep submicron devices the worst-case ratio shifts toward higher V_GS
• Low temperature: Unlike most degradation mechanisms, hot carrier injection worsens as temperature falls, because reduced phonon scattering lengthens the carrier mean free path and lets carriers gain more energy between collisions. Worst-case hot carrier stress therefore sits at the cold end of the operating range, not the hot end
• High frequency switching: Each switching event can inject carriers, accumulating damage over billions of cycles

The time to failure typically follows a power-law dependence on substrate current, which itself depends exponentially on the electric field. Accelerated testing therefore raises V_DS and V_GS rather than temperature, inducing measurable degradation in hours rather than years. Because the temperature coefficient of hot carrier damage is negative, an Arrhenius acceleration factor with a positive activation energy does not describe this mechanism, and hot carrier lifetime is characterized in a separate stress at or near room temperature rather than in the high-temperature tests described later in this article.

Design Mitigation Strategies

Several design techniques reduce HCI susceptibility in analog circuits:

• Lightly doped drain (LDD) structures: Graded doping profiles reduce the peak electric field near the drain
• Longer channel lengths: Longer devices have lower lateral fields for a given V_DS; analog circuits often use longer-than-minimum channels
• Reduced operating voltages: Lower V_DS exponentially decreases hot carrier generation
• Cascode configurations: Cascoding divides voltage across two devices, reducing the V_DS seen by each transistor
• Symmetric circuit topologies: Even if HCI occurs, symmetric degradation in matched pairs may preserve differential operation

Process technology improvements, including deuterium annealing and nitrided oxide interfaces, have reduced HCI sensitivity in modern technologies, but it remains a reliability concern, especially for circuits operating at the limits of their voltage ratings.

Physical Mechanism

NBTI is believed to involve the following processes:

• Hydrogen release: Under negative gate bias, holes at the silicon-oxide interface react with hydrogen-passivated silicon dangling bonds, releasing hydrogen atoms or molecules
• Interface state generation: The broken Si-H bonds become electrically active interface traps that shift threshold voltage
• Hydrogen diffusion: Released hydrogen diffuses into the oxide, potentially reacting with other oxide defects
• Oxide charge trapping: Pre-existing oxide defects can trap holes, adding to threshold shift

A key characteristic of NBTI is partial recovery when the stress is removed. When the gate bias returns to zero or positive, some of the generated interface states re-passivate as hydrogen diffuses back and reacts with dangling bonds. This recovery complicates both reliability assessment and circuit behavior prediction.

Impact on Circuit Parameters

NBTI degradation affects PMOS transistor parameters in ways that directly impact analog circuit performance:

• Threshold voltage increase: The magnitude of V_TH increases (becomes more negative), reducing PMOS drive current for a given overdrive voltage
• Transconductance reduction: Interface states cause mobility degradation, so transconductance falls alongside the threshold shift
• Drain current decrease: The threshold and mobility effects combine to reduce saturation current, which an analog stage shows directly as lost gain and shifted bias
• Leakage current changes: Subthreshold and gate leakage characteristics may shift

In analog circuits, NBTI can cause bias current drift in PMOS current mirrors, V_BE multiplier voltage shifts in bandgap references, offset voltage increase in differential amplifiers with PMOS input pairs, and gain degradation in PMOS-loaded amplifiers.

Time and Temperature Dependence

NBTI degradation follows characteristic time and temperature dependencies:

• Time dependence: Threshold voltage shift typically follows a power law in time, ΔV_TH ∝ tⁿ, where the exponent n of time is typically 0.15 to 0.25 (near 1/6 to 1/4, reflecting hydrogen-diffusion-limited kinetics in the reaction-diffusion model)
• Temperature activation: NBTI accelerates exponentially with temperature, with an apparent activation energy commonly reported between about 0.1 and 0.5 eV; the extracted value varies widely because it is sensitive to measurement delay and the recovery effect
• Electric field dependence: A higher oxide field, meaning a more negative V_GS, accelerates degradation
• Recovery effect: Removing stress allows partial recovery, complicating lifetime prediction

The fractional power-law time dependence means that most NBTI damage occurs early in device life, with the degradation rate slowing over time. This characteristic must be considered when extrapolating accelerated test results to operational conditions.

AC vs DC NBTI

Circuit operating conditions strongly influence NBTI behavior:

• DC stress: Continuous negative bias causes maximum degradation because no recovery occurs
• AC stress: Switching between stress and recovery phases produces less net degradation than DC stress, so a lifetime extrapolated from DC stress overstates the damage a switched device actually suffers
• Frequency independence: Measured degradation is essentially independent of the stress frequency across an enormous range, reported from about 1 Hz into the gigahertz region. The diffusion front that limits trap generation responds to accumulated stress time, not to cycle time
• Duty cycle effects: The duty cycle, not the frequency, sets the net shift. The dependence traces an S-shaped curve that is comparatively flat near 50 percent and rises steeply as the duty cycle approaches continuous negative bias

For analog circuits where PMOS devices remain continuously biased, DC NBTI conditions often apply, representing the worst case. Digital circuits benefit from AC operation, though the recovery is never complete. Recovery also makes the measurement delicate. Part of the threshold shift disappears during the interval between removing the stress and reading the device, so a slow measurement understates the degradation that was present under stress. Characterization therefore uses fast or on-the-fly measurement to keep that delay short, and a reported shift means little unless the measurement delay is reported with it.

Design Considerations

Analog designers can mitigate NBTI effects through careful design:

• Guard-banding: Design with margin to accommodate expected threshold voltage shift over lifetime
• Reduced overdrive: Lower gate-source voltage reduces oxide field and NBTI rate
• Larger devices: Using larger-than-minimum devices provides more current margin
• Symmetric stress: In matched pairs, ensuring equal stress conditions keeps degradation balanced
• Periodic refreshing: If possible, periodically removing stress allows recovery
• Consider NMOS alternatives: Where feasible, using NMOS devices avoids NBTI (though may introduce other issues)

Process technology improvements, including different oxide compositions, interface treatments, and strain engineering, continue to reduce NBTI sensitivity in advanced nodes.

Physical Fundamentals

Electromigration occurs through several mechanisms:

• Grain boundary diffusion: Atoms move preferentially along grain boundaries, the interfaces between crystalline grains in polycrystalline metal
• Surface diffusion: Atoms can migrate along metal surfaces, particularly in narrow lines
• Bulk diffusion: At elevated temperatures, atoms can move through the crystal lattice itself
• Interface diffusion: The metal-barrier and metal-dielectric interfaces provide additional diffusion paths

Aluminum and copper, the primary interconnect metals, have different electromigration characteristics. Copper has superior electromigration resistance due to its higher activation energy for atomic diffusion, but requires careful barrier layer design to prevent diffusion into surrounding dielectrics.

Current Density Limits

Electromigration occurs when current density exceeds technology-dependent limits:

• DC current limits: Continuous unidirectional current causes maximum atomic migration; limits are typically 1 to 2 mA per micrometer of metal width for aluminum, higher for copper
• AC current considerations: Alternating current allows partial atomic back-migration; effective limits are higher for AC
• Peak current constraints: Even brief current spikes can contribute to electromigration damage if they occur frequently
• Temperature effects: Electromigration rate increases exponentially with temperature; limits must account for worst-case operating temperatures
• Short-length immunity: Atoms piling up at the downstream end of a short line raise a back stress that opposes the electron wind. Below a critical product of current density and line length the two balance, no steady migration occurs, and design rules exempt interconnects shorter than that threshold

Design rules specify maximum current density for each metal layer, considering linewidth, temperature, and expected product lifetime. Analog circuits with high DC currents require particular attention to electromigration.

Analog Circuit Implications

Electromigration affects analog circuits in specific ways:

• Power distribution: Power supply and ground lines carrying large DC currents are primary electromigration concerns
• Output stages: High-current output drivers and power transistors require wide metal connections
• Current mirrors: Lines carrying DC bias currents must be adequately sized
• Resistance increase: Before complete failure, void formation increases interconnect resistance, potentially affecting precision circuits
• Thermal effects: Local heating from current flow accelerates electromigration; thermal design is critical

Unlike digital circuits where electromigration primarily causes binary failure, analog circuits may experience gradual performance degradation as interconnect resistance increases.

Design Rules and Verification

Preventing electromigration failure requires systematic design practices:

• Current density analysis: EDA tools calculate current density in each metal segment and flag violations
• Wire sizing: Increasing metal width reduces current density; multiple parallel paths can share current
• Via arrays: Multiple vias reduce current crowding at layer transitions
• Slotted or segmented power lines: For very wide lines, slots prevent mechanical stress issues while maintaining current capacity
• Thermal management: Reducing metal temperature through layout and packaging extends electromigration lifetime

Modern design flows include electromigration checking as a standard verification step, with tools that account for both average and peak current conditions.

Black's Equation

The time to electromigration failure is commonly described by Black's equation:

MTTF = A J⁻ⁿ exp(E_a/kT)

Where:

• MTTF: Mean time to failure
• A: A constant depending on metal properties and geometry
• J: Current density
• n: Current-density exponent. Black's original analysis gives 2. Current practice uses a value between 1 and 2, nearer 1 where the test holds the metal temperature fixed and nearer 2 where Joule heating from the test current adds to the stress
• E_a: Activation energy for atomic diffusion along whichever path dominates. Aluminum and aluminum-copper alloys fall near 0.6 eV, where grain-boundary diffusion governs. Copper damascene lines fall near 0.8 to 1.0 eV, because there the fast path is the interface between the copper and its dielectric cap rather than the grain boundaries
• k: Boltzmann's constant
• T: Absolute temperature of the metal, which local Joule heating raises above the ambient

Both dependences are steep. At n = 2, doubling the current density cuts the mean time to failure by a factor of four. At E_a = 0.7 eV, raising the metal temperature from 55 to 125 degrees Celsius shortens it by a factor of about 78. The activation energy is the parameter that must be measured rather than assumed: carrying the aluminum figure of 0.6 eV into a copper process that truly sits at 0.9 eV understates the projected field life by a factor of about six over that same temperature span. The error is conservative in direction, but it is large enough to distort a design margin.

Physical Mechanism

TDDB proceeds through several stages:

• Defect generation: Under electrical stress, bonds within the oxide break, creating defects (traps) that can store charge
• Trap formation: Both intrinsic oxide defects and stress-induced defects accumulate over time
• Percolation: When defect density reaches a critical level, a continuous path of defects spans the oxide thickness
• Breakdown: The percolation path becomes conductive, causing catastrophic oxide failure

The percolation model explains the statistical nature of TDDB: breakdown occurs when random defects happen to align into a spanning path, making failure time inherently variable even for identical devices under identical stress.

Oxide Thickness Effects

TDDB behavior depends strongly on gate oxide thickness:

• Thick oxides (greater than 5 nm): Breakdown occurs through avalanche multiplication and thermal runaway; field acceleration is primary concern
• Thin oxides (less than 5 nm): Quantum mechanical tunneling enables direct carrier transport; voltage acceleration dominates
• Ultra-thin oxides (less than 2 nm): Breakdown may be soft, with gate leakage increasing gradually rather than causing immediate hard failure
• High-k dielectrics: Alternative gate dielectrics have different breakdown characteristics and failure modes

Modern technologies with ultra-thin gate oxides face TDDB challenges that require careful voltage management and design margins.

Field and Voltage Acceleration Models

Three competing models describe how oxide lifetime depends on stress, and the choice among them matters more than the quality of the data:

• The E-model: A thermochemical picture in which the applied field lowers the activation energy for bond breaking, so the time to breakdown falls exponentially with the oxide field, t_BD ∝ exp(−γE_ox)
• The 1/E-model: An anode hole injection picture driven by the tunneling current, giving t_BD ∝ exp(G/E_ox)
• The power-law voltage model: An empirical form for ultra-thin oxides in which the time to breakdown falls as a large negative power of gate voltage, t_BD ∝ V_G⁻ⁿ

Across the narrow band of elevated stress where measurement is practical, all three fit the data comparably well. Extrapolated down to operating voltage, they diverge by orders of magnitude in projected lifetime. The predicted lifetime therefore rests chiefly on which model was assumed, which is why a reliability figure for a gate dielectric means little unless it names the acceleration model and the stress range over which that model was fitted.

Soft Breakdown and Progressive Degradation

In thin oxides, breakdown may occur in stages:

• Stress-induced leakage current (SILC): Before breakdown, trap-assisted tunneling increases gate leakage; this is often an early indicator of oxide damage
• Soft breakdown: A partial conductive path forms, increasing gate current by orders of magnitude but without immediate catastrophic failure
• Progressive breakdown: The initial breakdown path may heal and reform, causing noisy gate current
• Hard breakdown: Eventually, a stable low-resistance path forms, destroying device functionality

For analog circuits, even soft breakdown is problematic because the increased gate leakage current disrupts biasing and introduces noise. Detection and monitoring of SILC can provide early warning of impending failure.

Statistical Treatment

TDDB failure times follow Weibull statistics:

• Weibull distribution: The probability of failure increases with time according to the Weibull cumulative distribution function
• Shape parameter (β): Describes the failure rate trend. A β below 1 indicates a falling failure rate, and a β above 1 indicates a rising one, the signature of wear-out
• Scale parameter (η): The characteristic life, the time by which 63.2 percent of devices have failed
• Area scaling: Larger oxide areas fail sooner because they contain more potential defect sites

The statistical nature of TDDB means that a certain percentage of devices will fail earlier than the median; reliability specifications typically address the early tail of the distribution, for example fewer than 0.1 percent of devices failing within the product lifetime.

Design and Process Considerations

Managing TDDB risk requires attention at both design and process levels:

• Voltage derating: Operating below maximum rated voltage extends oxide lifetime exponentially
• Oxide quality: Process controls minimize oxide defect density; plasma damage must be avoided
• Gate area management: Minimizing total gate oxide area reduces statistical failure probability
• Thick oxide options: I/O transistors and analog circuits may use thicker oxides for improved reliability
• Stress management: Avoiding excessive gate voltage during operation and test protects oxide integrity

Qualification testing uses elevated voltage and temperature to accelerate TDDB, enabling lifetime prediction from relatively short test durations.

Origins of Mechanical Stress

Stress in metal interconnects arises from several sources:

• Thermal expansion mismatch: Metal (aluminum CTE approximately 23 ppm/K, copper CTE approximately 17 ppm/K) expands more than silicon (CTE approximately 2.6 ppm/K) and dielectrics
• Deposition stress: Metal films deposited under non-equilibrium conditions contain intrinsic stress
• Process thermal cycles: High-temperature processing steps followed by cooling create locked-in stress
• Passivation constraints: Overlying dielectric layers constrain metal expansion

When the interconnect cools from deposition temperature, the metal wants to contract more than the surrounding materials allow, creating tensile stress in the metal. This tensile stress provides the driving force for void formation.

Void Formation Mechanism

Under tensile stress, metal atoms migrate from regions of high stress to regions of low stress:

• Vacancy accumulation: Atoms leaving a location create vacancies that can cluster into voids
• Via and contact regions: The metal-barrier interface near vias often serves as a nucleation site for voids
• Grain boundaries: Stress concentrations at grain triple points can initiate void formation
• Line ends: Metal line terminations experience stress gradients that promote void growth

Unlike electromigration, stress migration does not require current flow and can occur in unused spare lines or unconnected metal features.

Temperature Dependence

Stress migration has a complex temperature dependence:

• Low temperature: Stress is highest but diffusion is too slow for significant migration
• High temperature: Diffusion is fast but stress is relieved by creep and other relaxation mechanisms
• Intermediate temperature: A "sweet spot" exists where both stress and diffusion are sufficient for significant migration; typically 100 to 250 degrees Celsius for aluminum
• Storage conditions: Devices stored at elevated temperature without power may be susceptible to stress migration

This non-monotonic temperature dependence means that stress migration testing must be performed at the critical temperature range, not simply at the highest practical temperature.

Design Considerations

Preventing stress migration failures requires design and process attention:

• Redundant vias: Multiple vias provide alternative current paths if one via location develops a void
• Metal slots: Wide metal lines may require slots to reduce stress concentration
• Bamboo structure: Metal lines narrower than the grain size (bamboo structure) have better stress migration resistance
• Barrier layer selection: The choice of barrier metal affects void nucleation at interfaces
• Stress relief features: Designed-in stress relief structures can manage stress distribution

Thermal Expansion Mismatch

The fundamental driver of thermal cycling damage is the difference in thermal expansion between connected materials:

• Silicon die: CTE approximately 2.6 ppm/K
• Copper lead frame: CTE approximately 17 ppm/K
• FR-4 PCB: CTE 14 to 16 ppm/K in-plane, 60 to 80 ppm/K through-thickness
• Ceramic substrates: CTE 6 to 7 ppm/K
• Plastic molding compound: CTE varies widely, from 15 to 50 ppm/K

When temperature changes, these materials expand or contract at different rates, creating stress at their interfaces. Cyclic stress leads to fatigue failure even when the stress in each cycle is below the material's static strength.

Solder Joint Fatigue

Solder joints connecting packages to PCBs are a primary thermal cycling failure mode:

• Shear strain: The relative motion between package and PCB shears the solder joints, with strain proportional to distance from the neutral point (DNP)
• Creep and stress relaxation: Solder deforms over time under stress, redistributing loads
• Crack initiation: Fatigue cracks typically initiate at stress concentrations near the solder joint corners
• Crack propagation: Cracks grow with continued cycling until the joint fails electrically

Larger packages with greater distance to the neutral point experience higher solder joint strain and fail sooner. Area array packages (BGA, CSP) distribute strain across many joints, improving reliability.

Wire Bond Fatigue

Wire bonds connecting the die to lead frame or substrate are also vulnerable:

• Bond heel stress: The wire-to-pad interface experiences concentrated stress during flexing
• Wire flexure: Wire loop deforms as die and substrate move relative to each other
• Intermetallic growth: Thermal cycling accelerates gold-aluminum intermetallic formation at bond interfaces
• Bond lift: Fatigue can cause the ball bond to lift from the pad

Wire bond reliability is improved through proper loop height and shape, appropriate bonding parameters, and limiting thermal exposure during assembly.

Package Cracking and Delamination

The package structure itself can fail under thermal cycling:

• Die-attach fatigue: The adhesive or solder attaching the die to substrate can crack or delaminate
• Package cracking: Thermal stress can cause cracks in ceramic or plastic packages
• Delamination: Interfaces between molding compound and lead frame or die can separate
• Moisture effects: Absorbed moisture vaporizing during temperature excursions (popcorning) can cause sudden delamination

Reliability Prediction

Thermal cycling reliability is typically predicted using the Coffin-Manson equation:

N_f = C (Δε)^−m

Where N_f is cycles to failure, Δε is the cyclic strain range, and C and m are material-dependent constants. This relationship enables prediction of field life from accelerated testing with larger temperature swings.

The exponent repays care, because the relation is more often written the other way round. The classical form gives strain against cycles, Δε_p/2 = ε_f′(2N_f)^c, where c is the fatigue ductility exponent. Solving that form for cycles makes the exponent on strain the reciprocal of c, so m = 1/|c|. For solder alloys c falls near −0.37 to −0.6, which places m near 1.7 to 2.7: eutectic tin-lead sits near 1.9, and published fits for tin-silver-copper lead-free alloys run distinctly higher. Quoting |c| itself as m is a common error and badly understates the strain sensitivity: for a two-to-one strain ratio it predicts a life ratio near 1.4 where the correct exponent predicts 4 or more. Because the shear strain in a solder joint is very nearly proportional to the temperature swing, the same exponent serves the temperature-range form N_f = C (ΔT)^−m in which qualification work usually quotes it.

Plain Coffin-Manson accounts for neither dwell time nor mean temperature, and both matter, because solder creeps. Engelmaier's refinement makes c a function of the mean joint temperature and of the high-temperature dwell, and the Norris-Landzberg form adds a cycling-frequency term and an Arrhenius term in the peak temperature. For a swing from −40 to 125 degrees Celsius with dwells of tens of minutes, Engelmaier's expression returns c near −0.42, so m lands near 2.4.

Qualification testing typically uses temperature cycling between −40 degrees Celsius and +125 degrees Celsius or similar ranges, with several hundred to thousands of cycles required to pass. At m = 2, a test swing of 165 degrees Celsius stands in for a 55-degree field swing at an acceleration factor of nine, so one thousand test cycles represent nine thousand field cycles.

Moisture Absorption and Effects

Plastic packages absorb moisture from the environment:

• Moisture diffusion: Water vapor diffuses through the molding compound, reaching saturation over days to weeks depending on temperature and humidity
• Interface weakening: Moisture accumulates at interfaces, weakening adhesion between molding compound and lead frame or die
• Corrosion enablement: Moisture provides the electrolyte necessary for electrochemical corrosion
• Parameter shifts: Moisture can cause surface charge changes affecting device parameters

Moisture sensitivity level (MSL) ratings indicate how long a package can be exposed to ambient humidity before reflow soldering. Excessively moist packages may "popcorn" during reflow as absorbed moisture vaporizes rapidly.

Corrosion Mechanisms

Several corrosion processes can affect packaged ICs:

• Aluminum corrosion: Moisture and ionic contamination can attack aluminum bond pads and metallization
• Gold-aluminum intermetallic: Kirkendall voiding at gold-aluminum interfaces creates weak bonds; "purple plague" describes advanced intermetallic failure
• Dendritic growth: Under bias with moisture present, metal dendrites can grow between adjacent conductors, eventually causing shorts
• Galvanic corrosion: Dissimilar metals in contact with an electrolyte (moisture) create galvanic cells that accelerate corrosion

Proper passivation, hermetic or near-hermetic packaging, and contamination control are essential for corrosion prevention.

Intermetallic Growth

At junctions between different metals, intermetallic compounds form and grow over time:

• Gold-aluminum: Several intermetallic phases form at gold wire to aluminum pad bonds, among them Au₄Al, Au₅Al₂, Au₂Al, AuAl, and AuAl₂
• Tin-copper: Cu₆Sn₅ and Cu₃Sn intermetallics grow in tin-based solder joints
• Kirkendall voids: Unequal diffusion rates at intermetallic interfaces create voids that weaken bonds
• Brittle phases: Some intermetallics are brittle and prone to cracking under mechanical stress

Intermetallic growth is thermally activated; elevated temperature during operation or storage accelerates growth. Proper material selection and limiting thermal exposure control intermetallic issues.

Package Selection for Reliability

Package type significantly affects reliability:

• Hermetic packages: Ceramic or metal packages with sealing prevent moisture ingress; used for high-reliability and military applications
• Plastic packages: Lower cost but susceptible to moisture; suitable for most commercial applications with proper controls
• Chip-scale packages: Minimal package volume reduces thermal mismatch but may have reliability trade-offs
• Flip-chip: Direct die attachment eliminates wire bonds but introduces underfill reliability considerations

Acceleration Principles

Accelerated testing relies on predictable relationships between stress and failure rate:

• Arrhenius acceleration: Thermally activated mechanisms follow an exponential temperature dependence. The familiar rule of thumb that the rate doubles for every 10 degrees Celsius is convenient but is not one activation energy: it corresponds to about 0.55 eV near room temperature and about 0.97 eV at 125 degrees Celsius, so the rule quietly changes its own physics as the baseline rises
• Power law acceleration: Voltage and current stress often follow power-law acceleration
• Humidity acceleration: Moisture-related failures accelerate with relative humidity, often following the Peck or Hallberg-Peck models
• Combined stresses: Multiple stresses may act independently or synergistically

The acceleration factor (AF) relates the time to failure under accelerated conditions to that under use conditions:

AF = t_use/t_test = exp[(E_a/k)(1/T_use − 1/T_test)]

Here E_a is the activation energy and T is absolute temperature, in kelvins rather than degrees Celsius. When the test runs hotter than the application, 1/T_use exceeds 1/T_test, the bracket is positive, and AF exceeds one, so each hour on test stands for AF hours of use. Take E_a = 0.7 eV, a use temperature of 55 degrees Celsius and a test temperature of 125 degrees Celsius: E_a/k is 8123 K, the reciprocal-temperature difference is 5.36 × 10⁻⁴ per kelvin, their product is 4.35, and AF is about 78. A one-thousand-hour test then demonstrates roughly 78,000 hours, close to nine years, of field life — at that activation energy and no other.

That last qualification carries the weight. The factor is only as good as the activation energy, and it applies only to mechanisms that are thermally activated at all. Hot carrier injection is not one of them, since its damage rate rises as temperature falls and no positive activation energy describes it. Stress-induced voiding is not one either, since its rate peaks at an intermediate temperature and falls away on both sides. Each needs its own stress conditions rather than a hotter version of the same test.

Standard Stress Tests

Industry-standard accelerated tests address specific failure mechanisms:

• High Temperature Operating Life (HTOL): Devices operate at elevated temperature, 125 degrees Celsius being typical, and at elevated voltage. The heat accelerates bias temperature instability, dielectric breakdown, and electromigration. It does not accelerate hot carrier damage, which the elevated voltage drives and the elevated temperature in fact suppresses, so hot carrier lifetime is characterized in a separate stress near room temperature
• Temperature Humidity Bias (THB): Exposure to 85 degrees Celsius and 85 percent relative humidity under bias accelerates moisture-related failures and corrosion
• Temperature Cycling: Repeated cycling between temperature extremes, commonly −40 degrees Celsius to +125 degrees Celsius, accelerates mechanical fatigue
• Autoclave or pressure cooker test: Saturated steam at 121 degrees Celsius stresses package sealing
• Electromigration Testing: Elevated current density and temperature accelerate interconnect migration

Analog-Specific Test Considerations

Testing analog circuits requires attention to specific concerns:

• Parameter monitoring: Tracking offset voltage, gain, linearity, and other analog parameters during stress reveals degradation trends
• Worst-case bias: Stress conditions should include the operating points that maximize specific degradation mechanisms
• Matching degradation: Differential parameters require monitoring of mismatch, not just individual device parameters
• Frequency dependence: AC parameters may degrade differently than DC parameters
• Noise measurement: Low-frequency noise can be an early indicator of device degradation

For analog products, defining "failure" requires establishing parametric limits rather than simple pass/fail functionality. Gradual degradation toward the specification limit must be characterized.

Burn-In Screening

Burn-in subjects production devices to elevated stress to precipitate early failures:

• Infant mortality: Devices with latent defects fail early; burn-in removes these before shipment
• Stress conditions: Typically elevated temperature and voltage, less aggressive than qualification test conditions
• Duration: Usually 24 to 168 hours, depending on product reliability requirements
• Dynamic vs static: Dynamic burn-in with active operation stresses more circuit elements than static bias

While burn-in improves shipped product reliability by removing weak devices, it consumes product lifetime for surviving devices. The trade-off between screening effectiveness and lifetime consumption must be optimized for each product's reliability requirements.

Lifetime Prediction

Accelerated test data enables lifetime prediction through extrapolation:

• Activation energy determination: Testing at multiple temperatures determines the Arrhenius activation energy for use-condition extrapolation
• Weibull analysis: Fitting failure data to Weibull distributions enables prediction of failure rates and early failure percentiles
• Monte Carlo simulation: For complex systems with multiple failure mechanisms, simulation techniques predict system reliability
• Physics of failure modeling: Detailed mechanism understanding enables modeling degradation trajectories

Conservative extrapolation requires attention to potential mechanism changes at lower stress, adequate sample sizes for statistical confidence, and recognition of field factors not represented in laboratory testing.

Margin Allocation

Accounting for aging in the design phase:

• End-of-life parameters: Design to meet specifications with aged device parameters, not fresh device values
• Simulation with aging models: Include device aging models in circuit simulation to verify operation after degradation
• Worst-case corners: Define process corners that include both manufacturing variation and aging effects
• Temperature derating: Reduce stress levels for high-temperature applications to extend lifetime

Layout Practices

Layout affects reliability in multiple ways:

• Matching for symmetric aging: Matched devices should experience identical stress conditions to degrade symmetrically
• Metal current density: Layout must ensure all interconnects operate within electromigration limits
• Via redundancy: Multiple vias at every connection protect against single via failures
• Thermal management: Layout affects local temperature; hot spots accelerate degradation
• Guard rings: Protection structures prevent contamination and radiation effects

Circuit Techniques

Some circuit techniques inherently provide reliability benefits:

• Calibration and trimming: Circuits that can be calibrated during operation can compensate for parametric drift
• Self-healing architectures: Redundancy and voting logic can tolerate single-point failures
• Built-in self-test: On-chip diagnostics can detect degradation before specifications are violated
• Stress monitoring: On-chip sensors can track temperature and voltage to estimate remaining life
• Graceful degradation: Designing for reduced performance rather than catastrophic failure when aging occurs