Electronics Guide

Basic Circuit Operation

In the common-emitter configuration, the input signal is applied to the base, the output is taken from the collector, and the emitter serves as the common terminal (typically connected to ground, sometimes through a resistor). The transistor operates in its active region, where small changes in base current produce proportionally larger changes in collector current, yielding current gain (beta) and, through the collector load resistor, voltage gain.

The voltage gain of a basic CE stage is approximately:

Av = -gm x Rc = -(Ic/Vt) x Rc

where gm is the transconductance, Ic is the collector current, Vt is the thermal voltage (approximately 26mV at room temperature), and Rc is the collector resistance. The negative sign indicates phase inversion.

Biasing Techniques

Proper biasing establishes a stable DC operating point (Q-point) that allows the transistor to amplify signals without distortion. Several biasing schemes offer different trade-offs between stability and complexity:

• Fixed bias: A single resistor from supply to base provides base current. Simple but highly sensitive to transistor beta variations and temperature changes.
• Collector feedback bias: The base resistor connects to the collector rather than the supply. Provides negative feedback that improves stability, as increased collector current reduces collector voltage, which in turn reduces base current.
• Voltage divider bias: Two resistors form a voltage divider that sets the base voltage. When designed so the divider current is much larger than base current, this configuration provides excellent stability against beta variations.
• Emitter degeneration: Adding an unbypassed emitter resistor provides local negative feedback, stabilizing the operating point and reducing gain sensitivity to transistor parameters.

Voltage Divider Bias Design

For the voltage divider bias configuration with emitter resistor, the design procedure is:

1. Choose the desired collector current Ic based on gain and power requirements
2. Select emitter voltage Ve = Ic x Re, typically 1-2V to provide good stability
3. Calculate base voltage Vb = Ve + Vbe, where Vbe is approximately 0.7V
4. Choose divider current Id to be at least 10 times the base current for stability
5. Calculate R2 = Vb / Id and R1 = (Vcc - Vb) / Id
6. Select Rc to provide the desired collector voltage, typically Vcc/2 for maximum symmetric swing

The stability factor S, which indicates how much collector current changes with temperature-induced changes in Ico, is minimized when the emitter resistor is large and the base circuit impedance is low.

Small-Signal Analysis

For AC analysis, the transistor is replaced by its small-signal model. Key parameters include:

• Input impedance: Zin = R1 || R2 || (beta x (re + Re)), where re = Vt/Ie is the intrinsic emitter resistance
• Output impedance: Zout approximately equals Rc (neglecting Early effect)
• Voltage gain: Av = -Rc / (re + Re) for unbypassed emitter resistor, or Av = -gm x Rc for fully bypassed emitter
• Current gain: Ai = beta for the transistor stage

Bypassing the emitter resistor with a capacitor increases AC gain by eliminating the emitter degeneration for signal frequencies while maintaining DC stability.

Frequency Response Considerations

The frequency response of a CE amplifier is limited by several factors:

• Low-frequency cutoff: Determined by coupling and bypass capacitors, which must be large enough to present low impedance at the lowest signal frequency
• High-frequency cutoff: Limited by transistor junction capacitances (Cbe and Cbc) and the Miller effect, which multiplies Cbc by the voltage gain
• Miller effect: The effective input capacitance is Cin = Cbe + Cbc(1 + |Av|), significantly reducing bandwidth at high gains

The gain-bandwidth product (ft) of the transistor sets a fundamental limit: higher gain necessarily means lower bandwidth.

Circuit Characteristics

In the emitter follower, input is applied to the base, output is taken from the emitter, and the collector connects directly to the supply (common for AC signals). Key characteristics include:

• Voltage gain: Av = Re / (re + Re), which approaches unity for practical values of Re
• No phase inversion: Output follows input, hence the name "follower"
• High input impedance: Zin = beta x (re + Re), multiplying the emitter circuit impedance by beta
• Low output impedance: Zout = (Rs/beta) + re, dividing the source impedance by beta
• Current gain: Approximately equal to beta, providing power gain despite unity voltage gain

Buffer Applications

The emitter follower excels at buffering, preventing a load from affecting the source:

• Voltage buffer: Presents high impedance to the source while driving low-impedance loads
• Impedance transformation: Transforms high source impedance to low output impedance, essential before driving cables or low-impedance circuits
• Level shifting: The output is offset from input by approximately 0.7V (Vbe), useful for DC level adjustment
• Current boosting: Provides current gain to drive loads that would overload a preceding stage

Bootstrapping Techniques

Bootstrapping further increases the input impedance of an emitter follower by making the bias resistors appear larger for AC signals:

A capacitor couples the output (emitter) back to the junction of the bias resistors. Since the emitter follows the base, the voltage across the lower bias resistor remains nearly constant for AC signals, effectively removing it from the input impedance calculation. This technique can increase input impedance by a factor of 10 or more.

The bootstrap capacitor must be large enough to maintain constant voltage across it at the lowest signal frequency.

Push-Pull Emitter Followers

For applications requiring significant output current in both directions, complementary push-pull emitter followers use both NPN and PNP transistors:

• The NPN transistor sources current to the load during positive half-cycles
• The PNP transistor sinks current from the load during negative half-cycles
• Crossover distortion occurs near zero crossing where both transistors are off
• Bias diodes or a Vbe multiplier establish a small quiescent current to minimize crossover distortion

This configuration forms the output stage of most power amplifiers, combining low output impedance with high efficiency.

Circuit Operation

In the common-base configuration, the input signal is applied to the emitter, the output is taken from the collector, and the base is grounded for AC signals (via a bypass capacitor). The transistor operates as a current-controlled current source:

• Current gain (alpha): Slightly less than unity, typically 0.98-0.995, since alpha = beta / (1 + beta)
• Voltage gain: Av = gm x Rc = Rc/re, similar magnitude to CE but without phase inversion
• Low input impedance: Zin = re = Vt/Ie, typically just a few ohms to tens of ohms
• High output impedance: Very high due to Early effect, as the base grounding eliminates the feedback path from collector to input

High-Frequency Advantages

The CB configuration excels at high frequencies for several reasons:

• No Miller effect: The grounded base shields the input from the output voltage swing, eliminating Miller multiplication of Cbc
• Higher frequency response: Bandwidth approaches the transistor's ft, compared to ft/gain for the CE configuration
• Better isolation: Excellent reverse isolation prevents output signals from feeding back to the input
• Lower noise at RF: The input current noise source sees a lower source impedance

These advantages make the CB stage valuable in RF amplifiers and as the upper transistor in cascode configurations.

Input Matching Considerations

The low input impedance of the CB stage can be both an advantage and a challenge:

• Current source driving: Ideal when driven by a current source, as in a cascode configuration
• 50-ohm matching: At moderate currents, the input impedance naturally approaches 50 ohms, simplifying RF matching
• Emitter degeneration: Adding an unbypassed emitter resistor increases input impedance: Zin = re + Re
• Transformer matching: Impedance transforming networks can match higher source impedances to the CB input

Applications

Common-base stages find use in:

• RF amplifiers: Where high-frequency performance and isolation are paramount
• Cascode upper stage: Providing voltage gain while the CE lower stage provides transconductance
• Current buffers: Converting voltage signals to current with low input impedance
• Transimpedance stages: Converting current (from photodiodes, for example) to voltage with wide bandwidth

Common-Source Amplifier

The common-source (CS) configuration provides voltage gain with very high input impedance:

• Voltage gain: Av = -gm x Rd, where gm is the FET transconductance
• Input impedance: Extremely high, limited by gate leakage (MOSFETs) or gate-source junction (JFETs), often exceeding 10^12 ohms for MOSFETs
• Output impedance: Approximately Rd in parallel with the FET's output resistance (1/gds)
• Phase inversion: 180 degrees, same as common-emitter

The transconductance of a FET depends on the drain current: gm = 2 x sqrt(Id x Idss) / Vp for JFETs, and gm = sqrt(2 x K x Id) for MOSFETs, where K is the device transconductance parameter.

FET Biasing Methods

FET biasing differs from BJT biasing because gate current is negligible:

• Self-bias (source resistor): The source resistor develops a voltage that reverse-biases the gate-source junction. For a JFET: Vgs = -Id x Rs
• Voltage divider bias: A resistive divider sets the gate voltage; the source resistor provides degeneration. Works well for enhancement-mode MOSFETs
• Fixed bias: A separate negative supply biases the gate. Provides precise control but requires additional supply
• Drain feedback bias: Resistor from drain to gate provides negative feedback, improving stability

The wide variation in FET parameters (especially Idss and Vp) requires biasing schemes that accommodate this spread or selection of matched devices.

Source Follower (Common-Drain)

The source follower provides voltage buffering with near-unity gain:

• Voltage gain: Av = gm x Rs / (1 + gm x Rs), approaching unity for large gm x Rs
• Input impedance: Extremely high, same as common-source (limited by gate leakage)
• Output impedance: Zout = 1/gm || Rs, typically a few hundred ohms
• No phase inversion: Output follows input

The source follower's output impedance is higher than that of an emitter follower because FET transconductance is generally lower than BJT gm at similar currents. However, the virtually infinite input impedance makes it valuable for high-impedance sources.

JFET vs MOSFET Considerations

The choice between JFET and MOSFET affects design decisions:

• JFETs: Depletion-mode operation (conduct at Vgs = 0), lower input capacitance, lower 1/f noise, excellent for low-noise preamplifiers
• MOSFETs: Available in both enhancement and depletion modes, higher transconductance possible, susceptible to gate oxide damage from ESD
• Parameter spread: JFETs show significant unit-to-unit variation; matched pairs are often required for differential stages
• Gate protection: MOSFETs require protection diodes or careful handling to prevent gate oxide breakdown

Circuit Characteristics

• Voltage gain: Av = gm x Rd, similar to common-source but without phase inversion
• Current gain: Approximately unity
• Input impedance: Low, approximately 1/gm, making it suitable for current-mode inputs
• Output impedance: High, comparable to common-source

RF and High-Frequency Applications

The common-gate stage offers the same high-frequency advantages as common-base:

• No Miller effect: Gate grounding eliminates Miller multiplication
• Wide bandwidth: Frequency response extends close to ft
• Excellent isolation: Output variations do not feed back to input
• Impedance matching: The 1/gm input impedance can be designed to match transmission line impedances

Common-gate stages frequently appear in RF low-noise amplifiers and as the upper device in cascode configurations.

Cascode Circuit Operation

In a BJT cascode, the lower transistor operates in common-emitter mode, providing transconductance (gm), while the upper transistor operates in common-base mode, providing voltage gain. The collector of the lower transistor connects to the emitter of the upper transistor:

• The CE transistor converts input voltage to current with high input impedance
• The CB transistor provides a low-impedance load to the CE collector, minimizing Miller effect
• The output is taken from the CB collector, which has very high impedance

Performance Advantages

The cascode offers several compelling advantages:

• Reduced Miller effect: The CE stage sees only a small voltage swing at its collector (the low impedance of the CB emitter), dramatically reducing effective input capacitance
• Extended bandwidth: With Miller effect minimized, bandwidth approaches that of a CB stage while maintaining the high input impedance of a CE stage
• Higher output impedance: The cascoded output impedance can exceed 1M ohm, beneficial for current sources and high-gain stages
• Improved isolation: The CB stage shields the input from output variations, improving reverse isolation
• Higher gain: The combination of high transconductance and high output impedance yields very high voltage gain

Cascode Biasing

Biasing the cascode requires establishing proper operating points for both transistors:

• The base of the CB transistor is held at a fixed voltage (typically 1-2 Vbe above the CE collector voltage)
• This voltage sets the CE collector voltage, which must keep the CE transistor in the active region
• A bypass capacitor on the CB base ensures AC grounding
• The CE transistor is biased conventionally using voltage divider or other techniques

The voltage dropped across the cascode structure reduces available output swing, a consideration in low-voltage designs.

Folded Cascode Variant

The folded cascode uses complementary transistors (NPN with PNP, or NMOS with PMOS) to reduce the voltage headroom requirement:

• The current flows "down" through the input device and "up" through the cascode device
• This allows operation with lower supply voltages
• Commonly used in integrated circuit operational amplifiers
• Requires careful matching of current levels between the two branches

Darlington Pair

The Darlington pair connects two transistors so that the emitter of the first drives the base of the second:

• Current gain: The overall beta equals beta1 x beta2, potentially exceeding 10,000
• Input impedance: Very high, as the already-high input impedance of the first transistor is multiplied by the second transistor's beta
• Vbe requirement: Approximately 1.4V (two Vbe drops), which is a significant fraction of low supply voltages
• Saturation voltage: Higher than a single transistor due to the cascaded structure
• Speed: Limited by the charge stored in the first transistor's base, requiring a speed-up resistor for fast switching

Darlington pairs are available as integrated devices and are widely used in power amplifier output stages and high-gain switching applications.

Sziklai Pair (Complementary Feedback Pair)

The Sziklai pair (also called the complementary Darlington) uses complementary transistors—typically an NPN driver and a PNP output (or vice versa):

• Current gain: Similar to Darlington, approximately beta1 x beta2
• Vbe requirement: Only one Vbe drop (approximately 0.7V), as the second transistor's base-emitter junction subtracts from the first
• Saturation voltage: Lower than Darlington, as the output transistor can fully saturate
• Thermal tracking: Better than Darlington because both junctions are in the signal path but with opposite temperature coefficients
• Output polarity: Appears as the same polarity as the input transistor (NPN input gives NPN-like behavior)

The Sziklai pair is often preferred in power amplifier output stages where low saturation voltage and good thermal behavior are important.

Super-Beta Transistors and Compound Input Stages

Some applications require extremely high input impedance or low bias current:

• Super-beta transistors: Specially fabricated devices with beta exceeding 1000, but with reduced breakdown voltage and Early voltage
• Compound input stages: Combining a super-beta input transistor with a conventional transistor in a cascode or Darlington arrangement
• FET-BJT combinations: JFET or MOSFET input feeding a BJT provides high impedance with BJT-level transconductance

These techniques are essential for instrumentation amplifiers and precision operational amplifiers requiring picoampere-level input bias currents.

Current Mirror Loads

While not a compound input configuration, current mirror loads are essential for maximizing single-stage gain:

• A current mirror provides an active load with very high dynamic resistance
• This maximizes voltage gain: Av = gm x (ro1 || ro2), where ro values are the transistor output resistances
• Gains of 1000 or more are achievable from a single stage with current mirror load
• Current mirrors also simplify biasing in differential pair configurations

Temperature Effects on BJTs

Several BJT parameters vary with temperature:

• Vbe: Decreases by approximately 2mV per degree Celsius at constant current. This is the primary cause of thermal drift in bias circuits.
• Beta: Increases with temperature, typically 0.5-1% per degree Celsius
• Leakage current (Icbo): Doubles approximately every 10 degrees Celsius
• Saturation voltage: Decreases with temperature

These variations can cause the operating point to shift dramatically over the operating temperature range, potentially causing distortion or device failure.

Thermal Runaway

Thermal runaway is a destructive positive feedback mechanism:

1. Increased current causes increased power dissipation
2. Power dissipation increases junction temperature
3. Higher temperature reduces Vbe, which increases current
4. The process accelerates until the device is destroyed

Thermal runaway is prevented by ensuring negative thermal feedback through circuit design:

• Emitter resistors: Create a voltage drop that opposes current increases
• Adequate heat sinking: Keeps junction temperature low
• Limiting ambient temperature: Designing for worst-case conditions
• Current limiting: Preventing excessive current under any condition

Bias Stability Techniques

Several techniques ensure stable biasing over temperature:

• Voltage divider with emitter degeneration: The "stiff" base voltage combined with emitter feedback provides stability. The stability factor S = (1 + Rb/Re) / (1 + Rb/(beta x Re)) approaches unity for large emitter resistors.
• Diode compensation: A diode in the bias network tracks Vbe changes, providing first-order compensation
• Transistor as temperature sensor: Using a matched transistor to sense temperature and adjust bias
• Negative temperature coefficient resistors: NTC thermistors in the bias network can provide temperature compensation

FET Thermal Considerations

FETs exhibit different thermal behavior than BJTs:

• Threshold voltage (Vth): Decreases with temperature, typically -2mV per degree Celsius for MOSFETs
• Transconductance: Decreases with temperature due to reduced carrier mobility
• Zero temperature coefficient point: FETs have a bias point where drain current is constant with temperature; operating here eliminates thermal drift
• No thermal runaway: The negative temperature coefficient of transconductance provides inherent stability at high currents

The zero TC operating point occurs at a specific Vgs and Id that depends on device parameters, typically at moderate current levels.

Thermal Design in Power Stages

Power amplifier output stages require careful thermal management:

• Heat sinking: Proper thermal resistance from junction to ambient must be calculated to keep junction temperature within limits
• Thermal coupling: Bias transistors should be thermally coupled to output transistors to track temperature changes
• Safe operating area (SOA): The combination of voltage and current must remain within the device's SOA at all temperatures
• Thermal protection: Over-temperature shutdown circuits prevent destruction if cooling fails

The thermal resistance from junction to case (Rth-jc), case to sink (Rth-cs), and sink to ambient (Rth-sa) sum to determine the total thermal resistance. Maximum power dissipation is: Pmax = (Tj-max - Ta) / (Rth-jc + Rth-cs + Rth-sa).

BJT Configuration Comparison

FET Configuration Comparison

Application Guidelines

• Voltage amplification: Common-emitter or common-source with emitter/source degeneration for gain stability
• Impedance buffering: Emitter follower or source follower
• High-frequency amplification: Common-base, common-gate, or cascode
• High input impedance: FET input stages or bootstrapped BJT stages
• Low output impedance: Emitter follower, possibly with compound configurations for high current
• Wide bandwidth with high gain: Cascode configuration
• High-current drive: Darlington or Sziklai pairs

Requirements Analysis

1. Define voltage gain requirement (including tolerance)
2. Specify input and output impedance requirements
3. Determine bandwidth (low and high frequency limits)
4. Establish noise requirements if applicable
5. Define supply voltage and power constraints
6. Consider temperature range and stability requirements

Topology Selection

1. Match basic configuration to impedance and gain requirements
2. Consider compound configurations if basic topologies are insufficient
3. Evaluate BJT vs FET based on impedance and noise requirements
4. Consider cascode for bandwidth extension

DC Design

1. Select operating current based on transconductance requirements
2. Choose bias topology for required stability
3. Calculate resistor values for the operating point
4. Verify thermal stability and operating margins

AC Design

1. Calculate small-signal parameters (gm, re, ro)
2. Determine coupling and bypass capacitor values
3. Verify gain and impedance meet requirements
4. Analyze frequency response

Verification

1. Simulate the design using SPICE or similar tools
2. Check performance over temperature range
3. Verify performance with worst-case component tolerances
4. Build prototype and measure actual performance