Electronics Guide

Gain Distribution

The total gain of a multi-stage amplifier equals the product of individual stage gains. However, the optimal distribution of gain among stages depends on several factors:

• Noise considerations: The first stage dominates overall noise performance, so it should have high gain to overcome noise contributions from subsequent stages
• Bandwidth constraints: The gain-bandwidth product limits each stage, requiring careful allocation to achieve the desired overall bandwidth
• Headroom requirements: Later stages must handle larger signal swings without clipping, potentially limiting their gain
• Stability margins: Excessive gain in any single stage may compromise stability, especially with feedback

Interstage Coupling

The method of coupling between stages affects both DC and AC performance:

• Direct coupling: Preserves DC information and extends low-frequency response to DC, but requires careful bias design and may accumulate DC offsets
• Capacitive coupling: Blocks DC offsets and simplifies biasing, but introduces low-frequency roll-off and potential phase shift
• Transformer coupling: Provides impedance transformation and DC isolation, but adds cost, size, and frequency limitations

The coupling time constant in capacitively coupled stages sets the low-frequency −3 dB point. For a coupling capacitor C between a source resistance R_S and a load resistance R_L, the cutoff frequency is:

f = 1 / (2πC(R_S + R_L))

DC Operating Point Design

In direct-coupled amplifiers, the DC operating points of all stages are interdependent. Design strategies include:

• Level shifting: Using diodes, zener diodes, or resistor networks to adjust DC levels between stages
• Complementary stages: Alternating NPN and PNP transistors (or N-channel and P-channel FETs) to naturally accommodate level shifts
• DC feedback: Using negative feedback around multiple stages to stabilize the overall DC operating point

Maximum Power Transfer

For maximum power transfer from source to load, the load impedance should equal the complex conjugate of the source impedance. In the purely resistive case, this means R_load = R_source. This condition delivers the source's entire available power to the load, but at an efficiency of only 50 percent: an equal power is dissipated in the source resistance.

Matching networks can transform impedances using:

• L-networks: Two reactive elements providing a single Q value and limited bandwidth
• Pi and T networks: Three elements offering independent control of Q and transformation ratio
• Transmission line transformers: Wound or printed structures for wideband matching at radio frequencies

Voltage Transfer Optimization

For voltage amplifiers, maximum signal voltage (rather than power) transfer is often desired. This requires the load impedance to be much greater than the source impedance. In this case, nearly all the source voltage appears across the load, though power transfer is not maximized.

Practical implementations include:

• High input impedance stages: FET input stages, bootstrap circuits, or instrumentation amplifiers
• Buffer amplifiers: Unity-gain stages with high input impedance and low output impedance
• Active impedance transformation: Using feedback to modify effective input or output impedance

Noise Matching

For minimum noise figure, the source impedance should equal the optimum source impedance of the amplifier, which generally differs from both the conjugate match and the voltage transfer optimum. This noise match minimizes the combined effect of the amplifier's voltage and current noise sources.

The optimum source resistance for minimum noise is approximately R_opt = e_n / i_n, where e_n is the equivalent input voltage-noise density and i_n is the equivalent input current-noise density. Reactive components can be added to achieve the optimum complex source impedance.

Noise Sources in Amplifiers

Several distinct mechanisms contribute to amplifier noise:

• Thermal noise: Generated by random electron motion in resistors, with a voltage power spectral density of 4kTR (V²/Hz)
• Shot noise: Arising from discrete charge carriers crossing a junction, with a current power spectral density of 2qI (A²/Hz)
• Flicker (1/f) noise: Low-frequency noise with power spectral density inversely proportional to frequency, dominant in semiconductors below the corner frequency
• Burst (popcorn) noise: Random telegraph-like switching between discrete levels, caused by trapping centers

Noise Figure and Noise Factor

The noise factor F quantifies how much an amplifier degrades the signal-to-noise ratio, measured with the source at the standard reference temperature of 290 K:

F = SNR_in / SNR_out

Noise figure (NF) is the noise factor expressed in decibels: NF = 10 log₁₀(F). An ideal noiseless amplifier has NF = 0 dB. Practical amplifiers always add some noise, resulting in NF greater than 0 dB.

Cascaded Noise Figure

For cascaded stages, the Friis formula gives the overall noise factor:

F_total = F₁ + (F₂ − 1)/G₁ + (F₃ − 1)/(G₁G₂) + …

where F_i and G_i are the noise factor and available power gain of stage i, both expressed as ratios rather than in decibels. This formula reveals that the first stage dominates overall noise performance, especially if it has high gain. Subsequent stages contribute progressively less as their noise is divided by the accumulated gain of preceding stages. This principle guides the design of low-noise amplifier chains.

Low-Noise Design Techniques

Practical strategies for minimizing amplifier noise include:

• Device selection: Choose devices with low noise voltage and current for the given source impedance
• Operating point optimization: Bias devices at currents that minimize noise for the signal bandwidth
• Source impedance matching: Transform the source to present the optimum noise impedance to the amplifier
• Bandwidth limiting: Restrict bandwidth to only what the signal requires, as noise integrates over bandwidth
• Parallel devices: Using n devices in parallel reduces voltage noise by a factor of √n while raising current noise by the same factor, which suits low source impedances

Types of Distortion

• Harmonic distortion: Generation of frequency components at integer multiples of the input frequency, characterized by THD (Total Harmonic Distortion)
• Intermodulation distortion: Generation of sum and difference frequencies when multiple signals are present
• Crossover distortion: Occurs in push-pull stages when transitioning between devices, causing discontinuities near zero crossing
• Slew-induced distortion: Results when the amplifier cannot change output voltage fast enough to follow the input
• Thermal distortion: Caused by signal-dependent power dissipation changing device parameters during the signal cycle

Negative Feedback

Negative feedback is the primary tool for reducing distortion. By comparing output to input and correcting errors, feedback reduces distortion by a factor approximately equal to (1 + loop gain).

For an amplifier with open-loop distortion D_o and loop gain T, compared at the same output amplitude:

D_closed-loop = D_o / (1 + T)

However, feedback introduces trade-offs:

• Reduces gain by the same factor it reduces distortion
• Can cause instability if not properly compensated
• May introduce transient intermodulation distortion if slew rate is insufficient

Feedforward Correction

Feedforward error correction subtracts the distortion generated by the main amplifier using an auxiliary path. Unlike feedback, feedforward does not affect stability and can achieve very high linearity. The technique requires:

• Precise amplitude and phase matching between paths
• A highly linear error amplifier
• Careful delay matching across frequency

Feedforward was long the standard linearizer for multicarrier cellular base-station amplifiers, where a feedback loop cannot be closed around a high-power RF stage at the required bandwidth. Its efficiency is poor, however, because the error amplifier draws power of its own and the delay line and coupler after the main amplifier waste part of its output. Digital predistortion, described next, has since displaced it in most such designs.

Predistortion

Predistortion introduces complementary nonlinearity before the amplifier to cancel its inherent distortion. The predistorter's transfer characteristic is the inverse of the amplifier's nonlinearity.

• Analog predistortion: Uses diodes or transistors to generate the inverse characteristic, offering low cost and wide bandwidth but limited accuracy and poor adaptability
• Digital predistortion (DPD): Implements the inverse function in DSP, with coefficients adapted from a feedback observation of the output. Modern DPD models the amplifier's memory effects (frequency-dependent nonlinearity) and can improve the adjacent-channel power ratio by tens of decibels

Digital predistortion is now standard in cellular base-station power amplifiers, where it lets an efficient but nonlinear amplifier meet the strict spectral-mask and error-vector-magnitude requirements of modern modulation schemes such as those used in LTE and 5G NR.

Class Selection and Bias Optimization

The amplifier operating class significantly affects distortion:

• Class A: Device conducts throughout the signal cycle, offering lowest distortion but lowest efficiency
• Class B: Each device of a push-pull pair conducts for half the cycle, efficient but prone to crossover distortion
• Class AB: Compromise between A and B, in which a small quiescent current makes both devices conduct around the crossover region, requiring careful bias

Bias current in Class AB stages should be optimized to minimize crossover distortion while maintaining acceptable quiescent power dissipation.

Gain-Bandwidth Trade-offs

For an amplifier whose response is dominated by a single pole, such as an internally compensated voltage-feedback operational amplifier, the product of gain and bandwidth is approximately constant: reducing the closed-loop gain increases the bandwidth proportionally. The gain-bandwidth product (GBW) is a fundamental figure of merit for amplifying devices; its counterpart for a transistor is the transition frequency f_T, at which the short-circuit current gain falls to unity.

For a single-pole system with DC gain A₀ and bandwidth f_{3 dB}:

GBW = A₀ × f_{3 dB}

Shunt and Series Peaking

Inductive peaking extends bandwidth by resonating with parasitic capacitances:

• Shunt peaking: An inductor in series with the load resistor resonates with load capacitance. A maximally flat response yields roughly a 70 percent bandwidth increase; pushing the inductor larger trades flatness for up to about 85 percent extension with visible gain peaking
• Series peaking: An inductor placed between stages isolates the driving stage's output capacitance from the following stage's input capacitance, dividing the total load and extending bandwidth
• Bridged T-coil peaking: A center-tapped, mutually coupled inductor with a small bridging capacitor that holds the input impedance constant and resistive. It is the most effective of these techniques, achieving a bandwidth-extension factor of about 2.8 (2√2 for a maximally flat magnitude response) over an unpeaked load

The optimum peaking inductor value depends on the load resistance R and capacitance C and on the desired response flatness. For shunt peaking it is conveniently expressed through the dimensionless ratio L/(R²C), which sets the network's damping: a ratio of about 0.41 gives the maximally flat magnitude response and its 1.72-fold bandwidth, while about 0.71 gives the widest bandwidth, about 1.85 times the unpeaked value, at the cost of roughly 1.5 dB of peaking. Practical on-chip inductors must also account for their own parasitic resistance and self-resonance.

Distributed Amplification

Distributed amplifiers absorb device capacitances into artificial transmission lines, achieving bandwidths from DC to many gigahertz. Multiple devices are connected with inductors forming input and output transmission lines. Each device contributes gain while its capacitance becomes part of the line.

Key characteristics:

• Bandwidth limited primarily by transmission line cutoff
• Gain proportional to the number of stages in the lossless ideal; losses in the artificial lines set an optimum number beyond which added stages no longer help
• Flat gain and good impedance match over wide bandwidth
• Higher power consumption than lumped designs

Cascode and Current-Mode Techniques

The cascode configuration reduces Miller-effect multiplication of the input capacitance by isolating the input device from the output voltage swing:

• A common-emitter/source input stage provides transconductance
• A common-base/gate output stage provides voltage gain and isolation
• Miller multiplication of the input device's feedback capacitance falls from (1 + g_mR_L) in a plain common-emitter stage to roughly 2, because the common-base/gate device presents a low load of about 1/g_m that holds the input device's voltage gain near unity

Current-mode circuits avoid voltage-swing-related bandwidth limitations by processing signals as currents. Current conveyors and current-feedback amplifiers exploit this principle. A current-feedback amplifier's closed-loop bandwidth is set chiefly by its feedback resistor rather than by its gain, so it largely escapes the constant gain-bandwidth trade-off of a voltage-feedback design.

AGC Loop Fundamentals

An AGC system forms a feedback loop comprising:

• Variable gain amplifier (VGA): Provides signal amplification with gain controlled by a control voltage or current
• Detector: Extracts amplitude information from the signal (peak, average, or RMS)
• Loop filter: Determines attack and decay time constants, smooths detector output
• Reference: Sets the desired output level

The loop adjusts VGA gain to maintain detector output equal to the reference level.

AGC Time Constants

AGC response characteristics are crucial for proper operation:

• Attack time: How quickly gain reduces when input increases; fast attack prevents overload but may cause distortion on transients
• Decay time: How quickly gain increases when input decreases; slow decay prevents gain pumping but may cause signal loss in fades
• Hold time: Delay before gain begins to increase after input decrease

Time constants must be chosen based on signal characteristics. Audio AGC typically uses attack times of 1 to 10 ms and decay times of 100 ms to 1 s. RF AGC may require a response measured in microseconds.

AGC Range and Dynamic Range

The AGC range defines the span of input signal levels over which output remains constant. This is limited by:

• Minimum and maximum VGA gain
• Detector sensitivity and saturation
• Noise floor at maximum gain
• Distortion at minimum gain (maximum input)

Well-designed AGC systems achieve 60 to 100 dB of gain range while maintaining acceptable noise and distortion.

VGA Architectures

• Multiplier-based VGA: Uses an analog multiplier with the signal and control voltage as inputs, giving gain linear in the control voltage; an exponential converter ahead of the control input makes the gain linear in decibels instead
• Resistive divider VGA: Varies effective feedback resistance using FETs or other variable elements
• Current-steering VGA: Splits signal current between output and ground using differential pairs; the exponential characteristic of bipolar transistors gives approximately exponential (dB-linear) gain control
• Digitally controlled VGA: Uses switched resistor networks or attenuator stages for discrete gain steps

Gain Control Characteristics

VGAs may have a linear or an exponential (dB-linear) relationship between gain and control voltage:

• Linear VGA: Gain proportional to control voltage. The circuit is simpler, but a given step in control voltage changes the gain by more decibels at low gain settings than at high ones, so the gain of the AGC loop, and with it the loop's settling time, varies with the input signal level
• Exponential VGA: Gain in decibels proportional to control voltage, so a given control step changes the gain by the same number of decibels at any setting

The gain control law therefore sets the AGC loop dynamics. With an exponential VGA the small-signal loop gain stays constant across the input range, and pairing it with a logarithmic detector, whose output is also in decibels, keeps the loop linear in decibels even for large steps in input level. That constant response is why dB-linear VGAs are generally preferred for AGC.

VGA Performance Parameters

Key specifications for VGA selection:

• Gain range: Ratio of maximum to minimum gain, typically 40 to 80 dB
• Gain accuracy: Deviation from ideal gain law, important for measurement applications
• Bandwidth versus gain: How bandwidth varies with gain setting
• Noise figure versus gain: Noise figure typically rises at lower gain settings
• Distortion versus gain: May vary significantly across the gain range
• Gain settling time: How quickly gain stabilizes after control voltage change

Basic Differential Pair

The differential pair consists of two matched transistors with joined emitters (or sources) connected to a current source. The configuration provides:

• Differential gain: Amplification of the difference between inputs
• Common-mode rejection: Attenuation of signals appearing equally on both inputs
• High input impedance: Especially with FET implementations
• Balanced outputs: Differential output signal available between collectors/drains

Differential Gain Optimization

The differential-mode voltage gain (differential input to differential output) for a BJT pair is:

A_v(diff) = g_mR_C = (I_C / V_T)R_C

where g_m is the transconductance, R_C is the collector resistance, I_C is the per-device collector current, and V_T is the thermal voltage (approximately 26 mV at room temperature). Because I_CR_C is the DC voltage across each collector resistor, the gain of a resistively loaded pair equals that voltage divided by V_T: a 1 V drop gives a differential gain of about 38. Raising the current and raising the resistance therefore run into the same limit, the available supply headroom.

Gain can be increased by:

• Increasing collector current (raises g_m and lowers input voltage noise, but costs power, raises base current and current noise, and enlarges the DC drop across R_C)
• Increasing load resistance (limited by voltage headroom and bandwidth)
• Using active loads (current mirrors provide high effective resistance)
• Adding gain stages (cascading differential pairs)

Input Stage Configurations

Different input configurations suit different applications:

• BJT differential pair: Low voltage noise and the highest g_m per unit current, but a narrow linear input range and appreciable input bias and current noise
• JFET differential pair: Very high input impedance, low current noise, moderate voltage noise
• MOSFET differential pair: High impedance, integrated circuit compatible, higher voltage noise than a BJT pair, particularly flicker noise
• Composite input: Combines advantages, such as JFET input with BJT cascode

CMRR Fundamentals

CMRR is defined as the ratio of differential gain to common-mode gain:

CMRR = A_d / A_cm

Expressed in decibels:

CMRR(dB) = 20 log₁₀(A_d / A_cm)

Good instrumentation amplifiers achieve CMRR of 100 to 120 dB at DC, declining at higher frequencies.

Factors Limiting CMRR

Several factors degrade common-mode rejection:

• Device mismatch: Differences in transistor parameters between the two sides of the differential pair
• Resistor mismatch: Unequal load or feedback resistors convert common-mode to differential
• Tail current source impedance: Finite impedance allows common-mode signals to modulate tail current
• Power supply rejection: Supply variations can appear as common-mode input
• Parasitic capacitance imbalance: Causes CMRR to decrease with frequency

CMRR Enhancement Techniques

• Precision resistor matching: Use matched resistor networks or laser-trimmed resistors. The resistor-limited CMRR of a difference amplifier with gain G is roughly (1 + G) divided by the fractional ratio mismatch, so 0.01 percent ratio matching yields about 86 dB at unity gain and about 101 dB at a gain of 10
• High-impedance current sources: Cascode current sources can present an output impedance of 10 MΩ or more at low frequencies, minimizing common-mode gain
• Common-mode feedback: Active feedback loop that senses and corrects common-mode level
• Instrumentation amplifier topology: The three-op-amp configuration applies differential gain in its input stage while passing common-mode voltage at unity gain, so the residual mismatch of the output difference stage is divided by that gain; a single gain resistor sets the gain without disturbing the rejection
• Trimming and calibration: Adjust resistor values or offset to null common-mode gain
• Auto-zero techniques: Periodically measure and subtract offset and common-mode errors

Frequency-Dependent CMRR

CMRR typically decreases with frequency due to:

• Phase mismatch between signal paths
• Capacitive imbalances becoming significant
• Reduced loop gain in feedback configurations

Maintaining high-frequency CMRR requires careful layout with matched trace lengths, guard rings, and shield connections. For demanding applications, fully differential signal paths from sensor to ADC may be necessary.

Component Selection

• Transistors: Match parameters for differential pairs; consider f_T, noise figure, and safe operating area
• Resistors: Use low temperature coefficient types for gain-setting; consider noise contribution of high-value resistors
• Capacitors: Select appropriate dielectric for the frequency range; avoid high-permittivity ceramics such as X7R, whose piezoelectric response turns vibration into noise, in sensitive circuits
• Integrated amplifiers: Operational amplifiers provide matched components and stable performance

Layout and Grounding

Physical implementation affects performance:

• Keep sensitive traces short and away from noisy signals
• Use ground planes to reduce inductance and shield against interference
• Match trace lengths and parasitic capacitances in differential paths
• Separate analog and digital grounds, joining at a single point
• Bypass supply pins with appropriate capacitors close to the device

Testing and Verification

Thoroughly characterize amplifier performance:

• Measure gain, bandwidth, and phase response across the frequency range
• Characterize noise spectral density and integrated noise
• Test harmonic and intermodulation distortion at various signal levels
• Verify CMRR using matched-amplitude, in-phase test signals
• Check stability with varying loads and temperatures