Electronics Guide

Digital-to-Analog Converter Based Generators

Digital-to-analog converters (DACs) provide flexible on-chip signal generation:

• Direct digital synthesis: Generate arbitrary waveforms by clocking digital samples through a DAC, enabling sinusoids, ramps, and complex modulated signals
• Sigma-delta modulators: Single-bit output simplifies the analog reconstruction while providing high resolution after filtering
• Current-steering DACs: Fast settling enables high-frequency signal generation with good spectral purity
• R-2R ladder DACs: Area-efficient implementation suitable for moderate resolution test signals

The key challenge is achieving sufficient spectral purity for testing high-performance analog circuits. The test generator must be significantly better than the circuit under test to avoid masking actual defects with stimulus imperfections.

Oscillator-Based Stimulus Generation

On-chip oscillators provide simple yet effective test signal sources:

• Ring oscillators: Generate square waves at a frequency set by the number of stages N and the delay t_d of each, f = 1 / (2Nt_d); compact, but their frequency drifts with supply voltage and temperature
• LC oscillators: Provide cleaner sinusoidal outputs but require inductors that consume significant area
• Relaxation oscillators: Generate triangular and square waves using capacitor charging and threshold detection
• Crystal oscillators: When crystals are already present for system timing, they provide extremely stable reference frequencies

Frequency dividers and phase-locked loops can derive multiple test frequencies from a single oscillator, enabling multi-tone testing for intermodulation distortion measurement.

Pseudo-Random Sequence Generators

Linear feedback shift registers (LFSRs) generate pseudo-random binary sequences useful for analog testing:

• Noise-like spectra: Low-pass filtering an LFSR output yields a band-limited, noise-like stimulus whose spectrum is nearly flat well below the clock frequency, a broadband excitation for frequency-response measurement
• Spread spectrum signals: Enable correlation-based measurements that reject interference
• Multi-tone approximation: A clocked sequence of length 2ⁿ − 1 has discrete spectral lines spaced f_clk / (2ⁿ − 1) apart, so a long sequence exercises many frequencies at once
• Deterministic repeatability: Unlike true random sources, LFSR sequences are perfectly repeatable for correlation analysis

The mathematical properties of maximal-length sequences enable elegant analysis. Mapped to values of +1 and −1, a maximal-length sequence of length N = 2ⁿ − 1 has a periodic autocorrelation of N at zero lag and −1 at every other lag, which is nearly an ideal impulse. Cross-correlating a linear circuit's response with the stimulus therefore recovers the circuit's impulse response, and with it the frequency response, while uncorrelated noise and interference average away.

Charge Injection and Current Pulse Generation

Simple switching circuits can generate precise charge packets and current pulses:

• Switched capacitor injection: Transfer known charge packets to test charge-sensitive circuits
• Current mirror pulses: Generate calibrated current steps using switched current mirrors
• Edge-based stimulus: Fast digital transitions provide step and impulse approximations for transient testing
• Ratiometric stimulus: Generate test signals as precise ratios of reference values using matched components

Analog-to-Digital Converter Based Analysis

On-chip ADCs enable direct digitization of analog responses:

• Successive approximation ADCs: Moderate speed and resolution suitable for many DC and low-frequency measurements
• Sigma-delta ADCs: High resolution at lower speeds for precision parametric measurements
• Flash ADCs: High speed for capturing transient responses and high-frequency signals
• Time-interleaved ADCs: Achieve high sample rates by combining multiple lower-speed converters

Once digitized, standard digital signal processing can compute gain, offset, distortion, and other performance metrics. A common rule of thumb is that the measuring converter should resolve at least two bits finer than the smallest error the test must detect, so that its own quantization and nonlinearity consume only a small part of the error budget. When the on-chip ADC is no better than the circuits it measures, or is itself part of the path under test, its errors must be characterized or calibrated out before its readings can be trusted.

Window Comparator Analysis

Simple comparators provide efficient go/no-go testing:

• Upper and lower limit detection: Verify signals remain within specification windows
• Peak detection: Capture maximum signal excursions using diode-capacitor peak detectors
• Threshold crossing timing: Measure when signals cross reference levels for timing parameter extraction
• Programmable thresholds: DAC-generated reference levels enable flexible limit setting

Window comparators consume minimal area and power while providing immediate pass/fail indication. For many production test applications, this binary output suffices.

Amplitude and RMS Detection

Measuring signal amplitude is fundamental to many analog tests:

• Rectifier-based detectors: Full-wave rectification followed by filtering provides average amplitude
• True RMS detectors: Square, average, and square root operations yield RMS regardless of waveform shape
• Log-ratio amplifiers: Compute ratios directly in the logarithmic domain for gain measurements
• Synchronous detection: Multiply by reference and filter to extract amplitude and phase at specific frequencies

Synchronous detection using on-chip multipliers achieves excellent noise rejection by measuring only the coherent component at the stimulus frequency.

Phase and Frequency Measurement

Timing relationships reveal important performance characteristics:

• Phase detector circuits: XOR gates or multipliers produce outputs proportional to phase difference
• Time-to-digital converters: Count clock cycles or delay line taps between events for precise timing measurement
• Frequency counters: Count zero crossings over defined intervals to measure frequency
• Period averaging: Measure time for multiple cycles to improve frequency resolution

Analog Signature Principles

Converting analog responses to signatures involves several approaches:

• Digitized waveform signatures: Sample the analog response, compute a signature (CRC or checksum) over the digital samples
• Feature extraction signatures: Extract specific features (peaks, zero crossings, slopes) and encode them digitally
• Histogram signatures: Build amplitude histograms and compute statistical signatures from the distribution
• Spectral signatures: Compute frequency domain representations and signature the spectral content

The aim is a signature that stays within a predictable range for good circuits despite process and environmental variation, while moving outside that range for faulty ones.

Multiple Input Signature Registers

Multiple Input Signature Registers (MISRs) efficiently compress multiple bit streams:

• Parallel signature compression: The output bits of one or more ADCs feed the MISR inputs together on each clock
• Polynomial division: The LFSR structure performs polynomial division, creating a remainder that serves as the signature
• Aliasing probability: The probability that a faulty circuit produces the correct signature is approximately 2⁻ⁿ for an n-bit MISR, an estimate that assumes every error pattern is equally likely
• Multiple signatures: Capture intermediate signatures to improve fault isolation when failures occur

An MISR is exact to the bit: a change of one least significant bit in any sample alters the whole signature. Applied directly to raw ADC codes, it therefore cannot distinguish noise and normal process spread from a fault, because two good devices, or two runs on the same device, rarely produce identical codes. The tolerance-based approaches below address this.

Tolerance-Based Signature Analysis

Accommodating analog tolerances requires modified signature approaches:

• Range encoding: Encode ADC outputs as ranges rather than exact values before signature computation
• Differential signatures: Compute signatures on differences between channels, canceling common-mode variations
• Statistical signature windows: Define acceptable signature ranges based on process variation analysis
• Adaptive golden signatures: Update reference signatures based on measured good device populations

The tolerance window must be wide enough to pass good devices with normal variation but narrow enough to catch faulty devices with abnormal responses.

Oscillation Test Principles

The fundamental concept exploits the relationship between circuit parameters and oscillation frequency. By the Barkhausen criterion, a feedback loop sustains oscillation at the frequency where the loop gain magnitude is unity and the total phase shift around the loop is zero (equivalently, an integer multiple of 360 degrees):

• Loop gain condition: An amplifier configured with feedback oscillates at the frequency satisfying the Barkhausen criterion; for an inverting stage, the feedback network must supply the additional 180 degrees needed to bring the total loop phase to 360 degrees
• RC time constant: Oscillation frequency in RC oscillators directly reflects the RC product
• Transconductance measurement: Oscillator frequency depends on active device transconductance, enabling parameter extraction
• Filter characteristics: Converting filters to oscillators reveals their frequency response characteristics

Pass and fail limits come from a tolerance band on the oscillation frequency, typically set by Monte Carlo simulation across the expected spread of process and design parameters. A fault that moves the frequency outside the band is detected; one that leaves it inside is not.

Oscillation Test Implementation

Practical oscillation test requires additional circuitry:

• Feedback switching: Multiplexers reconfigure the circuit under test into an oscillator topology during test mode
• Start-up circuits: Ensure that oscillation begins reliably, rather than the loop settling into a stable latched or quiescent state
• Amplitude limiting: Control oscillation amplitude to keep the active devices out of heavy saturation, so that the frequency reflects the parameters under test
• Frequency counters: On-chip counters measure the oscillation frequency against a reference clock

A key advantage is that frequency measurement is inherently digital, and its precision grows with measurement time. A counter that counts a 100 kHz oscillation over a 10 ms gate accumulates 1,000 counts, so its ±1 count quantization limits resolution to 0.1 percent; a 100 ms gate improves that to 0.01 percent. Reciprocal counting does better in less time: counting a 100 MHz reference clock across 100 cycles of the same oscillation, which last 1 ms, accumulates 100,000 counts, a resolution of 0.001 percent.

Oscillation Test Applications

Various analog circuits are amenable to oscillation-based testing:

• Operational amplifiers: Test-mode switches rearrange the amplifier with an added feedback network into an oscillator; which amplifier parameters the frequency tracks depends on the configuration chosen
• Filters: Positive feedback around a second-order section makes it oscillate at or near its pole frequency, which sets the section's cutoff or center frequency
• Data converters: A feedback loop, in which a digital comparison of the output code steers current sources at the ADC input, forces the converter to oscillate around a selected code; the oscillation frequency reflects the code widths at that point, so stepping the selected code through the range yields differential and integral nonlinearity without a precision analog stimulus
• Analog multiplexers: Include in oscillator path to verify switch resistance and bandwidth

The configuration determines what an oscillation test measures. In the familiar relaxation (astable) connection, the amplifier charges a capacitor C through a resistor R and compares the capacitor voltage with a fraction β = R₂ / (R₁ + R₂) of its own output. With symmetric output levels, the period is

T = 2RC ln[(1 + β) / (1 − β)]

The gain-bandwidth product does not appear. The external network sets the frequency, and the amplifier enters only through secondary effects: finite slew rate lengthens each transition, while offset and asymmetric output levels shift the switching points. A relaxation connection therefore screens for gross faults and slew-rate defects rather than measuring gain-bandwidth product. To make the frequency track the amplifier's small-signal response, the added network must be arranged so that the amplifier's own frequency roll-off supplies a significant part of the loop phase shift.

The technique is particularly valuable for testing analog IP blocks embedded in large digital SoCs where external analog access is limited.

Limitations and Considerations

Oscillation testing has important limitations:

• Fault coverage: Not all analog faults affect oscillation frequency; some defects may escape detection
• Correlation to specifications: The relationship between oscillation frequency and datasheet parameters may be indirect
• Additional circuitry: Feedback switches and control logic add area and potentially affect normal operation
• Start-up time: Oscillators require settling time, which adds to test duration

Static Current Testing

Quiescent current measurement detects many fault types:

• IDDQ testing: Measure static supply current; elevated current indicates defects such as gate oxide shorts or bridging faults
• Multiple supply monitoring: Analog circuits often have separate analog and digital supplies requiring independent monitoring
• Bias current verification: Compare measured bias currents against expected values for each operating mode
• Leakage characterization: Identify excessive leakage that may indicate reliability concerns

Digital IDDQ testing works because a defect-free static CMOS circuit draws almost no quiescent current, so even a resistive bridge or gate-oxide defect that leaves the logic functioning correctly raises the current measurably. An analog circuit draws substantial bias current by design, and that current varies from die to die with process and temperature. Analog supply-current tests must therefore set their limits around a nonzero nominal value, and they detect a defect only when it moves the current outside the normal spread.

Dynamic Current Analysis

Time-varying current reveals additional information:

• Transient current signatures: Current waveforms during state transitions reflect circuit timing and drive capability
• AC current consumption: Measure current at various operating frequencies to verify frequency-dependent behavior
• Current spectrum analysis: Frequency content of supply current reveals oscillations, instabilities, or abnormal modulation
• Activity-dependent current: Correlate current consumption with circuit activity to identify abnormal dependencies

On-Chip Current Sensors

Various circuit techniques enable on-chip current measurement:

• Series sense resistors: Small resistors in the supply path create voltage drops proportional to current
• Current mirrors: Copy a scaled version of the supply current to a measurement circuit
• Hall effect sensors: Magnetic field sensing enables non-contact current measurement in high-current applications
• Built-in current sensors (BICS): Compact circuits that compare quiescent current against a threshold on-chip, usually through a sensing device in the supply or ground return that a bypass switch shorts out during normal operation

The challenge is measuring current without significantly impacting circuit performance through added resistance or parasitic capacitance.

Current-Based Fault Detection

Current monitoring enables detection of various fault types:

• Catastrophic faults: Opens and shorts cause dramatic current changes easily detected by simple comparators
• Parametric faults: Gradual changes in bias currents indicate parameter drift or process variations
• Intermittent faults: Continuous monitoring catches intermittent failures that might pass single-point testing
• Reliability degradation: Trending current over time reveals wear-out mechanisms before functional failure

Ring Oscillator Monitors

Ring oscillators are widely used process monitors:

• Speed monitors: Oscillation frequency directly indicates transistor switching speed
• Multiple corner monitors: Rings whose delay is dominated by NMOS or by PMOS devices separate the two device speeds, placing the die among the process corners, such as fast NMOS with slow PMOS
• Voltage and temperature sensing: Frequency variation with supply voltage and temperature provides additional characterization
• Local variation monitors: Multiple oscillators across the die reveal local process gradients

Ring oscillator frequencies correlate strongly with digital logic speed and can help predict analog parameters such as transconductance.

Analog Process Monitors

Structures specifically designed for analog parameter monitoring:

• Reference voltage monitors: On-chip bandgap references provide process-compensated voltage standards
• Threshold voltage monitors: Dedicated transistor structures enable accurate extraction of the threshold voltage
• Matching monitors: Paired devices reveal local mismatch for critical analog specifications
• Capacitor ratio monitors: Verify capacitor matching critical for switched-capacitor circuits

Environmental Sensors

On-chip sensors measure environmental conditions affecting performance:

• Temperature sensors: Diode or bandgap-based sensors measure junction temperature
• Voltage monitors: Supply voltage measurement enables voltage-compensated testing
• Stress sensors: Piezoresistive structures detect mechanical stress from packaging
• Humidity sensors: Capacitive structures detect moisture ingress in some applications

Environmental sensors enable real-time compensation of measurements, so that pass/fail decisions remain accurate across a range of test conditions.

Using Monitor Data

Process monitor data enables sophisticated test strategies:

• Adaptive test limits: Adjust specification limits based on measured process corner
• Correlation-based testing: Skip detailed tests when monitors indicate the device is well-centered
• Binning decisions: Sort devices into speed grades or performance categories based on monitor data
• Yield prediction: Use monitor data to predict which detailed tests are likely to fail

Aging and Wear-Out Mechanisms

Several mechanisms cause gradual circuit degradation:

• Hot carrier injection: High-energy carriers near the drain become trapped in the gate oxide or at the silicon-oxide interface, shifting threshold voltage and reducing transconductance over time
• Bias temperature instability: Temperature-accelerated charge trapping shifts threshold voltage, classically as negative-bias instability (NBTI) in PMOS devices, with a complementary positive-bias effect (PBTI) in NMOS devices in high-k/metal-gate processes
• Electromigration: Current-induced metal migration forms voids that raise interconnect resistance and eventually cause open circuits
• Time-dependent dielectric breakdown: Gate oxide degradation that eventually leads to failure

These mechanisms progress gradually, enabling detection before catastrophic failure if appropriate monitoring is in place.

On-Chip Aging Monitors

Dedicated structures track degradation over device lifetime:

• Stressed transistor monitors: Transistors under continuous bias stress track hot carrier and BTI degradation
• Ring oscillator aging: Frequency drift over time indicates accumulated device degradation
• Stress-aged references: Compare stressed and unstressed reference circuits to measure drift
• Interconnect resistance monitoring: Track metal resistance increases indicating electromigration

In-Field Degradation Assessment

Monitoring during operation enables real-time degradation tracking:

• Background monitoring: Continuously measure degradation indicators without interrupting normal operation
• Periodic self-test: Run BIST sequences at scheduled intervals to assess current performance
• Wear-out prediction: Project remaining useful life based on observed degradation rate
• Graceful degradation: Reduce performance demands or switch to redundant circuits as degradation advances

Alarm and Reporting Systems

Communicating degradation status to the system level:

• Threshold-based alarms: Generate interrupts when degradation exceeds predetermined levels
• Degradation registers: Store degradation metrics accessible via system interfaces
• Trend reporting: Provide degradation history enabling trend analysis
• Predictive alerts: Warn of impending failure based on degradation trajectory

Calibration Architectures

Various approaches implement self-calibration:

• Foreground calibration: Dedicated calibration phase during which normal operation is suspended
• Background calibration: Continuous calibration that operates alongside normal circuit function
• One-time calibration: Performed once during production test, with results stored in non-volatile memory
• Continuous adaptation: Real-time adjustment responding to environmental and aging changes

Offset and Gain Calibration

Fundamental calibration targets in analog circuits:

• Auto-zero amplifiers: Periodically sample and cancel offset using switched-capacitor techniques
• Chopper stabilization: Modulate signals to move offset to high frequency where it can be filtered
• Digital offset correction: Measure offset with on-chip ADC and subtract digitally or adjust DAC bias
• Gain calibration: Compare against reference and adjust programmable gain elements

Linearity Calibration

Correcting nonlinearity in data converters and amplifiers:

• Trim DAC adjustment: Programmable current or capacitor elements compensate for mismatch
• Digital correction: Measure nonlinearity and apply correction in the digital domain
• Redundant architectures: Over-ranging enables digital correction of analog errors
• Segmented calibration: Calibrate different portions of the transfer function independently

High-resolution ADCs and DACs routinely employ self-calibration to achieve performance beyond what raw component matching would allow.

Timing Calibration

Adjusting timing relationships for optimal performance:

• Clock phase adjustment: Programmable delay elements align clock phases for optimal sampling
• Aperture delay calibration: Programmable delay places the sampling instant where intended, correcting the fixed part of aperture delay; random aperture jitter varies from sample to sample and cannot be calibrated out, so it is reduced only by a cleaner clock and sharper sampling edges
• Duty cycle correction: Adjust clock duty cycle for symmetric performance
• Skew calibration: Compensate for timing differences between parallel channels

Calibration Storage and Management

Maintaining calibration data across power cycles:

• On-chip fuses: One-time programmable elements store permanent calibration values
• Non-volatile memory: EEPROM or flash stores calibration data that can be updated
• External storage: System memory holds calibration values loaded at power-up
• Re-calibration triggers: Temperature or time triggers initiate recalibration sequences

Control Sequencing

The BIST controller manages test execution:

• Test mode entry: Configure the circuit for test mode, isolating sensitive nodes and enabling test access
• Stimulus sequencing: Control signal generators to produce required test patterns in proper order
• Timing control: Manage settling times, acquisition windows, and synchronization
• Result collection: Gather response data and compute pass/fail determinations

Hardware versus Software Control

Trade-offs between control implementations:

• Dedicated state machine: Fixed hardware provides deterministic timing but limited flexibility
• Microcode control: Programmable sequencer enables test modification without hardware changes
• Processor-based control: Embedded CPU runs test software, maximizing flexibility at cost of speed
• Hybrid approaches: Hardware handles time-critical operations while software manages sequencing

Result Reporting

Communicating BIST results to external systems:

• Pass/fail flags: Simple status bits indicate overall test result
• Diagnostic registers: Detailed results accessible via JTAG or other test interfaces
• Signature readout: Compressed signatures available for external comparison
• Parametric data: Measured values available for characterization and debugging

Testability Guidelines

Design practices that enhance analog BIST effectiveness:

• Observable nodes: Provide access to internal nodes critical for fault detection
• Controllable inputs: Enable stimulus injection at multiple points within the circuit
• Isolation capability: Include switches to isolate subsections for independent testing
• Reference accessibility: Make internal reference voltages and currents measurable

Partitioning for Test

Dividing complex analog systems into testable blocks:

• Functional partitioning: Align test boundaries with functional blocks for meaningful results
• Feedback loop breaking: Include mechanisms to open feedback loops during testing
• Analog/digital boundaries: Clearly define and provide access to mixed-signal interfaces
• Hierarchical testing: Enable testing at multiple levels from component to system

Overhead Considerations

BIST circuitry impacts the primary design:

• Area overhead: Test signal generators, response analyzers, and control logic consume silicon area
• Performance impact: Test multiplexers and routing add parasitic loading to sensitive nodes
• Power consumption: BIST circuits draw power even in normal operation unless carefully power-gated
• Design complexity: Additional circuitry increases design and verification effort

The overhead must be justified by reduced external test costs, improved field diagnostics, or enhanced reliability. It varies widely with the techniques employed and the size of the circuit under test: a few comparators and a counter add little to a large data converter, while a full on-chip stimulus generator and digitizer can rival a small analog block in area.

Data Converter BIST

ADCs and DACs commonly incorporate self-test capabilities:

• INL and DNL testing: On-chip ramp generation and histogram (code-density) analysis measure integral and differential nonlinearity (INL and DNL), provided the ramp is more linear than the converter under test
• SNDR testing: Sinusoidal stimulus and fast Fourier transform (FFT) analysis quantify the signal-to-noise-and-distortion ratio (SNDR) for dynamic performance
• Missing code and monotonicity checks: Verify that every ADC output code is reachable and that a DAC's output never decreases as its input code increases
• Self-calibration: Automatic adjustment of trim elements to optimize performance

Automotive Electronics BIST

Safety-critical automotive applications demand comprehensive self-test:

• ISO 26262 compliance: The standard sets hardware architectural metrics by safety integrity level, such as a single-point fault metric of at least 99 percent for ASIL D, and on-chip diagnostics, including analog BIST, contribute to that coverage
• Power-on self-test: Verify circuit functionality before enabling safety-critical functions
• Continuous monitoring: Runtime checking detects failures during operation
• Redundancy management: Detect failures and switch to backup circuits

Sensor Interface BIST

Analog front-ends for sensors benefit from self-test:

• Sensor connectivity testing: Verify sensor connection by measuring expected impedance
• Amplifier chain testing: Inject known signals and verify amplification through the chain
• Reference verification: Confirm voltage and current references are within tolerance
• Environmental compensation: Self-calibrate based on temperature and supply voltage

RF Circuit BIST

Radio frequency circuits present unique BIST challenges:

• Loopback testing: Connect transmitter to receiver for system-level self-test
• Power detector BIST: On-chip power detectors verify transmit power levels
• Frequency synthesis testing: Verify PLL lock and frequency accuracy
• Modulation quality: Error vector magnitude (EVM) and spectral mask compliance verification

Current Challenges

Key issues in analog BIST implementation:

• Fault coverage uncertainty: Unlike digital circuits, analog fault coverage is difficult to quantify precisely
• Test quality versus overhead trade-off: Higher quality testing requires more complex BIST circuitry
• Performance impact: BIST circuitry can degrade the analog performance being tested
• Standardization: Beyond the IEEE 1149.4 test bus, whose commercial adoption has been limited, no widely adopted standard governs analog BIST, which complicates tool support and methodology sharing

Emerging Approaches

New techniques addressing analog BIST limitations:

• Machine learning-based testing: Train classifiers on production data to improve fault detection with minimal test content
• Statistical learning methods: Use population statistics to optimize test content and limits
• Specification-driven BIST: Generate BIST structures automatically from specification requirements, an approach still largely confined to research
• System-level BIST: Test analog circuits within their system context rather than in isolation

Integration with Digital BIST

Unified approaches for mixed-signal testing:

• Shared infrastructure: Leverage digital BIST scan chains and controllers for analog test data transport
• IEEE 1149.4 mixed-signal test bus: Extends IEEE 1149.1 boundary scan to analog pins, adding an Analog Test Access Port (ATAP) with two dedicated pins, AT1 and AT2, that connect through a Test Bus Interface Circuit to two internal analog buses, AB1 and AB2, routing stimulus and measurement to internal nodes; one bus serves primarily as a current-drive path and the other as a voltage-sense path
• Unified fault models: Develop comprehensive fault models spanning digital and analog domains
• Hierarchical BIST: Coordinate digital and analog BIST for efficient system-level testing