Electronics Guide

DC Parameter Testing

Basic DC measurements reveal many common failure modes:

• Supply current (IDD/ICC): Elevated quiescent current may indicate gate oxide damage, latch-up, or internal shorts. In static CMOS the quiescent supply current of a healthy die is dominated by subthreshold and gate leakage, so a defect that adds a resistive path stands out clearly. This is the basis of IDDQ testing, which compares the settled supply current across many logic states and flags the states that draw anomalous current.
• Leakage currents: Junction leakage, gate leakage, or insulation breakdown appear as excessive current under reverse bias or with floating inputs.
• Input/output voltage thresholds: Shifts indicate transistor degradation or electrostatic discharge (ESD) damage.
• Output drive capability: Reduced current drive suggests transistor damage or increased on-resistance.
• Pin-to-pin resistance: Opens and shorts detected by resistance measurements.

Comparison to known good devices and datasheet specifications quickly identifies out-of-specification parameters. Note that IDDQ loses discriminating power as process nodes shrink and background leakage rises; on advanced nodes analysts rely on delta-IDDQ methods, which compare current between states on the same die rather than against an absolute limit.

AC Parameter Testing

Dynamic measurements characterize high-frequency behavior:

• Propagation delay: Increased delays may indicate degraded transistors or resistive defects.
• Rise and fall times: Slower edges suggest drive capability issues or excessive loading.
• Setup and hold times: Timing margin degradation in sequential circuits.
• Frequency response: Bandwidth reduction in amplifiers or filters.
• Clock jitter: Timing instability in clock circuits.

Test System Considerations

Effective parametric testing requires:

• Force and measure accuracy: Source-measure units (SMUs) force a voltage while measuring current, or the reverse. Bench-grade SMUs resolve currents in the picoampere range; instruments built for semiconductor characterization, fitted with remote preamplifiers, reach the femtoampere range.
• Kelvin connections: Four-wire sensing removes lead and contact resistance from low-resistance measurements, which matters when the defect of interest is a few ohms in series with a milliohm interconnect.
• Guarding: Triaxial cabling driven at the same potential as the signal conductor suppresses cable leakage and dielectric absorption, without which sub-nanoampere measurements are meaningless.
• Current compliance limits: Every forced source is set with a compliance limit low enough to keep the defect intact. A short that survives at 1 mA may be blown open at 100 mA, destroying the physical evidence and converting a diagnosable short into an unexplained open.
• Temperature control: Junction leakage roughly doubles for every 8 to 10 degrees Celsius of junction temperature rise, so comparisons between a suspect part and a reference part are only meaningful at a controlled, recorded temperature.
• ESD-safe handling: Grounded workstations, wrist straps, and ionizers prevent the analyst from adding a second ESD event on top of the one under investigation.

Junction Characterization

I-V curves reveal junction behavior:

• Normal diode characteristics: Forward voltage drop, reverse breakdown voltage, and leakage current.
• ESD damage signatures: Soft breakdown, increased leakage, or shifted characteristics indicate ESD damage to protection structures or input/output circuits.
• Shorts: Ohmic behavior instead of rectifying characteristic.
• Opens: No current flow regardless of voltage.
• Resistive defects: Increased forward voltage drop or series resistance.

Transistor Curve Tracing

Family of curves with varying base/gate drive reveals transistor characteristics:

• Gain (beta/gm): Relationship between control input and output current.
• Breakdown voltages: Collector-emitter or drain-source breakdown.
• Saturation characteristics: On-resistance and saturation voltage.
• Leakage: Off-state current.

Comparison to good devices reveals degradation even when devices still function within specification limits.

Pin-Level Analysis

Systematic curve tracing of all pins identifies:

• Pin-to-ground characteristics: ESD protection diode behavior on each pin.
• Pin-to-supply characteristics: Upper protection diode and pull-up structures.
• Pin-to-pin characteristics: Internal connections, multiplexed signals, or cross-coupled failures.

Recording the full set of pin traces produces a signature for the part type. Because most pins on a given package share the same input/output cell design, an anomalous pin usually announces itself as the one trace that does not match its neighbors, and no reference part is strictly required. Automated pin-scan systems capture every pin combination in minutes and difference the result against a stored golden signature.

Electrostatic Discharge

ESD delivers a small amount of energy in a very short time. Component qualification models the two cases that dominate in practice: the human body model (HBM), a relatively slow discharge through the resistance of a person, and the charged device model (CDM), a very fast discharge of the package's own stored charge through a single pin as it touches ground. These are defined by the joint ESD Association and JEDEC standards ANSI/ESDA/JEDEC JS-001 for HBM and JS-002 for CDM.

Electrical signatures of ESD damage include:

• Soft leakage: A junction that still rectifies but leaks microamperes to milliamperes in reverse. This often precedes hard failure and may be the only anomaly on an otherwise functional part.
• Localized damage: Damage sites are typically a fraction of a micrometer across, so the part frequently retains most of its function.
• Damage at protection structures: HBM events usually damage the input/output protection devices or the power clamp that was designed to absorb them.
• Damage away from the pins: CDM events are fast enough to rupture the thin gate oxide of internal circuitry before the protection network responds, so a CDM signature is often an internal gate oxide short with intact I/O protection.

Electrical Overstress

Electrical overstress (EOS) delivers far more energy over a far longer time, typically from a misapplied supply, a hot-plug transient, a shorted load, an inductive kick, or a reversed connector. The signature is correspondingly larger:

• Hard, low-resistance shorts: Fused metal creates ohmic paths of ohms or less rather than the soft leakage typical of ESD.
• Melted or open bond wires: Sustained current opens the weakest link in the current path, which is often a bond wire or a narrow metal run.
• Externally visible damage: Cracked or discolored packages, blown mold compound, and carbonized residues are common, so visual inspection alone often identifies EOS.
• Damage tracking the current path: The damage follows the route the fault current took, which helps reconstruct how the energy entered the device.

ESD is a handling and process control problem. EOS is an application problem, and the corrective action normally belongs to the board or system design rather than to the component supplier. Attributing an EOS failure to ESD, or the reverse, sends the corrective action to the wrong organization, which is why the distinction is worth the analysis time.

Latch-Up

Bulk CMOS contains a parasitic silicon-controlled rectifier formed by the n-channel and p-channel devices together with the well and substrate. If an injected current or an overvoltage on a pin triggers it, the structure latches into a regenerative low-impedance state between supply and ground and stays there until the supply is removed or the current source is exhausted. The electrical signature is distinctive:

• Sustained high supply current: The part draws far above its specified current and does not recover on its own.
• Recovery on power cycling: If the current did not exceed the level that melts metal, a power cycle restores normal operation, which distinguishes latch-up from permanent damage.
• Trigger dependence: The event correlates with a transient at an I/O pin, a supply sequencing violation, elevated temperature, or, in space and avionics applications, a heavy-ion strike.

Latch-up susceptibility is characterized under JEDEC standard JESD78, which applies I-test current pulses to input and output pins and overvoltage pulses to the supplies at elevated temperature. Emission microscopy is well suited to latch-up work because the latched structure emits strongly and continuously, marking the holding region directly.

Test Vector Application

Applying known input patterns and checking outputs:

• Pattern matching: Comparing actual outputs to expected results identifies failing vectors.
• Shmoo plotting: Sweeping two conditions, most often supply voltage against clock period, and plotting pass or fail at every point produces a two-dimensional map of the operating window. The shape of the failing region is diagnostic in itself: a boundary that moves with voltage suggests a timing path, while a failure confined to low voltage suggests eroded noise margin.
• At-speed testing: Verifying operation at intended frequencies, since resistive and capacitive defects frequently pass slow-speed structural tests.
• Boundary scan: Test access defined by IEEE 1149.1 provides control and observation at the device pins through a four-wire or five-wire port, which reaches nets under ball grid arrays that no probe can touch.

Marginal Analysis

Stressing operating conditions reveals weaknesses:

• Voltage margining: Reducing supply voltage reveals circuits with reduced noise margins.
• Temperature testing: Hot and cold testing exposes temperature-sensitive failures.
• Frequency sweeping: Finding the frequency at which failures occur identifies timing-related problems.

Fault Isolation

Narrowing down failure location through functional tests:

• Block isolation: Testing functional blocks independently when possible.
• Signature analysis: Comparing test signatures to identify deviating circuits.
• Error pattern analysis: Using the pattern of failing vectors to deduce failure location.

Diagnosis Using Design-for-Test Structures

On a modern integrated circuit, the structures built in for manufacturing test are usually the most powerful localization aid available, and they operate before any optical technique is attempted.

• Scan chain diagnosis: Internal flip-flops are stitched into shift registers, so the state of essentially every sequential element can be loaded and observed. Diagnosis software compares the observed failing bits against the fault simulation of the applied patterns and returns a ranked list of candidate nets, frequently narrowing a whole-chip failure to a handful of locations.
• Chain integrity failures: A defect within the scan chain itself is diagnosed separately, by shifting a known pattern and observing where it is corrupted, which localizes the fault to a position along the chain.
• Memory failure bitmapping: Failing addresses from a memory test are translated through the array's row, column, and bank scrambling into physical coordinates on the die. The resulting bitmap shape is diagnostic: isolated single bits point to a cell or contact defect, full rows or columns point to a wordline, bitline, or driver failure, and larger blocks point to decoders, sense amplifiers, or supply distribution.
• Built-in self-test: Logic and memory BIST engines exercise structures that no external tester can reach at speed, and their diagnostic modes can report failing addresses or signatures rather than a single pass or fail bit.
• Redundancy caveats: Memories with repaired rows or columns must be diagnosed with the repair map in hand, or the physical location derived from the logical address will be wrong.

The output of scan or bitmap diagnosis is a short list of physical coordinates. Emission microscopy, laser stimulation, and physical analysis then start from those coordinates instead of searching the whole die, which is often the difference between a two-day analysis and a two-week one.

Light Emission Mechanisms

Semiconductors emit light through several mechanisms:

• Forward-biased junctions: Radiative recombination across the band gap. Silicon is an indirect-gap material, so this process is inefficient compared with direct-gap semiconductors, but the emission near 1.1 micrometers is still detectable with a cooled sensor and a long integration time.
• Saturated transistors: A MOSFET in saturation supports a high lateral field in the pinch-off region near the drain. Carriers accelerated in that field emit a broad infrared spectrum through intraband transitions. Because electrons reach higher energies than holes, n-channel devices emit substantially more strongly than p-channel devices of the same size.
• Hot carrier emission: The same mechanism observed where it is not wanted, marking sites of channel hot-carrier stress and flagging a latent reliability problem rather than a present failure.
• Avalanche emission: Impact ionization in a junction driven into breakdown produces emission far brighter than normal circuit operation, which makes reverse-biased damaged junctions easy to find.
• Leakage paths: Current through a defective dielectric or a filament in a gate oxide rupture emits at the defect, so anomalous emission from a location that should be dark identifies the defect directly.

Interpreting the image requires care. Healthy circuits emit, so an emission spot is evidence only when it is unexpected. Standard practice is to compare the emission image against a reference die under identical bias and pattern conditions, and to confirm that the spot's intensity tracks the electrical symptom as bias is varied.

Photon Emission Microscopy (PEM)

Emission is faint, so PEM systems pair a high-numerical-aperture infrared objective with a deeply cooled detector and integrate for seconds to minutes in a light-tight enclosure. Detector choice follows the optical path:

• Silicon CCD sensors: Cooled, back-thinned silicon CCDs offer very low noise and fine spatial resolution, but silicon's own band gap cuts their response off near 1.1 micrometers. They are best suited to front-side imaging.
• InGaAs arrays: Indium gallium arsenide detectors respond from roughly 900 to 1700 nanometers. That range covers the part of the emission spectrum that silicon transmits, which is what makes backside imaging possible.
• Time-resolved detection: Gating the detector to a specific phase of the clock separates emission from a suspect node from the surrounding background. Single-photon detectors with picosecond timing resolution extend this to waveform-level analysis of switching activity.

Backside emission microscopy is essential for flip-chip devices, where solder bumps and the package substrate block the active surface entirely. It works because silicon's indirect band gap of about 1.12 electron volts corresponds to a wavelength near 1.1 micrometers: photons of longer wavelength pass through the substrate rather than being absorbed. The substrate is nevertheless thinned and polished to an optical finish, typically to well under 100 micrometers, because residual absorption in doped silicon and scattering from a rough surface both cost signal and resolution. Solid immersion lenses placed against the polished silicon improve resolution further by raising the effective numerical aperture.

Front-side imaging requires decapsulation, which for plastic packages normally means a controlled acid etch that removes mold compound without attacking the bond wires or die surface. Because decapsulation is destructive to the package, it is planned in the sequence only after nondestructive electrical characterization is complete.

Emission Analysis Applications

• Defect localization: Identifying the location of shorts, leakage paths, or damaged junctions.
• Gate oxide integrity: Detecting hot carrier injection sites indicating oxide stress.
• Latch-up detection: Localizing the trigger and holding regions of latch-up.
• Logic state verification: Confirming internal node states during operation.

Infrared Thermography

IR cameras image thermal radiation from device surfaces:

• Steady-state imaging: Continuous power application shows equilibrium temperature distribution.
• Hot spot detection: Elevated temperatures indicate shorts, high current paths, or failing components.
• Comparative analysis: Temperature differences between good and failing devices reveal problem areas.

Failure analysis cameras use cooled photon detectors in the mid-wave infrared band of roughly 3 to 5 micrometers, where indium antimonide and mercury cadmium telluride sensors give both good sensitivity and, because diffraction scales with wavelength, better spatial resolution than the long-wave band of 8 to 12 micrometers used by most general-purpose thermal cameras. A cooled mid-wave camera reaches a noise-equivalent temperature difference in the range of tens of millikelvin, and microscope objectives bring the pixel pitch on the sample down to a few micrometers, which is close to the diffraction limit at these wavelengths.

The practical limit is usually emissivity rather than the camera. A die surface presents polished aluminum or copper metallization next to passivation and bare silicon, and emissivity across those materials varies from below 0.1 to above 0.8. Raw thermal images therefore show apparent temperature differences that are purely optical. The two standard remedies are to apply a thin, uniform high-emissivity coating over the region of interest, or to record an emissivity reference image at a known uniform temperature and use it to correct every subsequent frame.

Lock-In Thermography

Pulsing the electrical stimulus at a fixed frequency and correlating every camera frame against that reference transforms the sensitivity of the measurement. Averaging over thousands of modulation periods suppresses uncorrelated noise, and only heating synchronized with the stimulus survives:

• Sensitivity: Where a conventional thermal image is limited to roughly tens of millikelvin, lock-in thermography resolves temperature modulation amplitudes of about 100 microkelvin and below, a gain of two to three orders of magnitude. This makes buried defects dissipating only microwatts detectable.
• Phase information: The thermal wave takes time to diffuse from the heat source to the surface, so the phase lag between stimulus and response encodes the depth of the source. Phase images therefore separate a defect on the die surface from one in the package substrate or an inner PCB layer, and support approximate depth estimation.
• Rejection of background: The steady thermal background, including self-heating of the whole die and emissivity contrast, is not correlated with the modulation and largely disappears. The amplitude image consequently isolates the stimulus-dependent heat source with far less emissivity artifact than a steady-state image.
• Frequency as a depth control: Thermal diffusion length falls as the modulation frequency rises. Low frequencies probe deeper but blur laterally; high frequencies give sharper images of shallow sources. Sweeping the lock-in frequency is a standard way to establish how deep a defect lies.

Lock-in thermography is widely used on packaged parts, power modules, and assembled boards precisely because it sees through molding compound and laminate, which no optical technique can do.

Thermal Laser Stimulation

Instead of imaging the heat a device generates, thermal laser stimulation supplies the heat and watches what the device does about it. A focused laser is raster-scanned across the die while an electrical parameter is monitored, and the resulting image maps electrical response against beam position. The laser wavelength is chosen to be below the silicon band gap, conventionally 1340 nanometers, where the photon energy of about 0.93 electron volts is less than silicon's 1.12 electron volt gap. The beam therefore passes through the substrate and deposits heat without generating photocurrent, which cleanly separates thermal from photoelectric effects.

• OBIRCH (optical beam induced resistance change): The device is held at constant voltage and the supply current is monitored. Local heating changes local resistance, and because the temperature coefficient of a defective structure differs from that of sound metal, voids, thinned lines, and high-resistance contacts appear as current anomalies.
• TIVA (thermally induced voltage alteration): The complementary configuration, holding current constant and monitoring the voltage across the device. It is particularly effective for localizing shorts.
• SEI (Seebeck effect imaging): With no external bias applied, the thermal gradient produced by the laser generates a thermoelectric voltage. This works on unpowered parts and is well suited to locating opens in metal lines.
• XIVA (externally induced voltage alteration): A variant that uses an external constant-current source and lock-in detection to improve signal-to-noise on weak responses.
• Resolution: The optical spot at 1340 nanometers sets a limit near a micrometer; a solid immersion lens on polished backside silicon brings practical localization below that. Because the response is thermal, resolution is also blurred by heat spreading, so the electrical signal, not the optics alone, sets the achievable precision.

These techniques share the geometry and much of the hardware of the photoelectric laser methods described in the next section; the wavelength, and therefore the physics of the interaction, is what distinguishes them.

OBIC and LIVA

Photocurrent-based scanning techniques:

• OBIC (optical beam induced current): Carriers generated in the depletion region of a junction are swept out by the built-in field and appear as external current. Scanning the beam while monitoring that current maps every junction on the die and reveals damaged junctions, which respond with altered amplitude or a shifted profile.
• LIVA (light induced voltage alteration): The complementary constant-current configuration, monitoring the voltage change produced by the photocurrent. Because the voltage response depends on the impedance the photocurrent sees, LIVA is sensitive to open contacts and to junctions whose bias state is abnormal, and it is a standard method for finding floating or partially connected nodes.

Laser Voltage Probing

Laser voltage probing (LVP) measures the waveform on an internal node without any physical contact, by parking a continuous-wave beam on a transistor through the backside and analyzing the reflected light. It has largely replaced mechanical probing for internal signal debug on flip-chip parts.

• Principle: A sub-band-gap beam, typically at 1319 or 1064 nanometers, passes through the silicon and reflects from the transistor structure. Its amplitude and phase are modulated as the node switches, because the free-carrier density in the device changes both the refractive index and the absorption coefficient of the silicon, and because the strong field in the depletion region adds electro-absorption and electro-refraction contributions. The recovered modulation is a small fraction of the reflected power, so the signal is extracted by averaging over many repetitions of a looping test pattern.
• Backside access: Probing takes place through the thinned and polished substrate, which is the only optical path available once the active surface is covered by solder bumps.
• Time-resolved measurement: Locking acquisition to the pattern loop yields waveforms with picosecond timing resolution, enough to measure path delay and to compare a failing part against simulation.
• Laser voltage imaging: A frequency-domain variant tunes the detection to a specific switching frequency and scans the beam, producing an image of every node toggling at that rate. This is a fast way to find, for example, the one node in a large block that is stuck or running at the wrong frequency.

Marginality Localization: SDL and LADA

Some failures are not hard defects but marginalities that appear only at a particular voltage, temperature, or clock rate. Both techniques below run the device continuously on a test loop biased at the edge of failure, scan the laser, and record where the beam flips the outcome between pass and fail. The resulting map marks the circuit responsible for the marginality.

• SDL (soft defect localization): Uses the sub-band-gap thermal wavelength, conventionally 1340 nanometers, so the perturbation is local heating. Heating shifts threshold voltages and carrier mobility, and thus timing, which makes SDL well matched to temperature-sensitive and resistive defects.
• LADA (laser-assisted device alteration): Uses the above-band-gap wavelength near 1064 nanometers, so the perturbation is injected photocurrent rather than heat. The injected carriers momentarily change a transistor's switching point, which perturbs propagation delay along the path under test. Spatial resolution with a continuous-wave 1064 nanometer beam is on the order of a few hundred nanometers, better than the thermal techniques because there is no heat diffusion to blur the response.

LADA is the standard tool for speed-path debug, where a design passes at nominal frequency but fails at the margin and no physical defect exists at all. Pulsed variants synchronized to the test pattern allow the analyst to identify not only which circuit is responsible but which clock cycle it fails in.

TDR Principles

• Impedance discontinuities: Changes in impedance cause reflections that appear at specific time delays corresponding to distance. The delay is round-trip, so the distance to the fault is half the propagation velocity times the observed delay.
• Opens and shorts: An open reflects the step with the same polarity and full amplitude; a short reflects it inverted. Intermediate impedances give intermediate amplitudes, so the reflection coefficient recovers the fault impedance directly.
• Resistive faults: A series resistance produces a positive step of partial amplitude, while a shunt resistance produces a negative one, which lets a cracked joint be distinguished from a leakage path.
• Propagation velocity: Converting time to distance requires the velocity in the medium under test, which is the speed of light divided by the square root of the effective dielectric constant. In FR-4 stripline this is roughly 15 centimeters per nanosecond, and an error in the assumed dielectric constant translates directly into an error in the reported fault location.
• Spatial resolution: Resolution is set by the combined rise time of the step generator and the sampling head, not by the sample rate. Two discontinuities merge unless they are separated by more than half the distance the signal travels during that rise time. A high-performance instrument with a combined system rise time near 35 picoseconds resolves features a few millimeters apart; a general-purpose cable tester with a nanosecond edge resolves nothing finer than several centimeters.
• Loss and dispersion: Conductor and dielectric loss slow the edge as it propagates, so effective resolution degrades with distance along a lossy trace. Faults near the launch point are always resolved more sharply than distant ones.

Package and Board-Level TDR

TDR applications at the assembly level:

• Bond wire opens: Missing or broken wire bonds appear as characteristic impedance changes.
• Solder joint failures: Open or high-resistance joints produce reflection signatures.
• PCB trace defects: Cracks, opens, or impedance variations along traces.
• Connector issues: Contact resistance or mechanical problems in connectors.

Practical fixturing dominates the quality of the result. The probe launch is itself a discontinuity, so a reference trace taken on a known good assembly is subtracted or overlaid rather than interpreted in isolation. Differential TDR, which drives both conductors of a pair, is required for differential interconnect and separates a fault on one conductor from a symmetric impedance change on both.

From Field Map to Current Path

The measured quantity is the field component normal to the scan plane, which is not the same thing as the current path. A current-carrying line produces a field that peaks on either side of it rather than above it, so raw field images are ambiguous. Standard practice inverts the Biot-Savart relation numerically, most often through a Fourier-domain transformation, to recover the two-dimensional current density that would produce the observed field. That current-density image can then be overlaid on a computed tomography or design layout view to name the failing net.

Resolution is governed almost entirely by the standoff between sensor and current, because the field of a line source falls off with distance. Halving the standoff roughly halves the smallest resolvable feature, which is why sample preparation for magnetic imaging concentrates on thinning whatever lies between the sensor and the current rather than on exposing the die.

Sensor Technologies

• SQUID sensors: A superconducting quantum interference device offers the highest field sensitivity available, low enough to image currents in the microampere range. The penalty is cryogenic operation: the sensor sits behind a vacuum window in a cooled dewar, which imposes a standoff of tens of micrometers or more and correspondingly limits spatial resolution.
• Giant magnetoresistive sensors: GMR heads operate at room temperature and can be brought within a few micrometers of the sample. They are less sensitive than a SQUID in absolute terms but frequently deliver better spatial resolution because of the far smaller standoff, and they are the practical choice for die-level and package-level shorts.
• Magneto-optical imaging: A Faraday-rotating indicator film placed on the sample converts the local field into a rotation of polarized light, which a camera reads as a full-field image. Acquisition is fast because the whole field of view is captured at once, and the technique visualizes current spreading and current crowding around defects in metallization.

Magnetic imaging is nondestructive and requires no optical access, but it does require that fault current actually flow, so the part must be biased to reproduce the failure. It is most valuable for supply-to-ground shorts in package substrates and multilayer boards, for open and shorted traces beneath components, and as a confirmation step when thermal or emission results are ambiguous.

Localizing Shorts on Power Distribution

A short between a supply rail and ground on a board with hundreds of decoupling capacitors and dozens of loads cannot be found by resistance measurement alone, because every path reads a few milliohms. The voltage-gradient method solves this: a current-limited supply injects a known current, perhaps one ampere, between the shorted rails, and a sensitive microvoltmeter measures the resulting drop between pairs of points on the plane. Because the plane behaves as a resistive sheet, the measured voltage falls as the probe approaches the short and reaches a minimum at it. Lock-in thermography over the powered board and magnetic current imaging solve the same problem without probing and are usually faster when the equipment is available.

In-Circuit and Flying-Probe Test

• In-circuit test: A bed-of-nails fixture contacts test pads across the assembly and measures components individually, using guarding to isolate a part from those in parallel with it. Coverage is excellent, but the fixture is specific to one board and expensive to build.
• Flying-probe test: Motorized probes reach nets in sequence with no fixture, which suits failure analysis and low volumes at the cost of much longer test time.
• Boundary scan: Where fine pitch and area-array packages leave no accessible pads, IEEE 1149.1 test access remains the only way to control and observe the nets between compliant devices.
• Access limits: All in-circuit measurements are affected by the surrounding circuit. A reading taken with the part in place is a measurement of the network, not of the component, and a suspicious result must be confirmed after isolation or removal.

Intermittent and Condition-Dependent Faults

The hardest board failures are those that do not reproduce on the bench. Useful approaches include:

• Thermal provocation: Localized heating with a hot air pencil or cooling with freeze spray, applied to one component or joint at a time, exposes faults that depend on differential expansion.
• Mechanical provocation: Controlled board flexure or tapping individual joints while continuity is monitored reveals cracked solder and fractured plated-through holes.
• Event detection: A continuity monitor that latches a resistance excursion lasting less than a microsecond catches transients that no periodic measurement would ever see, and is standard practice during thermal cycling.
• Condition logging: Recording supply voltage, temperature, and load alongside the failure indication builds the correlation that tells the analyst which stress to apply.

An intermittent that cannot be reproduced cannot be confirmed as fixed, so the effort spent making a failure repeatable is nearly always recovered later.

Initial Assessment

1. Review failure information: Symptoms, operating conditions at failure, application circuit, manufacturing and field history, and whether other units failed the same way.
2. Document the as-received condition: Photograph the part before anything is touched, and preserve date and lot codes. Evidence of handling damage, rework, or a prior repair attempt frequently explains the failure by itself and cannot be recovered once the part is unsoldered.
3. Visual inspection: External damage, discoloration, cracking, residues, or contamination, under a stereo microscope before any cleaning.
4. Basic electrical checks: Supply current, pin-to-pin resistance, and ground continuity, taken with conservative current compliance so that a soft defect is not converted into a hard one.

Characterization Phase

1. Parametric testing: Comprehensive DC and AC measurements.
2. Curve tracing: I-V characteristics of all pins.
3. Functional testing: Verify reported failure and characterize symptoms.
4. Comparison to good device: Identify deviations from normal behavior.

Localization Phase

1. Emission microscopy: Detect anomalous light emission.
2. Thermal imaging: Find hot spots or abnormal heating patterns.
3. Laser-based techniques: Localize resistive or junction defects.
4. TDR: Identify interconnect faults.

Documentation

• Record all measurements: Data supports conclusions and enables comparison.
• Capture images: Emission, thermal, and optical images document findings, each with a scale reference and a registration feature that ties it to die coordinates.
• Note conditions: Temperature, bias, timing, and other test conditions, since a localization result is meaningless without the conditions under which it was obtained.

Verification

Localization is not the same as explanation, and the analysis is not finished until the candidate defect is shown to account for what was actually observed:

1. Consistency check: The proposed defect must explain every measured symptom, not merely the most obvious one. A supply short that fails to explain an accompanying timing failure means the analysis is incomplete.
2. Independent confirmation: Two techniques based on different physics, for example emission microscopy and lock-in thermography, agreeing on the same coordinate is far stronger evidence than either alone.
3. Physical confirmation: Targeted cross-sectioning or delayering at the identified coordinate converts an electrical inference into observed structure and identifies the mechanism.
4. Mechanism to root cause: A gate oxide rupture is a mechanism, not a root cause. The analysis must go on to establish what applied the stress, whether design margin, a handling process, or an application transient, because only that answer supports corrective action.