Electronics Guide

Controllability and Observability

Two properties underlie all testability: controllability and observability. Controllability is the ability to drive an internal node to a known state from the available inputs; observability is the ability to propagate the value of an internal node to an output where it can be measured. A node that cannot be controlled cannot be exercised, and a node that cannot be observed cannot be checked. Faults hide precisely where controllability or observability is poor, so DFT techniques exist largely to improve one or both at points the functional design leaves inaccessible.

Deeply embedded logic illustrates the problem. A node buried behind several layers of combinational and sequential logic may require a long, carefully crafted input sequence to reach a known state and an equally long sequence to make its value visible. DFT structures such as scan chains and test points shorten these paths, converting hard-to-reach nodes into directly settable and readable ones, and thereby make otherwise impractical tests feasible.

Fault Models and the Goal of Test

Testing is organized around fault models that abstract physical defects into analyzable forms. The stuck-at model, in which a node is held permanently high or low, remains the workhorse for digital test because it is simple and correlates well with many real defects. Other models address bridging between nodes, opens, transition delays, and parametric drift. A fault model gives the test a concrete target: a defined list of faults that test patterns must detect, against which coverage can be measured and improved.

The goal of test is not to prove a design correct, which verification addresses, but to distinguish good manufactured units from defective ones. DFT serves this goal by making the defects of the chosen fault models detectable with practical test patterns and reasonable test time. A testable design is one in which the fault list can be covered thoroughly without resorting to impractically long or complex test sequences.

Physical Access for Board Test

At the board level, much testing depends on physical access to circuit nodes. Test points are deliberately placed pads or vias that expose nodes to a test fixture, typically a bed-of-nails that presses spring-loaded probes against the board. Adequate test-point size, spacing, and placement on a single side where possible determine whether a fixture can be built at all and how reliably it contacts each node. Probing component leads directly is unreliable and risks damage, so dedicated test points are preferred for any node the test strategy must reach.

The relentless shrinking of components and rise of dense, double-sided assemblies has steadily eroded physical access. Fine-pitch and bottom-terminated packages bury their connections beneath the part, and high node counts leave little room for probe pads. This erosion of access is the principal force driving the adoption of structural test methods such as boundary scan, which reach internal nodes electronically rather than mechanically.

Planning Access Early

Test access cannot be reserved after layout, because by then the board area is allocated and the nodes are routed. Planning access early means identifying the nodes the test strategy requires, budgeting board area for their test points, and constraining placement so that probes can reach them. It also means deciding the division of labor between physical probing and electronic access methods, since the two are complementary. Designs that defer these decisions routinely discover that critical nodes are unreachable, forcing either reduced coverage or a costly redesign.

The Boundary-Scan Architecture

Boundary scan, standardized as IEEE 1149.1 and universally known by the name of the Joint Test Action Group, JTAG, addresses the loss of physical access by building test access into the integrated circuits themselves. Each compliant device contains a shift-register cell at every relevant pin, forming a boundary-scan register that rings the device's core logic. Through a small four-wire or five-wire test access port, these cells can be loaded with values driven onto the pins and can capture values present at the pins, all without physical contact at the board level.

The architecture centers on a test access port controlled by a defined state machine, an instruction register that selects the test mode, and the boundary-scan register itself. Standard instructions allow the cells to drive and observe pin states, to bypass a device, or to read an identification code. Because the boundary-scan cells of devices on a board can be chained together, a single port can access the interconnections of many components in series.

Interconnect Test and Beyond

The primary application of boundary scan is interconnect test: detecting opens, shorts, and bridges in the nets between compliant devices. By driving a pattern from the boundary cells of one device and capturing it at the cells of connected devices, the test confirms that each net carries the expected value, identifying missing, bridged, or misrouted connections that physical probing might be unable to reach. This structural coverage of the board's wiring is boundary scan's defining strength.

Beyond interconnect test, the boundary-scan infrastructure supports in-system programming of flash and programmable logic, access to internal scan and self-test resources, and limited functional interaction with on-chip logic. Building a complete and correctly chained boundary-scan path through a board, with attention to which devices are compliant and how non-compliant clusters are handled, is itself a DFT design task that pays back in dramatically improved access on dense assemblies.

The original standard assumes static, directly coupled digital nets, so a family of companion standards extends it to modern designs. IEEE 1149.6 adds the means to test AC-coupled and differential high-speed interconnects, which the base standard cannot exercise, by driving and detecting signal edges that pass through the coupling. IEEE 1687, known as IJTAG, standardizes structured access to the growing population of embedded instruments inside a device, such as built-in self-test controllers, sensors, and monitors, reached through the same test access port. Choosing the appropriate members of this standards family for the technologies a board actually uses is part of planning boundary-scan coverage.

On-Chip Test Generation and Analysis

Built-in self-test, BIST, moves the test apparatus onto the device itself, so that a circuit can exercise and check portions of its own logic with minimal external support. A typical BIST block contains a pattern generator that applies stimulus to the circuit under test and a response analyzer that compresses the resulting outputs into a compact signature. The device runs the test internally and reports a simple pass or fail, greatly reducing the demands on external test equipment and the volume of test data that must be applied from outside.

For regular structures such as memories, logic BIST and the closely related memory BIST are especially effective. A memory BIST controller can march standard algorithmic patterns through every cell and detect the addressing, coupling, and retention faults characteristic of memory arrays, at speed and without external addressing of each location. The regularity of the target makes the on-chip generator and analyzer compact and the coverage high.

Trade-Offs and Field Use

BIST imposes a cost in silicon area, design effort, and sometimes performance, since the test structures occupy space and may load functional paths. These costs are weighed against substantial benefits: reduced reliance on expensive external testers, the ability to test at the device's native operating speed, and the option to run tests in the field for power-on diagnostics and ongoing health monitoring. In systems where field testability matters, the capacity to invoke self-test after deployment can be as valuable as the manufacturing coverage it provides.

In-Circuit Test

In-circuit test, ICT, examines individual components and connections on an assembled board, largely independent of overall function. Using bed-of-nails or flying-probe access, ICT measures component values, checks orientation and presence, and verifies that nodes are neither shorted nor open. Its great advantage is diagnostic resolution: because it probes individual nodes, a failure points directly to the offending component or joint, which makes repair efficient. ICT excels at catching the manufacturing defects, such as wrong, missing, reversed, or poorly soldered parts, that dominate assembly yield loss.

The method's weakness is its dependence on physical access, the same access that component miniaturization steadily removes. Where probes cannot reach, ICT coverage falls, and boards increasingly rely on boundary scan to supply structural coverage that probing alone cannot. Combined techniques, blending physical probing with electronic access, have become common precisely because neither method alone reaches every node on a modern dense board.

Functional Test

Functional test exercises the assembled product through its normal interfaces to confirm that it performs its intended operation. Rather than checking components individually, it applies realistic stimuli and observes whether outputs and behavior match specification, often at or near operating speed. Functional test catches defects that structural methods miss, including timing problems, interaction effects, and faults that only manifest when the system runs as a whole, and it most closely represents the conditions the product will face in service.

The trade-off is diagnostic resolution. A functional failure proves only that the product does not work, not which component is responsible, so isolating the cause can require additional diagnosis. Functional and in-circuit test are therefore complementary: structural methods provide fast, well-localized coverage of manufacturing defects, while functional test confirms holistic operation. A sound test strategy sequences them to balance coverage, diagnosis, and throughput.

Converting Sequential Logic for Test

Scan design is the foremost DFT technique for digital integrated circuits, and it directly attacks the controllability and observability problem inside sequential logic. In a scan design, the ordinary storage elements of the circuit are replaced by scan-capable equivalents that, in test mode, link together into one or more shift registers called scan chains. In functional mode the elements behave normally; in test mode they form a path along which test data can be shifted in and captured results shifted out.

This transformation reduces the difficult problem of testing sequential logic to the far easier problem of testing combinational logic. By shifting a desired state into the scan chain, the test directly controls every scan element; by capturing the circuit's response and shifting it out, the test directly observes them. The deep sequences that would otherwise be needed to reach and read internal nodes disappear, replaced by straightforward shift-in, capture, and shift-out operations.

Pattern Generation and Compression

With full scan in place, automatic test pattern generation can compute, for the combinational logic between scan elements, the patterns that detect the targeted faults and can report the coverage achieved. This automation is a principal reason scan design dominates digital DFT: high fault coverage becomes a tractable, tool-driven result rather than a hand-crafted feat. The completeness of scan access is what makes the pattern-generation problem solvable at scale.

Scan does carry costs. The scan elements add area and may slightly affect timing, and the volume of shifted test data and the time to shift it can grow large for big designs. Test-data compression techniques reduce both the data volume and the test time by encoding patterns compactly and expanding them on-chip, keeping scan practical even as designs grow. Balancing chain length, compression, and coverage is a routine part of digital DFT planning.

Measuring and Targeting Coverage

Fault coverage is the fraction of the modeled fault list that a given set of tests detects, and it is the primary quantitative measure of test quality. High coverage means few defects escape; low coverage means defective units pass and reach later stages or customers. Coverage is computed by fault simulation or derived from pattern-generation tools, and it lets engineers compare test strategies objectively and identify the untested faults that remain. Targeting those residual faults, often by improving access at the nodes they involve, is how coverage is raised toward its goal.

Coverage interacts directly with field quality. The defect level that escapes test depends on both the incoming defect rate and the coverage achieved, so even modest gaps in coverage can allow a meaningful number of bad units through when volumes are high. Setting a coverage target appropriate to the product's quality requirements, and designing the test access needed to reach it, is a central output of DFT planning.

Composing a Layered Strategy

No single method covers everything, so a sound test strategy layers complementary techniques across the stages of manufacture. Structural methods, in-circuit test, and boundary scan efficiently catch the manufacturing defects that dominate early yield loss and localize them for repair. Built-in self-test covers regular structures such as memories at speed. Functional test confirms that the integrated product operates correctly as a whole. Each stage targets the defects it detects best, and the sequence is arranged so that cheaper, better-localized tests filter out the bulk of defects before more expensive tests run.

Designing this strategy is inseparable from designing the product, because each method imposes its own requirements: test points for probing, compliant devices and a clean chain for boundary scan, on-chip resources for self-test, and accessible interfaces for functional test. Deciding early which methods will carry which coverage, and providing the features each one needs, is the essence of effective DFT and the surest way to avoid the untestable design that no amount of later effort can rescue.