Failure Analysis Methodologies

Failure analysis methodologies provide systematic frameworks for investigating, understanding, and preventing failures in electronic systems. These structured approaches turn reactive troubleshooting into proactive reliability improvement, helping engineers identify not only what failed, but why it failed and how to keep the same failure from recurring.

Effective failure analysis draws on several disciplines, including electrical engineering, materials science, physics, chemistry, and statistics. The methodologies covered in this section range from predictive techniques applied during design to investigative approaches used when field failures occur. Two broad classes recur throughout: prospective methods such as failure modes and effects analysis and fault tree analysis, which anticipate failures before they happen, and retrospective methods such as root cause analysis, physical failure analysis, and failure reporting systems, which dissect failures that have already occurred. Together, they form a comprehensive toolkit for understanding and improving electronic system reliability.

The measure of a failure analysis is not the sophistication of its instruments but the strength of the conclusion it supports. An analysis succeeds when it identifies the physical mechanism that produced the failure, traces that mechanism back to a design, manufacturing, supply, or use decision that can be changed, and yields a corrective action whose effectiveness can later be verified with data. A micrograph of a cracked solder joint is evidence; the finding that a specific pad geometry concentrates strain at that joint is the analysis.

Articles in This Category

Failure Modes and Effects Analysis - Systematically evaluate potential failures before they occur. Coverage includes FMEA methodology and procedures; severity, occurrence, and detection ratings; risk priority number calculation and the action priority tables that have replaced it in automotive practice; design FMEA development; process FMEA creation; system FMEA integration; criticality analysis (FMECA); failure mode prioritization; corrective action tracking; FMEA software tools; living document maintenance; cross-functional team approaches; customer-specific requirements; and industry-specific adaptations.
Fault Tree Analysis - Construct logical diagrams that analyze system failures from the top down. Topics include fault tree construction techniques, AND/OR gate logic, common cause failures, minimal cut set analysis, quantitative probability calculations, and integration with safety analysis to identify critical failure paths in complex electronic systems.
Root Cause Analysis Techniques - Trace a confirmed failure back to the decision that permitted it. Coverage includes the eight disciplines, DMAIC, and A3 frameworks, fishbone (Ishikawa) diagram construction, the five whys method, event tree analysis, cause and effect matrices, Pareto analysis, scatter diagram interpretation, failure investigation protocols, evidence collection procedures, failure replication methods, hypothesis development and testing, corrective action verification, preventive action development, and lessons learned documentation. Fault trees appear only as one investigative aid among several; their construction, logic, and quantification belong to Fault Tree Analysis.
Physics of Failure Approaches - Model degradation quantitatively and predict life from the model. Topics include stress-strength interference analysis, damage accumulation models, the Arrhenius, Eyring, Peck, Black, and Coffin-Manson relations, physics-based reliability prediction, physics-based test planning, and the practical limits of the approach. This page carries the modeling methodology; the catalog of the mechanisms it models is Failure Mechanism Understanding.
Physical Failure Analysis - Examine failed components microscopically. Topics encompass optical microscopy techniques, scanning electron microscopy (SEM), energy-dispersive X-ray spectroscopy (EDS), focused ion beam (FIB) analysis, X-ray inspection methods, scanning acoustic microscopy, infrared thermography, decapsulation techniques, cross-sectioning procedures, metallographic analysis, fractography principles, corrosion analysis, contamination identification, bond wire analysis, and semiconductor failure mechanisms.
Electrical Failure Analysis - Diagnose failures using electrical measurement and characterization techniques. Topics include parametric testing, functional testing and diagnosis using design-for-test structures, curve tracing, discrimination of electrostatic discharge, electrical overstress, and latch-up signatures, photon emission microscopy, thermal imaging, lock-in thermography, OBIC and OBIRCH (optical beam induced current and optical beam induced resistance change) techniques, laser voltage probing, soft defect localization and laser-assisted device alteration (LADA), magnetic current imaging, time-domain reflectometry, and board- and assembly-level fault localization.
Failure Reporting and Corrective Action Systems - Implement systematic processes for capturing failure data and driving improvements. Coverage includes FRACAS (failure reporting, analysis, and corrective action system) implementation, failure databases, trend analysis, corrective action tracking, effectiveness verification, and closed-loop systems that translate failure information into reliability improvements.
Contamination and Corrosion Analysis - Investigate the failures that moisture, ionic residue, and bias produce together. Topics include contamination sources, cleanliness testing by ion chromatography and resistivity of solvent extract, corrosion mechanisms in electronics, electrochemical migration, conductive anodic filament (CAF) formation, conformal coating failures, and prevention strategies. Tin whiskers appear as a related stress-driven growth phenomenon and are treated in full in Tin Whisker Analysis and Mitigation.
Tin Whisker Analysis and Mitigation - Understand, test for, and control the conductive tin filaments that grow from lead-free finishes. Coverage includes stress-driven growth mechanisms and incubation behavior, the distinction between whiskers and electrochemical migration dendrites, bridging shorts and metal vapor arcs, documented satellite, nuclear, medical, and automotive failures, JESD22-A121A measurement methods, JESD201A acceptance classes and limits, GEIA-STD-0005-2 control levels, and part-, assembly-, and design-level mitigation.
Solder Joint and Interconnect Analysis - Analyze failures in solder connections and electrical interconnects. Coverage includes solder joint metallurgy, intermetallic compound formation, thermal fatigue, mechanical stress failures, wire bond analysis, ball grid array (BGA) inspection, and techniques specific to analyzing interconnection failures in electronic assemblies.
Semiconductor Failure Analysis - Run the die-level laboratory sequence on an integrated circuit. Topics include electrical characterization of the failed device, fault isolation, sample preparation from decapsulation to backside thinning, die-level imaging and nanoprobing, the added difficulty of advanced technology nodes, and the workflow that carries a part from reported symptom to identified defect site. The device mechanisms this work uncovers are cataloged in Failure Mechanism Understanding.
Failure Mechanism Understanding - The reference catalog of the mechanisms by which electronic hardware degrades, organized by where they act. Coverage includes electromigration and stress migration in conductors, time-dependent dielectric breakdown (TDDB), hot carrier degradation, negative bias temperature instability (NBTI), electrostatic discharge and electrical overstress damage, thermal cycling and mechanical fatigue, creep and stress relaxation, corrosion, tin whisker growth, solder joint and package failures, interface delamination, and passive component wear-out.

Modes, Mechanisms, and Root Causes

Careful failure analysis keeps three terms separate, because conflating them is the most common way an investigation stops too early.

Three Distinct Concepts

A failure mode is the observable manner in which an item fails to perform its function: an open circuit, a short, a parameter drifting outside tolerance, an intermittent connection, or a loss of output. Failure modes are what a test technician or a customer reports.

A failure mechanism is the physical, chemical, or electrical process that produced the mode: a fatigue crack propagating through a solder joint, metal atoms migrating along a conductor, a gate oxide breaking down under field stress, or a metallic dendrite bridging two conductors.

A root cause is the design, manufacturing, procurement, or operating decision that allowed the mechanism to act: a pad geometry that concentrates strain, a reflow profile outside the supplier's process window, an unqualified part substitution, or an application beyond the rated ambient temperature.

An investigation that stops at the mode produces a replacement part. One that stops at the mechanism produces an explanation. Only an investigation that reaches the root cause produces a corrective action capable of preventing recurrence, which is why the methodologies in this category deliberately push the analyst from one level to the next.

Mechanisms Common in Electronic Hardware

Silicon wear-out mechanisms dominate at the die level. Electromigration moves metal atoms under high current density, thinning conductors until they open and piling material where it can short; the classic Black relation expresses median time to failure as an inverse power of current density combined with an Arrhenius temperature term. Time-dependent dielectric breakdown degrades gate oxides under sustained electric field, hot carrier injection shifts transistor thresholds through carriers trapped near the drain, and negative bias temperature instability shifts thresholds in PMOS devices held at negative gate bias and elevated temperature. Each of these mechanisms has an accepted acceleration model, which is what makes short, hot qualification tests interpretable as statements about years of use.

Interconnect mechanisms dominate at the assembly level. Mismatched coefficients of thermal expansion between a package and its board drive cyclic strain into solder joints on every power or ambient cycle, and Coffin-Manson-type relations link the resulting plastic strain range to cycles until cracking. Intermetallic compounds grow at the solder-to-pad interface over time and temperature, and an excessively thick or voided intermetallic layer embrittles a joint that was sound when built. Wire bonds fail by heel cracking, lift, and corrosion of the bond pad interface.

Electrochemical and environmental mechanisms need moisture, an ionic contaminant, and a bias voltage. Given all three, electrochemical migration grows dendrites across a surface, and conductive anodic filament formation grows conductive paths through the glass-fiber-to-resin interfaces inside a laminate, typically between plated holes. Both produce intermittent shorts that can vanish when the assembly dries or when the filament fuses, which is one reason such failures are commonly returned as no fault found. Whiskers growing from compressively stressed pure tin finishes and general corrosion of exposed metals belong to the same family.

Overstress mechanisms are single events rather than accumulated damage. Electrostatic discharge delivers a high voltage in nanoseconds to a few hundred nanoseconds and typically leaves small, localized melt or oxide rupture sites that require die-level imaging to find. Electrical overstress lasts longer and delivers far more energy, leaving gross evidence such as fused metallization, cratered silicon, or a ruptured package. Distinguishing the two matters because the corrective actions diverge sharply: electrostatic discharge points toward handling controls and on-chip protection design, while electrical overstress points toward circuit-level protection, supply transients, or misapplication. Moisture absorbed by plastic packages is a related single-event hazard, since it can flash to steam during reflow and delaminate or crack the package, the defect known informally as popcorning.

Prospective and Retrospective Methods

Prospective methods work from a design description and ask what could go wrong. Failure modes and effects analysis proceeds from the bottom up, enumerating the failure modes of each component or process step and tracing each one to its effect on the system. Fault tree analysis proceeds from the top down, taking a defined undesired event and decomposing it through logic gates into the combinations of lower-level events that can produce it. The two are complementary rather than interchangeable: an FMEA is exhaustive across single failures but represents combinations poorly, while a fault tree handles combinations and common cause dependencies well but only for the top events an analyst thought to define.

Retrospective methods start from hardware that has already failed. They are more expensive per finding, because they consume laboratory time, specialized instruments, and often the sample itself, but their conclusions rest on physical evidence rather than on engineering judgment. Physical and electrical failure analysis establish what happened inside the part; root cause techniques connect that finding to a changeable decision; a failure reporting, analysis, and corrective action system accumulates the findings so that patterns emerge across units, lots, and programs.

Mature programs run both classes and let each correct the other. A field failure mode that the FMEA never listed is an indictment of the FMEA, not merely a surprise, and the measured mechanism from a returned unit should update the occurrence rating and the detection assumptions used on the next product. Without that feedback path, prospective analyses drift into documentation exercises and retrospective analyses become a series of unconnected case files.

The Failure Analysis Workflow

Laboratory failure analysis follows one governing rule: proceed from nondestructive to destructive techniques, and do not take a step that destroys evidence until the evidence it would destroy has been recorded. Decapsulation, cross-sectioning, and mechanical probing are all legitimate, but performed prematurely they can ruin a sample that cannot be replaced.

Verification and Evidence Preservation

Confirm the failure before analyzing it, and capture the as-received condition first. Useful records include photographs of the unit and its packaging, serial numbers and date codes, the reported symptom in the reporter's own words, the operating conditions at the time of failure, and the handling history since. Applying power to a returned unit, cleaning a board, or reflowing a suspect joint can each erase the evidence that would have identified the mechanism. Where a result may support a warranty claim, a supplier dispute, or litigation, documented chain of custody is as important as the technical work.

Nondestructive Analysis

Optical inspection under magnification catches obvious damage, contamination, mechanical stress marks, and assembly defects. X-ray radiography reveals internal structure without opening a package, exposing voids, wire sweep, cracked or open ball grid array joints, and die attach problems. Scanning acoustic microscopy locates delamination and voids at internal interfaces. Electrical characterization compares the failed unit against its specification and against a known good sample, with curve tracing revealing junction damage, leakage, and shorted or open pins, and parametric measurement quantifying how far a parameter has drifted. Infrared and lock-in thermography under bias show where power is actually dissipated, which frequently points at the fault before any package is opened.

Fault Localization

Narrowing the failure to a physical site before opening the device determines whether the destructive work that follows lands on the defect or misses it. Lock-in thermography extends thermal imaging by averaging synchronously with a modulated bias, resolving heat sources far below the sensitivity of a static thermal image. Photon emission microscopy detects the faint light emitted at leakage paths, junction breakdown sites, and saturated transistors. Optical beam induced current and optical beam induced resistance change techniques scan a laser across the die and map the resulting change in current or resistance to find defective junctions and marginal conductors. Time-domain reflectometry locates opens and shorts along package and board interconnects by timing reflections. At the board level, boundary scan, selective depopulation, and node-by-node measurement serve the same purpose.

Destructive Physical Analysis

With the site known, the analyst opens the sample along a path chosen to intersect it. Chemical or plasma decapsulation exposes the die while preserving bond wires and metallization. Cross-sectioning followed by metallographic polishing exposes a plane through a solder joint, via, or package interface, and is the standard way to measure intermetallic thickness, crack paths, and plating quality. Focused ion beam milling cuts site-specific cross sections a few micrometers wide and prepares lamellae for transmission electron microscopy. Scanning electron microscopy supplies the imaging resolution, and energy-dispersive X-ray spectroscopy identifies the elements present, which distinguishes solder from plating, flux residue from ionic contamination, and corrosion product from base metal. Fractography separates ductile overload from fatigue by the character of the fracture surface, an important distinction because the two imply entirely different causes.

From Mechanism to Corrective Action

Establishing the mechanism ends the laboratory phase and begins the engineering one. Structured techniques such as the five whys, Ishikawa diagrams, and cause and effect matrices connect the mechanism to the decisions that permitted it. The strongest confirmation is replication: reproducing the same mechanism on good hardware by deliberately reinstating the suspected condition demonstrates causation rather than correlation. Corrective action then proceeds in two stages, containment to protect customers and production immediately, followed by a permanent change to the design, process, specification, or supplier control. Verification closes the loop, using requalification data and field return rates to confirm that the change worked, and the result is recorded in the failure reporting system, the FMEA, and the design guidelines so that the lesson outlives the project team.

Standards and Reference Frameworks

Several international standards define the core analytical methods. IEC 60812:2018 covers failure modes and effects analysis together with failure modes, effects, and criticality analysis, and presents both risk priority numbers and criticality matrix approaches to ranking. IEC 61025:2006 defines fault tree analysis, including its symbols, construction procedure, and qualitative and quantitative treatment. IEC 62740:2015 sets out the principles and steps of root cause analysis and compares candidate techniques by attribute; it deliberately covers only events that have already occurred and does not address the assignment of responsibility or liability.

Sector practice adds its own frameworks. In the automotive supply chain, the AIAG and VDA FMEA Handbook, published in 2019, harmonized North American and German practice around a seven-step process and replaced the risk priority number with an action priority rating of high, medium, or low, assigned from a published table covering every combination of severity, occurrence, and detection. The change responds to a well-known weakness of the risk priority number: because it is the product of three ordinal ratings, very different risks can share a value, and arbitrary numeric thresholds tempt teams to adjust ratings rather than reduce risk. Defense and aerospace work still refers to MIL-STD-1629A, issued 24 November 1980 and cancelled 4 August 1998 without a direct replacement, whose severity classifications and criticality analysis remain in wide use. Its reporting counterpart, MIL-STD-2155 of 1985, was superseded in December 1995 by MIL-HDBK-2155, which describes the failure reporting, analysis, and corrective action system in handbook rather than requirement form. Many organizations also structure investigations around the eight disciplines problem-solving format, which pairs a containment step with a verified permanent corrective action.

Device and assembly references supply the physical detail. The JEDEC publication JEP122, Failure Mechanisms and Models for Semiconductor Devices, collects the accepted semiconductor failure mechanisms with their acceleration models, and the JESD22 series defines the stress tests that exercise them. Electrostatic discharge sensitivity is classified by ANSI/ESDA/JEDEC JS-001 for the human body model and JS-002 for the charged device model, and the classification level of a damaged part is often the first question a discharge investigation must answer. At the assembly level, IPC documents define the cleanliness, acceptability, and inspection criteria that failure analysis tests against, while the moisture sensitivity levels of J-STD-020 and the floor-life handling rules of J-STD-033 exist because moisture-driven package cracking was a recurring and expensive assembly failure.

Common Pitfalls

Several failure modes afflict failure analysis itself. The most frequent is stopping at the component: replacing a failed part restores function but explains nothing, and the same part will fail again in the next unit. Closely related is mistaking the failure site for the cause, since a fused trace or a burned resistor is often the victim of a short somewhere downstream rather than the origin of the event.

Units returned as no fault found deserve treatment as data rather than as noise. Intermittent behavior has real physical sources, including connector fretting, marginal timing, moisture-dependent leakage, self-clearing dendrites, and cracks that conduct when warm and open when cold. A rising no-fault-found rate frequently signals a marginal design or a test that fails to reproduce field conditions, and dismissing those returns discards the earliest available warning.

Statistical discipline matters as much as laboratory skill. A single failed unit establishes what happened to that unit; deciding whether a problem is systematic requires population data, lot and date code traceability, and a denominator. Conversely, an analysis that concludes with a correlation and no mechanism invites a corrective action aimed at the wrong variable. Finally, corrective actions that are never verified are among the most costly outcomes of all, because containment gets mistaken for a permanent fix and the organization believes a problem is closed while the mechanism remains untouched.

About This Category

Failure analysis methodologies form the investigative foundation of reliability engineering. Without systematic approaches to understanding failures, organizations cannot effectively improve their products or prevent recurring problems. The techniques in this section enable engineers to move beyond anecdotal troubleshooting to evidence-based reliability improvement. Whether applied during design to anticipate potential failures or after field failures to drive corrective actions, these methodologies provide the structured frameworks needed to understand and eliminate the root causes of electronic system failures.

Successful failure analysis requires both technical expertise and systematic thinking. Engineers must combine knowledge of electronics, materials, and physics with disciplined investigation methods to reach valid conclusions, and they must resist the pressure to close an investigation at the first plausible story. The methodologies presented here have been developed and refined over decades of industrial practice, and they are most effective when used together: a prospective analysis that predicts where failures will occur, a laboratory workflow that determines what actually happened, and a reporting system that turns each finding into a change the next design will inherit.

Electronics Guide