Electronics Guide

Fundamental Concepts

Traditional optical modules connect to host electronics through external electrical interfaces, requiring signal conditioning, retiming, and other power-intensive processing to overcome electrical losses over printed circuit board traces. Co-packaged optics fundamentally changes this paradigm by placing optical engines adjacent to or integrated with the host silicon, reducing electrical path lengths from tens of centimeters to just millimeters.

This proximity enables several key advantages: dramatically reduced power consumption for electrical signaling, elimination of signal integrity challenges on long PCB traces, higher aggregate bandwidth density, reduced latency, and improved system scalability. The approach is particularly critical for applications demanding multi-terabit aggregate bandwidth, such as large-scale switching ASICs, AI accelerators, and high-performance computing interconnects.

CPO architectures typically separate the optical and electronic functions into distinct chiplets or dies that are integrated using advanced packaging techniques. The electronic die handles digital processing and high-speed serializer/deserializer (SerDes) functions, while the photonic die manages light generation, modulation, detection, and wavelength management. This heterogeneous integration allows each technology to be optimized independently and manufactured using the most appropriate process node.

2.5D and 3D Integration Approaches

Co-packaged optics leverages advanced packaging methodologies to achieve the close integration between electronic and photonic components. Two primary approaches dominate the landscape: 2.5D integration using interposers and 3D integration using vertical stacking.

2.5D Integration

In 2.5D integration, multiple dies are mounted side-by-side on a common substrate called an interposer. The interposer contains fine-pitch interconnect routing that connects the dies with much shorter electrical paths than would be possible on a standard organic package substrate. Silicon interposers offer the highest interconnect density with line widths and spacings similar to those achievable in standard CMOS processes, enabling thousands of connections between dies with minimal electrical parasitic effects.

For co-packaged optics, 2.5D integration allows the photonic integrated circuit (PIC) to be placed immediately adjacent to the electronic ASIC, connected through high-speed differential pairs routed through the silicon interposer. This approach maintains thermal isolation between the optical and electronic components, which is critical since many photonic devices operate optimally at different temperatures than electronic circuits. The interposer can also include passive optical routing, thermal management features, and decoupling capacitance.

3D Integration

3D integration vertically stacks dies using through-silicon vias (TSVs) to create direct vertical connections between layers. This approach offers the ultimate in interconnect density and minimizes signal path lengths, but introduces significant thermal management challenges. Heat generated by the electronic die must be efficiently removed without adversely affecting temperature-sensitive photonic components.

For CPO applications, 3D integration typically places the photonic die on top of the electronic die, allowing optical fibers to attach from above while heat is extracted from below through the package substrate. TSVs carry high-speed electrical signals and power between layers, while careful thermal design ensures the photonic layer operates within its required temperature range. Some implementations use hybrid approaches, combining 2.5D side-by-side placement for some functions with 3D stacking for others.

Hybrid Integration Strategies

Many practical CPO implementations use hybrid approaches that combine elements of both 2.5D and 3D integration. For example, a design might use 2.5D integration to place electronic and photonic dies side-by-side on a silicon interposer, while simultaneously using 3D stacking to place memory or control logic above the main processing die. These hybrid approaches balance the competing demands of interconnect density, thermal management, manufacturing yield, and cost.

Optical Interposers

Optical interposers represent an advanced evolution of traditional silicon interposers, incorporating embedded optical waveguides and passive photonic components directly into the interposer substrate. This technology enables optical signals to be routed between dies and to/from fiber interfaces without requiring active photonic components at every location.

Silicon Photonics Interposers

Silicon photonics interposers use standard CMOS-compatible fabrication processes to create optical waveguides in silicon-on-insulator (SOI) substrates. These waveguides can route optical signals with low loss across the interposer, connect to vertical grating couplers for fiber attachment, and integrate passive optical components such as splitters, combiners, and wavelength filters. The same interposer simultaneously provides electrical routing through metal interconnect layers.

The key advantage of silicon photonics interposers is their ability to monolithically integrate both electrical and optical distribution networks. This eliminates the need for discrete optical connections between every die, instead allowing a centralized photonic die to fan out optical signals across the package through the interposer waveguide network. Manufacturing compatibility with standard CMOS processes also enables high-volume, cost-effective production.

Glass and Polymer Interposers

Alternative interposer materials include specialized glasses and polymers that offer different tradeoffs. Glass interposers can achieve very low optical loss and provide excellent dimensional stability across temperature variations, critical for maintaining optical alignment. They support both surface-mounted and embedded waveguides, and can integrate fiber v-grooves directly into the substrate for precise fiber positioning.

Polymer interposers offer flexibility in fabrication and can be patterned using low-cost techniques such as photolithography or embossing. While optical losses are typically higher than silicon or glass, polymers provide excellent mechanical compliance to accommodate thermal expansion mismatches and can be manufactured in large formats. Some designs embed optical waveguides within multilayer organic substrates, creating a fully integrated electrical-optical package substrate.

Fiber Attachment Methods

Connecting optical fibers to co-packaged optics presents unique challenges due to the need for precise alignment, mechanical stability, and protection of sensitive optical interfaces within a densely integrated package environment.

Edge Coupling

Edge coupling aligns the fiber perpendicular to the chip edge, launching light directly into waveguides fabricated on the photonic die or interposer. This method requires extremely precise alignment, typically within ±1 micrometer, to achieve low-loss coupling. Mode field matching between the fiber and waveguide is critical; often spot-size converters are integrated at the waveguide edge to taper the mode from the tight confinement of a silicon waveguide to match the larger mode of a single-mode fiber.

Edge coupling requires careful cleaving and polishing of both the fiber end and chip edge to minimize scattering and back-reflection. The assembled fiber-chip interface is typically secured with index-matched adhesive to maintain alignment and reduce Fresnel reflections. While edge coupling offers low insertion loss when properly executed, it is sensitive to mechanical stress and requires robust packaging to maintain alignment over temperature cycling and mechanical shock.

Vertical Coupling

Vertical coupling, also called surface-normal coupling, uses grating couplers fabricated on the chip surface to redirect light between fibers positioned above the chip and in-plane waveguides. This approach significantly relaxes lateral alignment tolerances compared to edge coupling, with acceptable insertion loss over alignment ranges of tens of micrometers. Grating couplers can be placed anywhere on the chip surface, enabling two-dimensional fiber arrays and flexible routing.

The primary challenges with vertical coupling include higher insertion loss (typically 2-4 dB per interface) and wavelength sensitivity due to the grating's dispersive properties. Modern designs mitigate these issues through apodized gratings, multi-layer grating structures, and careful optimization of grating parameters. Vertical coupling is particularly well-suited to co-packaged optics because fibers can be routed above the package, avoiding edge access constraints and enabling high port densities.

Fiber Arrays and MT Ferrules

High-density CPO implementations often use fiber arrays where multiple fibers are precisely positioned in a single assembly. MT ferrules, standardized for parallel optical interconnects, hold 12 or 24 fibers in a rectangular array with precise spacing (typically 250 micrometers). These ferrules can mate directly to matching grating coupler arrays on the photonic die, providing a robust, high-density connection method.

Custom fiber arrays can also be fabricated using v-groove assemblies, where precision-etched grooves in silicon or glass align bare fibers to exact positions. The fibers are bonded in place and the array is polished to create a clean end face. These arrays can then be actively aligned to the photonic die during assembly and permanently attached. Some designs integrate the v-grooves directly into the optical interposer, allowing fibers to be dropped in and bonded as a final assembly step.

Alignment Techniques

Achieving and maintaining precise optical alignment is critical for CPO performance and reliability. Alignment requirements span multiple scales, from nanometer-level waveguide fabrication tolerances to millimeter-scale fiber positioning.

Active Alignment

Active alignment uses live optical feedback during assembly to optimize coupling efficiency. Light is launched into the fiber, and the transmitted power is monitored while the fiber position is adjusted in multiple degrees of freedom using precision micromanipulators. Once optimal coupling is achieved (maximum transmitted power), the fiber is bonded in place using UV-curable or thermal-cure adhesives.

This approach achieves the highest possible coupling efficiency by compensating for fabrication tolerances in waveguide dimensions, fiber core position, and grating coupler performance. However, active alignment is time-consuming and requires sophisticated automation to be economically viable in production. For CPO with many fiber channels, parallel active alignment systems can simultaneously optimize multiple fibers, but equipment cost remains significant.

Passive Alignment

Passive alignment relies on precision mechanical features to position optical components without optical feedback. V-grooves, precision holes, mechanical stops, and other datum features define component positions based purely on mechanical tolerances. When the cumulative tolerance stack-up is tight enough, passive alignment can achieve acceptable coupling efficiency without the time and cost of active alignment.

Silicon micromachining enables v-groove arrays with sub-micrometer positioning accuracy, making passive alignment viable for many CPO applications. The key is designing the mechanical interface such that fiber position is deterministic and repeatable. Some designs use silicon alignment pedestals or pins that mate with corresponding features on the photonic die, creating a self-aligning interface. Passive alignment is particularly advantageous for vertical coupling with grating couplers, where larger alignment tolerances reduce mechanical precision requirements.

Self-Alignment and Solder Reflow

Self-alignment techniques exploit surface tension forces during solder reflow to automatically position components with high precision. Matching metal pad patterns on the components and substrate create strong surface tension forces when solder melts, pulling components into alignment. This technique is widely used for flip-chip assembly and can be adapted for aligning optical components.

For CPO, solder self-alignment can position photonic dies or fiber array assemblies with several-micrometer accuracy, sufficient for many waveguide coupling applications. The challenge is ensuring the self-alignment features do not interfere with thermal management paths or create stress that degrades optical alignment during thermal cycling. Some implementations use temporary alignment features that position components during bonding, then are removed or rendered inactive after the permanent bond is formed.

Thermal Management and Isolation

Effective thermal management is one of the most challenging aspects of co-packaged optics design. Electronic ASICs may dissipate hundreds of watts while operating efficiently at 80-100°C, while many photonic components require stable temperatures in the 20-40°C range for optimal performance and wavelength stability.

Thermal Challenges

Laser sources are particularly temperature-sensitive, with wavelength shifts of approximately 0.1 nm/°C for distributed feedback (DFB) lasers and even larger shifts for some chip-scale laser types. For wavelength-division multiplexed (WDM) systems with tight channel spacing, this wavelength drift can cause channel crosstalk or signal loss. Additionally, laser efficiency and lifetime degrade at elevated temperatures, making thermal control essential for reliability.

Modulators, photodetectors, and many passive photonic components also exhibit temperature-dependent behavior. Silicon photonics resonant devices, such as ring resonator modulators and filters, are extremely temperature-sensitive with resonance wavelength shifts around 70-80 pm/°C. Maintaining wavelength alignment in WDM systems requires either tight temperature control or active wavelength tuning mechanisms.

Thermal Isolation Strategies

Thermal isolation separates hot electronic components from temperature-sensitive photonic components, allowing each to operate in its optimal temperature range. Physical separation in a 2.5D layout provides inherent thermal isolation, with the interposer substrate acting as a thermal barrier. Additional thermal isolation can be achieved through air gaps, low-thermal-conductivity materials, or active thermal break structures in the interposer.

Some designs use dedicated thermoelectric coolers (TECs) to actively control photonic die temperature independently of the electronic die. The TEC can be integrated into the package substrate beneath the photonic die, or positioned on the back side if the die is mounted in a flip-chip configuration. TEC-based thermal management adds power consumption (typically 10-30% of the cooling power) but enables precise temperature control and can compensate for varying ambient conditions.

Heat Extraction and Spreading

Effective heat extraction from high-power electronic dies in CPO packages requires careful thermal path design. Most designs extract heat from the back side of the electronic die through the package substrate to an external heat sink. High-performance thermal interface materials (TIMs), vapor chambers, or embedded heat spreaders distribute heat across a larger area, reducing thermal resistance.

For 3D stacked configurations, thermal management becomes more complex. Heat from lower dies must be extracted through or around upper dies, potentially requiring through-silicon thermal vias (TSTVs) or lateral heat spreading in metal layers. Some designs intentionally place low-power photonic dies above high-power electronic dies, accepting the thermal gradient but minimizing overall thermal resistance to ambient.

Temperature Monitoring and Control

Integrated temperature sensors monitor die temperatures in real-time, enabling active thermal management and wavelength compensation algorithms. On-die diode sensors or resistive temperature detectors (RTDs) provide local temperature measurements with millidegree accuracy. This information feeds back to thermal control systems that adjust TEC drive currents, modulate electronic die power states, or tune photonic component wavelengths to maintain system performance.

Test Strategies

Testing co-packaged optics presents unique challenges due to the permanent integration of multiple dies and the combination of high-speed electrical and optical signals. Comprehensive test strategies are essential to achieve acceptable manufacturing yields and ensure long-term reliability.

Die-Level Testing

Pre-packaging die-level testing verifies functionality before expensive assembly processes. Electronic dies undergo standard wafer-level testing using automated test equipment (ATE) to verify logic functions, SerDes performance, and built-in self-test (BIST) circuits. This testing identifies gross defects and performance outliers, preventing known bad dies from entering the packaging flow.

Photonic die testing is more challenging due to the need for optical access and the variety of integrated components. Wafer-scale optical probing systems use fiber arrays or free-space optics to inject test signals and measure optical responses while dies remain in wafer form. Key parameters include modulator bandwidth and extinction ratio, photodetector responsivity and bandwidth, waveguide propagation loss, and grating coupler insertion loss. Some photonic wafer probers achieve throughputs of hundreds of dies per hour, making comprehensive testing economically feasible.

Package-Level Testing

After assembly, package-level testing validates the complete integrated system. Optical testing requires fiber connections to the package, either through temporary test probes or mated connectors if the final assembly includes them. Automated test systems measure optical transmit and receive paths, verify wavelength alignment in WDM systems, and characterize bit error rate (BER) performance across operating conditions.

Electrical testing validates high-speed SerDes links between the electronic ASIC and external interfaces, power supply sequencing and current consumption, and system-level functions such as media access control (MAC) layer operation. Environmental testing subjects packages to temperature cycling, thermal shock, vibration, and mechanical stress to verify reliability margins. These tests are typically performed on a sample basis rather than 100% screening due to time and cost constraints.

Built-In Self-Test (BIST)

Embedded BIST capabilities enable testing without external test equipment, reducing test time and enabling field diagnostics. Optical BIST can include pseudo-random bit sequence (PRBS) generators and checkers, on-chip photodetector monitors to measure optical power levels, wavelength locker circuits that track and compensate for wavelength drift, and eye diagram monitors that assess signal quality in real-time.

BIST functions operate during normal system operation, providing continuous health monitoring and early warning of degradation. This capability is particularly valuable for co-packaged optics in critical infrastructure applications where unplanned downtime is costly. BIST data can feed back to system management interfaces, enabling predictive maintenance and optimized system performance.

Accelerated Life Testing

Reliability qualification uses accelerated life testing to predict long-term performance in actual operating environments. High-temperature operating life (HTOL) testing stresses packages at elevated temperatures while continuously monitoring key parameters. Thermal cycling between temperature extremes verifies solder joint integrity and die attach reliability. Humidity testing assesses hermeticity and moisture ingress resistance.

Optical components often have unique failure modes, including laser degradation, optical adhesive darkening, and fiber-to-chip coupling drift. Accelerated testing must specifically address these mechanisms with appropriate stress conditions and monitoring. Industry standards such as Telcordia GR-468 provide guidance on reliability testing for optical components, though CPO-specific standards are still evolving.

Known Good Die (KGD) Concepts

The economics of co-packaged optics depend critically on the availability of known good die (KGD), since the cost of integrating even a single defective die into a complex multi-die package can be substantial. KGD strategies ensure that only dies meeting stringent quality and performance criteria enter the packaging flow.

KGD Requirements

True KGD requires testing that predicts post-packaging performance and long-term reliability, not just basic functionality. This includes full parametric testing across operating conditions, burn-in to eliminate early failures, and screening for latent defects that might manifest during or after packaging. The testing must be comprehensive enough that the probability of a packaging-induced failure is acceptably low.

For photonic dies, KGD requires optical testing at the wafer level, which is more challenging than electrical testing but essential for cost-effective CPO manufacturing. The wafer-level optical test must characterize all integrated photonic functions, including laser threshold and slope efficiency, modulator performance, detector responsivity, and passive component losses. Some manufacturers also perform limited burn-in on photonic wafers to stabilize laser performance before dicing.

Die Grading and Binning

Not all functional dies have identical performance. Die grading sorts tested dies into bins based on key parameters such as maximum operating speed, power consumption, or optical performance. Higher-performance bins command premium pricing and may be reserved for specific applications, while lower bins are used in less demanding applications or sold at reduced prices.

For co-packaged optics, die binning enables optimization of die combinations. A high-performance electronic ASIC can be paired with a high-performance photonic die to create a premium product, while more typical dies are combined to create mainstream offerings. This binning strategy maximizes revenue and yield by finding appropriate applications for all functional dies rather than rejecting anything that doesn't meet the highest specifications.

Supply Chain Considerations

CPO packages often integrate dies from different manufacturers, requiring a robust KGD supply chain. The electronic ASIC might come from a leading-edge logic foundry, while the photonic die comes from a silicon photonics specialist, and memory or control dies come from yet another source. Each supplier must provide true KGD with compatible testing standards and traceability.

Industry standards for KGD certification, such as JEDEC's JEP136, provide frameworks for qualifying die suppliers and specifying KGD requirements. However, photonic KGD standards are less mature, and many CPO manufacturers develop custom qualification processes specific to their applications. As the industry matures, standardized photonic KGD specifications will become increasingly important for supply chain efficiency.

Yield Considerations

Manufacturing yield is a critical factor in the economic viability of co-packaged optics. The complexity of integrating multiple dies with both electrical and optical connectivity creates numerous opportunities for defects and performance degradation.

Yield Loss Mechanisms

CPO yield depends on the multiplicative effect of individual component yields. If an electronic die has 95% yield, a photonic die has 90% yield, and the assembly process has 95% yield, the overall package yield is only 0.95 × 0.90 × 0.95 = 81.2%. As more dies are integrated or processes become more complex, this multiplicative effect can severely impact economics.

Assembly-specific yield losses include die cracking during pick-and-place, solder void formation, underfill delamination, fiber misalignment, optical contamination, and thermal interface material voids. Each of these can result in a non-functional package despite all input components being known good die. Minimizing assembly defects through process optimization, automation, and robust design is essential for acceptable overall yields.

Yield Enhancement Strategies

Several strategies can improve CPO manufacturing yield. Redundancy at the system level allows some component failures to be tolerated; for example, a 16-lane optical interface might be designed to operate with one or two failed lanes. This significantly improves package yield at the cost of some performance degradation in failed units.

Repair strategies enable salvaging packages with localized defects. Laser trimming can adjust resistor values to compensate for process variations. Wavelength tuning using integrated heaters or bias adjustments can bring WDM channels back into specification. Some designs include spare optical channels that can be activated to replace failed primary channels. The economic trade-off between added complexity for repairability and the value of recovered units must be carefully evaluated.

Design for Manufacturability (DFM)

DFM principles applied to co-packaged optics can significantly improve yields. This includes designing optical couplings with sufficient tolerance margins, choosing alignment methods appropriate for the required precision, minimizing the number of assembly steps and opportunities for contamination, and incorporating test access points for in-process monitoring.

Thermal design also impacts yield through thermal stress effects. Careful selection of materials with matched thermal expansion coefficients reduces stress during thermal cycling. Compliant die attach materials or stress relief features can prevent die cracking. Underfill materials that flow reliably and avoid void formation improve bump interconnect reliability.

Learning Curves and Yield Improvement

CPO is an emerging technology with yields improving rapidly as manufacturing processes mature. Early production typically shows low yields that improve through iterative process refinement, defect analysis, and design optimization. Manufacturers employ statistical process control and failure analysis to identify systematic yield limiters and prioritize improvement efforts.

As production volumes increase and learning curves drive down defect densities, CPO yields will approach those of mature packaging technologies. However, the optical coupling and alignment aspects will likely remain more yield-limiting than purely electrical interconnects, requiring continued investment in automation, process control, and design optimization.

Applications and Future Directions

Co-packaged optics is being adopted in applications where bandwidth density, power efficiency, and reach converge to make traditional electrical or pluggable optical approaches impractical.

High-Performance Computing

Supercomputers and AI training clusters require massive inter-node bandwidth with minimal latency. CPO enables switch ASICs with integrated 51.2 Tbps or higher optical I/O, supporting thousands of parallel optical lanes. This bandwidth density is unachievable with electrical signaling and difficult to realize with traditional pluggable optics due to faceplate space constraints.

Data Center Networks

Hyperscale data centers are rapidly adopting CPO for spine and leaf switches. The reduced power consumption (up to 50% reduction in I/O power compared to pluggable modules) translates to significant operational cost savings and improved sustainability. The smaller form factor enables higher-radix switches with more ports in the same physical space, improving network topology efficiency.

Telecommunications

5G and emerging 6G wireless networks require high-capacity fronthaul and backhaul links with strict latency requirements. CPO enables compact, power-efficient optical line terminals that can be deployed closer to cell sites. The integration reduces overall system cost and simplifies deployment in space-constrained locations.

Emerging Technologies

Future CPO developments include integrated linear-drive photonics for coherent transmission, enabling long-haul optical transport directly from the ASIC. Quantum key distribution (QKD) systems may use CPO to integrate single-photon detectors and quantum light sources with control electronics. Optical computing approaches that use light for computation, not just communication, will require unprecedented levels of electronic-photonic integration that build on CPO foundations.

As silicon photonics technology matures, integration density will increase through smaller feature sizes and 3D photonic integration. Standardization efforts through industry consortia will drive interoperability and reduce costs. The next decade will likely see CPO transition from a specialized high-end technology to a mainstream approach for high-bandwidth interconnects across the computing and telecommunications industries.

Key Takeaways

• Co-packaged optics integrates photonic components directly with electronic circuits in a single package, dramatically reducing power consumption and enabling higher bandwidth densities than traditional pluggable optics
• 2.5D integration using interposers and 3D stacking with TSVs are the primary packaging approaches, each offering different trade-offs between interconnect density, thermal management, and manufacturing complexity
• Optical interposers with embedded waveguides enable sophisticated optical routing within the package, supporting high port densities and flexible optical topologies
• Fiber attachment methods include edge coupling and vertical coupling through grating couplers, with active or passive alignment techniques depending on performance and cost requirements
• Thermal management is critical, requiring careful isolation of temperature-sensitive photonics from high-power electronics, often using active cooling with thermoelectric coolers
• Comprehensive test strategies spanning die-level, package-level, and built-in self-test capabilities are essential for manufacturing quality control and field reliability
• Known good die practices ensure only pre-qualified components enter the expensive packaging flow, critical for maintaining acceptable overall yields
• Yield optimization through redundancy, repair strategies, and design for manufacturability is essential for economic viability as CPO integrates multiple dies and complex assembly processes
• Applications in high-performance computing, data centers, and telecommunications are driving rapid adoption as bandwidth demands outpace the capabilities of electrical interconnects

Related Topics

• Optical Link Design - System-level considerations for optical communication links
• Optical-Electrical Conversion - Photodetectors, lasers, and modulators at the optical-electrical interface
• Signal Integrity - Broader context of electrical and optical signal integrity