Electronics Guide

Elements of a Stackup Specification

A complete specification records the following:

• The number of copper layers and the function assigned to each
• The finished copper thickness of every layer, usually stated as a copper weight in ounces per square foot
• The laminate and prepreg materials by manufacturer and grade, along with glass style and resin content where they matter
• The dielectric thickness between each pair of adjacent copper layers, with tolerances
• The finished board thickness and its tolerance
• Impedance targets, the layers and geometries they apply to, and the acceptable tolerance
• Soldermask and surface finish, both of which affect outer-layer impedance and high-frequency loss

Cores, Prepreg, and Copper Foil

Understanding how a board is actually built prevents specifications that cannot be manufactured. Rigid multilayer boards are laminated from three ingredients:

• Cores: Fully cured laminate sheets with copper foil bonded to both faces. Inner-layer patterns are etched into these copper faces before lamination.
• Prepreg: Glass cloth impregnated with partially cured resin, supplied without copper. During lamination, heat and pressure melt the resin so it flows into etched areas and bonds adjacent layers together.
• Copper foil: Bare foil placed on the outside of the stack, bonded by the outermost prepreg plies and later plated and etched to form the outer layers.

Because prepreg carries no copper of its own, a conventional build alternates cores and prepreg. This is why even layer counts are natural and odd layer counts are awkward. It also explains why pressed prepreg thickness varies: resin flows away from dense copper regions and pools in open areas, so the final dielectric thickness depends on copper coverage as well as on the glass style chosen.

Layer Types and Functions

Each copper layer is assigned one of a few roles:

• Signal layers: Carry routed traces. Every layer intended for high-speed signals needs a solid reference plane on at least one adjacent layer.
• Ground planes: Provide the return path for signal currents, the reference for impedance control, and shielding between layers. Ground planes are the single most valuable resource in a high-speed stackup.
• Power planes: Distribute one or more supply rails at low impedance and serve as alternating-current references in the same way ground planes do, provided they are well decoupled to ground.
• Mixed layers: Combine routed traces with poured plane regions. Mixed layers save layer count on cost-sensitive boards, but every plane split becomes a potential return-path discontinuity for any trace that crosses it.

Core Rules

A small set of rules covers most of what layer ordering has to accomplish:

• Give every signal layer an adjacent reference plane. Return current follows the path of least impedance, which at high frequency means directly beneath the trace. A signal layer with no adjacent plane has no defined impedance and no controlled return path.
• Do not place two signal layers adjacent to each other unless the design accepts dual-stripline behavior. When two routing layers share the same pair of reference planes, broadside coupling between them can be severe. If the arrangement is unavoidable, route the two layers orthogonally and separate them with as much dielectric as the stackup allows.
• Keep the stack symmetric about the centerline. Mirroring copper weights and dielectric thicknesses balances the resin and copper shrinkage that occurs during lamination and reflow, which limits warp and twist.
• Shield the outer layers. Placing a plane immediately below each surface layer both defines microstrip impedance and reduces radiated emissions from surface traces.
• Pair power planes with ground planes. A closely spaced power-ground pair supplies interplane capacitance exactly where discrete decoupling capacitors become ineffective.
• Minimize reference-plane changes. Assign critical nets to layers that let them run between the same pair of planes from source to load, so that via transitions do not force return current to hunt for a stitching path.

Four-Layer Stackups

The four-layer board is the entry point to controlled-impedance design. The conventional arrangement is:

• Layer 1: Signal (top)
• Layer 2: Ground plane
• Layer 3: Power plane
• Layer 4: Signal (bottom)

Both signal layers are microstrips referenced to an adjacent plane, which is the main reason this arrangement works well. Its weakness is power distribution. On a standard 1.57 mm (0.062 in) board, layers 2 and 3 are separated by a thick core, often around 1 mm, so interplane capacitance between them is negligible and the power distribution network depends entirely on discrete decoupling.

Some designers invert the proportions, pulling layers 2 and 3 close together with a thin core and using thick prepreg to the outer layers. That recovers useful plane capacitance but pushes the signal-to-plane spacing on the outer layers out to 15 mils or more, which forces impractically wide traces for a 50 ohm microstrip. The usual compromise on cost-sensitive four-layer boards is to keep the conventional arrangement, treat layer 3 as a ground-dominant mixed plane with power poured only where it is needed, and rely on well-placed decoupling.

Six-Layer Stackups

Six layers buy either routing density or reference quality, and the two goals pull in opposite directions. The traditional density-oriented arrangement is:

• Layer 1: Signal (top)
• Layer 2: Ground plane
• Layer 3: Signal (inner)
• Layer 4: Signal (inner)
• Layer 5: Power plane
• Layer 6: Signal (bottom)

This gives four routing layers, but layers 3 and 4 form a dual stripline. They share the same reference planes and couple to each other broadside, so they demand orthogonal routing, generous vertical separation, and restraint about which nets go there. The power and ground planes are also at opposite ends of the stack, so interplane capacitance is minimal.

The signal-integrity-oriented alternative sacrifices one routing layer for a much cleaner cross-section:

• Layer 1: Signal (top)
• Layer 2: Ground plane
• Layer 3: Signal (stripline)
• Layer 4: Power plane
• Layer 5: Ground plane
• Layer 6: Signal (bottom)

Here every signal layer sits directly against a plane, layer 3 is a buried stripline with strong electromagnetic containment, and layers 4 and 5 form a closely spaced power-ground pair. Boards carrying multi-gigabit serial lanes or fast memory buses generally justify the lost routing layer.

Eight-Layer Stackups

Eight layers allow four routing layers and four planes without compromise:

• Layer 1: Signal (top)
• Layer 2: Ground plane
• Layer 3: Signal (stripline)
• Layer 4: Power plane
• Layer 5: Ground plane
• Layer 6: Signal (stripline)
• Layer 7: Ground plane
• Layer 8: Signal (bottom)

Every signal layer is adjacent to a plane, no two routing layers are adjacent, the arrangement is symmetric about the centerline, and layers 4 and 5 form a tightly coupled plane pair. Designs that need plane-level distribution for two separate rails sometimes replace layer 5 with a second power plane, but two adjacent power planes provide no decoupling to ground; if the design goes that way, each rail still needs its own path to ground capacitance elsewhere in the stack.

Ten Layers and Beyond

Above eight layers the pattern usually repeats: additional plane-signal pairs are inserted toward the middle of the stack, and the most demanding nets are given stripline layers that never change reference. Higher layer counts also open options that thinner stacks cannot support, such as dedicating a plane pair to a single noisy rail, isolating analog and digital reference regions on separate layers, or inserting an ultra-thin dielectric between a power-ground pair to raise interplane capacitance. Layer count should still be driven by routing density and reference requirements rather than added as insurance.

Interplane Capacitance

A power plane and a ground plane separated by a thin dielectric form a parallel-plate capacitor distributed across the whole board. The capacitance follows the parallel-plate relation, so it scales with area and with dielectric constant and falls inversely with separation. For FR-4 with a dielectric constant near 4.3, a separation of 1 mil yields roughly 1 nF per square inch of overlapping plane area; at 4 mils the figure drops to roughly 0.25 nF per square inch.

Those numbers are small compared with the bulk and ceramic decoupling on a typical board, so interplane capacitance is not a substitute for discrete decoupling. Its value lies in the frequency range where mounted ceramic capacitors have already become inductive. Because the plane pair has almost no mounting inductance, it continues to supply charge above a few hundred megahertz, filling the gap between discrete decoupling and on-package or on-die capacitance. Bringing the plane pair from a 4 mil separation down to 2 mils doubles the capacitance for essentially no cost in layer count.

Plane Splits and Return Paths

Every split in a reference plane is a discontinuity for any trace that crosses it. The return current cannot follow the trace across the gap, so it detours around the split, enlarging the current loop and producing crosstalk, radiated emissions, and impedance discontinuity. Two habits keep this under control: route critical nets so they never cross a split in their reference plane, and place stitching capacitors near unavoidable crossings so the return current has a low-impedance path between the two references. Where a signal changes layers between different reference planes, a nearby ground stitching via or stitching capacitor performs the same job for the via transition.

The stackup itself can reduce the problem. Assigning power splits to a layer that is not the primary reference for any high-speed net, and keeping at least one uninterrupted ground plane spanning the full board area, removes most opportunities for a return path to break.

Standard FR-4

FR-4 designates a family of flame-retardant woven-glass and epoxy laminates rather than a single specified material. Its typical properties are:

• Dielectric constant: Roughly 4.2 to 4.8 at 1 MHz, falling to about 4.4 near 1 GHz and toward 4.2 and below at several gigahertz
• Loss tangent: Commonly 0.017 to 0.025 at 1 GHz, with 0.02 the usual worst-case figure quoted by suppliers
• Glass transition temperature: 130°C to 140°C for standard grades, 170°C to 180°C for high-Tg grades intended for lead-free assembly
• Applications: Serviceable for digital signals into the low gigahertz range and for short multi-gigabit links, given adequate design margin

The wide tolerance is the real limitation. Because the specification governs flammability and general performance rather than tightly controlled electrical parameters, dielectric constant and loss vary among suppliers, between grades from the same supplier, and with resin content. Designs that depend on precise impedance should name a specific laminate and grade, not simply "FR-4."

Low-Loss and High-Performance Laminates

Where FR-4 runs out of margin, several classes of laminate are available:

• High-Tg and improved epoxy systems (for example, Isola IS410 and Park Nelco N4000-13): Retain FR-4 processing and cost characteristics while offering higher thermal endurance and tighter property control. They improve thermal reliability more than they improve loss.
• Low-loss epoxy and modified-resin laminates (for example, Isola I-Speed and I-Tera, Panasonic Megtron 6 and Megtron 7): Substantially lower dissipation factor and better-controlled dielectric constant, aimed squarely at multi-gigabit digital backplanes and high-layer-count boards. They process on conventional lines, though often with modified lamination profiles.
• Hydrocarbon-ceramic laminates (for example, Rogers RO4350B and RO4003C): Very low loss and tightly held dielectric constant, developed for radio-frequency and microwave circuits but widely used in hybrid stackups. RO4350B is specified at 3.48 ± 0.05 measured at 10 GHz, with a higher design value of 3.66 recommended for impedance modeling; RO4003C is specified at 3.38 ± 0.05, with a design value of 3.55. Both carry a cost premium of several times standard FR-4.
• PTFE-based laminates: The lowest loss available, used at microwave and millimeter-wave frequencies. They require specialized drilling, surface preparation, and lamination processes, and not every fabricator handles them.

Hybrid stackups place premium laminate only on the layers that carry the critical signals and use conventional material elsewhere. This controls cost but complicates lamination, since materials with different resin systems, flow characteristics, and coefficients of thermal expansion must be pressed together. Hybrid construction should always be reviewed with the fabricator before the stackup is fixed.

Dielectric Constant in Practice

The dielectric constant governs both propagation delay and characteristic impedance, so its accuracy determines whether the first fabricated board meets its impedance targets.

• Lower dielectric constant increases propagation velocity and permits wider traces for the same impedance, which reduces conductor loss and eases manufacturing.
• Dielectric constant falls gradually with frequency in these materials, so a value measured at 1 MHz will overstate impedance if applied at multi-gigahertz rates.
• Dielectric constant also shifts with temperature, moisture uptake, and resin content, all of which should be treated as contributors to the impedance tolerance budget.
• Some suppliers publish both a measured process value and a higher design value intended for use in field solvers. Using the process value in an impedance model produces traces that come out too narrow.

Loss Tangent and Attenuation

Loss tangent, also called dissipation factor, sets the dielectric contribution to channel attenuation:

• Dielectric attenuation per unit length grows roughly in proportion to frequency, while conductor attenuation grows with the square root of frequency. Above a few gigahertz the dielectric term therefore dominates on any appreciable trace length.
• The relevant figure is total channel loss in decibels at the Nyquist frequency of the link, not loss tangent alone. Material choice, trace length, trace width, and via count all enter the same budget.
• For links at 10 Gbps and above, the loss budget should be established before the stackup is fixed, because it determines both material grade and the minimum practical trace width.
• Equalization can recover some loss, but it cannot recover reflections and resonances caused by a poor cross-section.

Glass Style, Resin Content, and the Fiber Weave Effect

Woven-glass laminates are not electrically uniform. E-glass has a dielectric constant near 6, while the resin sits near 3, so the weave imposes a periodic variation in local dielectric constant across the board. Common glass styles and their approximate pressed thicknesses are 106 at about 50 μm (2 mils), 1080 at about 60 to 75 μm (2.4 to 3 mils), 2116 at about 90 to 115 μm (3.5 to 4.5 mils), and 7628 at about 170 to 190 μm (6.7 to 7.5 mils). Final thickness depends on resin content and on how much copper the prepreg has to fill.

When the two halves of a differential pair happen to run over different parts of the weave, one conductor travels mostly over glass and the other mostly over resin. The resulting difference in propagation velocity produces intra-pair skew, which converts differential signal into common mode and erodes eye margin. The effect grows with trace length and with edge rate, and it is a leading cause of unexplained skew on multi-gigabit links. Practical mitigations include:

• Specifying mechanically spread or flat glass styles, which distribute the yarn more evenly and reduce the amplitude of the variation
• Using higher resin content, which raises the resin fraction seen by every trace
• Routing differential pairs at an angle to the weave, either by deliberate zig-zag routing or by rotating the board image a few degrees on the manufacturing panel
• Building the dielectric from several thin plies of different glass styles so that the weave patterns do not reinforce one another

Glass style also has a direct effect on impedance. Two prepregs of nominally the same thickness but different styles carry different resin fractions and therefore different effective dielectric constants, so the stackup should name glass styles wherever impedance tolerance is tight.

Standard Copper Weights

Copper weight expresses the thickness of a copper layer as the weight of foil per square foot:

• 0.5 oz (about 17 μm): Thin foil for fine-pitch routing and tight impedance control. Etching is more accurate because less copper has to be removed.
• 1 oz (about 35 μm): The default for signal layers and most planes. Best balance of current capacity, cost, and etch resolution.
• 2 oz (about 70 μm): Heavy copper for power planes and high-current traces. Wider etched spacing is required, and impedance control becomes more difficult.
• 3 oz and heavier: Power electronics and high-current distribution. Requires fabricators equipped for heavy copper, and design rules loosen considerably.

Outer layers are a special case. Foil placed on the outside of the stack is plated during through-hole metallization, so a 0.5 oz starting foil typically finishes near 1 oz and a 1 oz starting foil finishes near 1.5 oz or more. Stackup documents should distinguish base foil weight from finished weight, since impedance models must use the finished value.

Foil Roughness and Conductor Loss

Copper foil is deliberately roughened so that it adheres to the resin. That roughness matters electrically once the skin depth becomes comparable to the tooth profile. Skin depth in copper is roughly 2 μm at 1 GHz and falls to under 1 μm at 10 GHz, so at multi-gigabit rates the current is confined to a layer thinner than the surface texture and must follow a longer, more resistive path.

Foil grades address this directly. Standard high-temperature-elongation foil has the coarsest profile; reverse-treated foil, very-low-profile foil, and hyper-very-low-profile foil progressively reduce it, at increasing cost and with tighter process requirements for adhesion. Inner-layer oxide or oxide-alternative treatments add roughness of their own. For channels above roughly 5 GHz, foil roughness can contribute a significant fraction of total conductor loss, and field solver models should include a roughness correction rather than assume smooth conductors.

Current-Carrying Capacity

Copper weight must satisfy current requirements at an acceptable temperature rise:

• IPC-2152 is the reference for current-carrying capacity. It supersedes the older IPC-2221 charts and accounts for board thickness, thermal conductivity, and copper distribution, which the earlier curves did not.
• Internal layers are surrounded by dielectric and lose heat less readily than external layers, so internal traces of the same width run hotter.
• Continuous current, intermittent duty, and short pulses lead to very different conductor sizes; sizing for a peak that lasts microseconds wastes copper.
• Nearby traces, plane copper, and thermal vias all change the local thermal environment, so charts should be treated as a starting point and confirmed by measurement or simulation on high-current designs.

Impedance and Manufacturing Implications

Copper thickness enters the impedance calculation directly and the manufacturing tolerance indirectly:

• Thicker copper lowers the impedance of a trace of a given width, so heavier layers require wider traces for the same target.
• Etching produces a trapezoidal rather than rectangular cross-section, and the trapezoid becomes more pronounced with thicker copper. Field solvers should model the actual etch factor.
• Plating thickness variation across a panel translates directly into impedance variation on outer layers, which is one reason critical controlled-impedance nets are often placed on inner layers.
• High-speed designs frequently specify 0.5 oz base foil on signal layers precisely to reduce these effects.

Mixed Copper Weights

Many designs benefit from different weights on different layers, for example 0.5 oz on signal layers for fine routing and impedance control, with 2 oz on power planes for low direct-current resistance and better heat spreading. Mixed-weight construction is routine at most fabricators but adds material handling and cost, and it complicates symmetry. Balance the stack by mirroring weights about the centerline wherever possible, and confirm the specific combination with the fabricator before committing.

Controlled Impedance Fundamentals

Traces behave as transmission lines when the signal edge is fast relative to the propagation delay along the trace. Controlling characteristic impedance keeps reflections small and preserves the eye:

• Single-ended: 50 ohms is the general-purpose target for digital and radio-frequency work; 75 ohms is standard in video and broadcast.
• Differential: Targets are set by the interface standard. PCI Express specifies 85 ohms differential, USB specifies 90 ohms, and Ethernet, HDMI, DisplayPort, and most LVDS and SerDes interfaces use 100 ohms.
• Tolerance: ±10% is the usual production target. Interfaces with tight loss and reflection budgets, including the later PCI Express generations, commonly call for ±7% or ±5%, which raises cost and may narrow the choice of fabricator.

Because differential impedance depends on the coupling between the two conductors as well as on each conductor's impedance to the reference, differential targets constrain trace spacing as tightly as they constrain trace width.

Microstrip Versus Stripline

Two geometries dominate PCB transmission lines:

• Microstrip: A trace on an outer layer with one reference plane below and air or soldermask above. Microstrips are easy to probe and rework and are faster for a given dielectric because part of the field travels in air. They radiate more, are exposed to external coupling, and are more sensitive to plating and soldermask variation.
• Stripline: A trace on an inner layer with reference planes above and below. Striplines contain their fields almost entirely, giving lower emissions and better crosstalk isolation and more stable impedance, at the cost of slower propagation, no access for rework, and additional via transitions.
• Dual stripline: Two routing layers sharing one pair of reference planes. It recovers a routing layer, but the two layers couple broadside, so orthogonal routing and maximum vertical separation between them are mandatory.
• Asymmetric stripline: A stripline positioned closer to one plane than the other. It is perfectly usable, but the impedance model must reflect the actual offset rather than assume a centered conductor.

Impedance Calculation and Modeling

Closed-form impedance equations are useful for intuition and inadequate for production. A two-dimensional field solver, run against the actual stackup, should be the basis for released trace geometry:

• Model the finished copper thickness, including plating on outer layers, rather than the base foil weight.
• Include soldermask on outer-layer microstrips. Mask covers part of the field that would otherwise be in air and typically lowers microstrip impedance by a few ohms.
• Model trapezoidal cross-sections with the fabricator's etch factor, not ideal rectangles.
• Apply a conductor roughness correction for channels above a few gigahertz.
• Use the supplier's design dielectric constant where one is published, at a frequency relevant to the signal.
• Have the fabricator run its own model against its actual materials and press schedule, and reconcile any disagreement before release.

Trace Geometry and Manufacturability

Impedance, dielectric thickness, and trace width form a single system:

• For a fixed dielectric thickness, wider traces have lower impedance; for a fixed trace width, thinner dielectric lowers impedance.
• Thin dielectrics therefore yield narrow traces at a given impedance. Narrow traces cost more in conductor loss and are harder to hold in tolerance, so the thinnest possible dielectric is not automatically the best choice.
• Escape routing under fine-pitch packages usually sets the minimum practical trace width, which in turn sets the maximum usable dielectric thickness on that layer.
• Verify that the widths the field solver produces sit comfortably above the fabricator's minimum, not at it. Designing to the process limit converts normal variation into yield loss.

Verification

Controlled impedance is verified on test coupons fabricated on the same panel as the boards, measured by time-domain reflectometry. The stackup document should state which layers and geometries are to be tested, the target impedance and tolerance for each, and whether a test report is required with each shipment. Coupons consume panel area and testing adds a per-lot charge, so specify testing where it protects a real requirement rather than by default.

Heat Spreading Through the Stack

Copper is roughly three orders of magnitude more thermally conductive than the laminate around it, so the copper layers do nearly all the lateral heat spreading in a board:

• Continuous planes spread heat far more effectively than fragmented copper pours, which is an argument for keeping at least one plane unbroken.
• Heavier copper on planes improves both direct-current resistance and thermal spreading.
• External layers shed heat to ambient air; internal layers must conduct it outward or through vias before it can leave the board.
• Vertical conduction through the laminate is poor, so the stack cannot move heat between layers without via structures.

Thermal Vias

Thermal vias provide the vertical path that the dielectric cannot:

• Place arrays of vias directly under the thermal pads of power devices and connect them to internal plane copper for spreading.
• Many small vias generally outperform a few large ones, because plated barrel area rather than hole volume carries the heat.
• Filled and capped via-in-pad construction improves both thermal transfer and assembly yield under bottom-terminated packages, at additional cost.
• Thermal via arrays interact with assembly: unfilled vias in pads wick solder away from the joint and cause voiding.

Copper Balance and Warp

Copper and resin shrink by different amounts as a laminated panel cools. When copper coverage differs substantially between the top and bottom halves of the stack, the mismatch bends the board:

• Mirror copper weight and approximate copper coverage about the centerline.
• Add non-functional balancing copper in sparse areas where coverage cannot otherwise be matched, keeping it clear of high-speed structures.
• Ask the fabricator for its maximum acceptable coverage imbalance; the tolerance narrows as panels get thinner and larger.
• Warp shows up as coplanarity failures at assembly, particularly under large ball grid arrays, and is expensive to diagnose after the fact.

High-Power Construction

Power conversion and high-current designs push the stackup in a different direction. Heavy copper of 2 oz or more becomes the norm for distribution layers, and extreme cases use metal-core boards or insulated metal substrates, in which the circuit layer sits on a thin dielectric bonded to an aluminum or copper base. These constructions move heat exceptionally well but typically support only one or two circuit layers, so they suit power stages rather than mixed digital boards. Thermal simulation is worth the effort here, because copper distribution, via placement, and airflow interact in ways that hand calculation does not capture.

Layer Count and Build Sequence

Fabrication processes constrain which stackups are practical:

• Conventional boards alternate etched cores and prepreg plies, pressed in a single lamination cycle.
• Even layer counts follow naturally from that construction and are the most economical.
• Odd layer counts above two require an unbalanced build and generally cost more than the next even count, so there is rarely a reason to specify them.
• At least two prepreg plies are usually required between adjacent etched layers to guarantee reliable fill and adequate dielectric spacing.

Dielectric Thickness Control

Dielectric thickness is the parameter that impedance is most sensitive to, and it is set by process rather than by machining:

• Pressed thickness depends on glass style, resin content, copper coverage, and press profile. Two boards built to the same nominal stackup by different shops can differ measurably.
• A tolerance of ±10% on dielectric thickness is typical; tighter control is available at added cost and may require the fabricator to select specific glass and resin combinations.
• Layers below roughly 2 mils require specific thin glass styles such as 106, careful resin selection, and close attention to copper coverage; they are common in high-speed work but leave less margin.
• Thicker prepreg builds are more forgiving but yield wider traces for a given impedance, which may not fit under fine-pitch packages.

Aspect Ratio Limits

Plating chemistry must reach the center of every drilled hole, which limits how thick a board can be relative to its smallest via:

• Many volume fabricators quote 8:1 to 10:1 as standard through-hole aspect ratio, with 12:1 to 20:1 available as an advanced capability.
• Thick boards with small vias may need larger drills, thinner construction, or a shift to blind and buried structures.
• Back-drilling shortens the plated barrel that must be filled and is often driven by signal integrity, but it also interacts with board thickness and drill depth control.
• High-density interconnect construction sidesteps the limit for the outer layers by using laser-drilled microvias, which span only one dielectric layer.

Registration Tolerances

Inner layers must line up with each other and with the drilled holes after lamination shrinkage:

• Layer-to-layer registration is typically held to about ±0.05 mm to ±0.15 mm (±2 to ±6 mils), depending on panel size, layer count, and shop capability.
• Registration error sets the minimum annular ring, and therefore the minimum pad size around every drilled hole.
• High layer counts and large panels accumulate more error, so annular ring rules should be checked against the actual layer count rather than a generic figure.
• Fine-pitch ball grid arrays and high-density interconnect designs are the first casualties of loose registration, since pad and antipad sizes are already at the limit.

Working With the Fabricator

Stackup design is a collaboration, and the fabricator holds information the designer does not:

• Request a proposed stackup from the intended fabricator before layout begins, and provide the impedance targets and layer functions rather than only a thickness table.
• State impedance requirements as target and tolerance per layer and geometry, and identify which nets they apply to.
• Review the fabricator's capability document and design to a margin inside its limits, not at them.
• Confirm material availability and lead time; premium laminates and specific glass styles are not always in stock.
• Ask which parameters the fabricator will adjust to hit impedance. Most will change trace width or dielectric thickness within agreed bounds, and the designer needs to know which.

What Drives Cost

Stackup decisions have a direct and often underestimated effect on board price:

• Layer count: Each added layer pair adds material, an etch and inspection cycle, and lamination content. Cost rises steadily with layer count, and the increase is steeper on small production runs where setup is amortized over fewer boards.
• Materials: Low-loss and hydrocarbon-ceramic laminates cost several times standard FR-4 per unit area, and hybrid stackups add engineering and process risk on top of material cost.
• Copper weight: Heavy copper raises material cost and forces looser design rules, which can push the design to a larger board or a higher layer count.
• Board thickness: Non-standard finished thicknesses may require custom builds. Standard finished thicknesses such as 0.8 mm, 1.0 mm, 1.57 mm (0.062 in), and 2.36 mm (0.093 in) are cheapest.
• Controlled impedance: Adds coupon area, test time, and a per-lot charge, and tighter than standard tolerance narrows the field of qualified suppliers.
• Advanced construction: Sequential lamination, blind and buried vias, back-drilling, and cavity work each add process steps and yield risk.

Controlling Cost Without Losing Performance

• Use the smallest layer count that satisfies routing density and reference-plane requirements, and prove the requirement before adding a pair.
• Keep standard FR-4 unless a loss budget or thermal requirement genuinely rules it out; on short traces, better routing often buys more margin than better material.
• Restrict premium material and tight impedance tolerance to the layers and nets that need them.
• Start from the fabricator's standard stackups, which use materials already in stock and press schedules already qualified.
• Reserve advanced construction for the specific problem it solves. Back-drilling is worthwhile on a long backplane channel and wasted on a short board-level link.
• Design with margin against process limits. Yield loss is a cost, and it is usually larger than the saving that caused it.

Thermal Cycling

The stackup determines how the board responds to repeated heating and cooling:

• Symmetric construction limits the warp and internal stress that thermal cycling would otherwise accumulate.
• Mismatch in coefficient of thermal expansion between copper, resin, glass, and attached components drives stress at every interface. Expansion in the board's thickness direction, which is far less constrained than the in-plane directions, is the usual cause of plated barrel failure.
• Via barrel cracking becomes more likely as boards get thicker and vias get smaller, which is another consequence of aspect ratio.
• Glass transition temperature should be chosen for the assembly process as well as the operating environment. Lead-free reflow peaks well above 240°C, and standard-Tg material spends that excursion above its transition point.
• Decomposition temperature and time to delamination are better predictors of assembly survival than glass transition temperature alone, particularly for thick boards and multiple reflow cycles.

Mechanical Robustness

Physical durability follows from thickness and copper distribution:

• Thicker boards and higher layer counts are stiffer, which helps connector retention and resists flexing during handling.
• Stiffness is not always desirable: a rigid board transmits shock and vibration directly to solder joints under large components.
• Balanced copper improves dimensional stability and reduces the risk of coplanarity problems at assembly.
• Boards subject to vibration should be evaluated for resonance with the mounting scheme rather than for stiffness alone.

Environmental Exposure

The operating environment feeds back into material and stackup choices:

• Moisture absorption raises both dielectric constant and loss, and moisture trapped in laminate can vaporize during reflow and cause delamination. Bake before assembly where the material and storage conditions warrant it.
• Sustained high-temperature operation calls for materials rated for it, and accelerates resin degradation in materials that are not.
• Conductive contamination and humidity together drive conductive anodic filament growth between closely spaced vias, which is influenced by glass style, drilling quality, and via-to-via spacing set in the stackup.
• Automotive, aerospace, and medical programs frequently impose qualified material lists and additional testing, which should be settled before a laminate is designed in.

Back-Drilling

A through via that connects layer 1 to layer 3 still has a plated barrel running to layer 8. That unused length is a resonant stub:

• The stub behaves as an open-circuited transmission line and produces a resonant null in the channel response, with the first null occurring where the stub is a quarter wavelength long.
• Controlled-depth back-drilling removes most of the unused barrel after plating, leaving a short residual stub set by depth control tolerance.
• The technique becomes valuable on thick boards and long channels at multi-gigabit rates, and is standard practice on backplanes.
• Blind and buried vias eliminate stubs entirely but require sequential lamination and cost considerably more.
• Back-drilling adds a drilling operation and consumes clearance around the hole, so antipads and neighboring routing must accommodate the larger back-drill diameter.

Sequential Lamination and HDI

High-density interconnect construction builds the board in stages, laminating and drilling more than once:

• Laser-drilled microvias span a single dielectric layer. Under IPC-T-50, a microvia is a blind structure with an aspect ratio no greater than 1:1 and a total depth no greater than 0.25 mm; the older definition based on a diameter of 0.15 mm or less has been superseded.
• Build-up structures are described by notation such as 1+N+1 or 2+N+2, where N is the conventionally laminated core and the leading digits count the sequentially added build-up layers on each face.
• HDI allows escape routing from ball grid arrays with pitches that through vias cannot serve, and shortens via structures enough to remove stub effects on outer layers.
• Microvias may be staggered or stacked. Stacked structures save area but concentrate stress, and the industry has documented thermal-cycling reliability concerns with stacked microvias, so process qualification matters.
• Each additional lamination cycle adds cost, lead time, and registration error, so build-up depth should be driven by the finest component pitch on the board.

Cavities and Embedded Components

Two further techniques change the stackup itself rather than its via structures:

• Cavity construction mills recesses into the laminated board so that tall components sit below the board surface. It reduces assembly height in constrained enclosures at the cost of extra machining, reduced structural integrity around the cavity, and more complex assembly.
• Embedded components place resistors, capacitors, and occasionally active die inside the layer stack. Embedding shortens interconnects and frees surface area, and embedded capacitance placed directly under a package can outperform surface decoupling at high frequency. The trade-offs are specialized materials and processes, limited component values and tolerances, restricted supplier choice, and the fact that an embedded part cannot be reworked.

Gather Requirements

Begin by collecting the constraints that the stackup must satisfy:

1. List every high-speed interface, its impedance target and tolerance, and its channel loss budget.
2. Enumerate supply rails, their currents, and which of them need plane-level distribution.
3. Estimate routing density from the pin counts and pitches of the largest packages, since escape routing usually sets the minimum layer count.
4. Define thermal requirements, including power dissipation by device and available airflow.
5. Establish electromagnetic compatibility targets and any shielding or isolation the board must provide.
6. Record mechanical constraints: board thickness, connector requirements, and enclosure fit.
7. Note cost targets, production volume, and any qualified-material or environmental requirements.

Draft and Refine

Convert the requirements into a candidate cross-section, then iterate:

1. Choose a starting layer count from routing density, then verify that every signal layer can be given an adjacent plane.
2. Assign layer functions and check the arrangement against the core rules, particularly plane pairing and the absence of adjacent routing layers.
3. Select materials from the loss budget and thermal requirements, not from habit.
4. Set copper weights by layer function, keeping the arrangement symmetric.
5. Model each controlled-impedance layer in a field solver, adjusting dielectric thickness and trace width together until impedance targets and minimum widths are both met.
6. Check the resulting finished thickness against connector and enclosure constraints, and against via aspect ratio limits.
7. Send the draft to the fabricator, reconcile its impedance model with yours, and incorporate its material and thickness feedback.

Document and Release

The released stackup drawing should stand on its own:

• A layer diagram showing every copper and dielectric layer in order, with layer names matching the fabrication data
• Material manufacturer, grade, glass style, and resin content where they are specified
• Dielectric thicknesses with tolerances, and copper weights distinguishing base foil from finished thickness
• Finished board thickness with tolerance
• Impedance table listing layer, geometry, target, and tolerance for each controlled structure
• Coupon and test report requirements, and the acceptance criteria for each
• A revision history, so that field failures can be traced to the construction that produced them

Modeling Tools

Stackup and impedance work relies on a few classes of tool:

• Two-dimensional field solvers such as Polar Si9000e compute characteristic impedance from an actual cross-section and are the industry reference for controlled-impedance work.
• Signal integrity simulators such as Siemens HyperLynx combine stackup editing with transmission line and channel simulation.
• Three-dimensional electromagnetic solvers such as Ansys SIwave and HFSS, Cadence Clarity, and Keysight ADS model the structures that two-dimensional solvers cannot, including via transitions, plane resonances, and connector launches.
• Fabricator tools such as online stackup builders and impedance calculators reflect the materials a specific shop actually stocks, which makes them a useful reality check on any draft.

Relevant Standards

Several IPC documents bear directly on stackup decisions:

• IPC-2141A, Design Guide for High-Speed Controlled Impedance Circuit Boards: Transmission line geometry, impedance relationships, and controlled-impedance design practice
• IPC-2152, Standard for Determining Current-Carrying Capacity in Printed Board Design: Conductor sizing based on measured thermal data
• IPC-2221, Generic Standard on Printed Board Design: Baseline design rules, spacing, and general construction requirements
• IPC-2222 and IPC-2226: Sectional design standards for rigid organic boards and for high-density interconnect structures respectively
• IPC-4101, Specification for Base Materials for Rigid and Multilayer Printed Boards: Laminate and prepreg classification, including the slash sheets that identify specific material types
• IPC-6012, Qualification and Performance Specification for Rigid Printed Boards: Acceptance criteria, including performance classes and plating requirements
• IPC-T-50, Terms and Definitions: The authoritative definitions the other documents depend on, including the current definition of a microvia

Further Study

Stackup design rewards continued study, since materials and process capability keep moving:

• Laminate suppliers publish detailed datasheets, including dielectric constant and loss over frequency, which are more useful than generic material tables.
• Fabricator capability documents and application notes describe what a given shop can actually build, and are updated more often than textbooks.
• Signal integrity and power integrity textbooks cover the underlying electromagnetics that the design rules summarize.
• Industry conferences such as DesignCon and IPC APEX EXPO publish papers on material characterization, microvia reliability, and channel design.