Field-Programmable Gate Arrays
Field-Programmable Gate Arrays (FPGAs) are integrated circuits that bridge the gap between fixed-function hardware and flexible software. Each device contains a large array of programmable logic blocks linked by a configurable routing network, so a designer can implement almost any digital circuit by loading a configuration rather than fabricating custom silicon. The same chip can be erased and reprogrammed to realize an entirely different design, which is why these devices are described as programmable "in the field."
Most contemporary FPGAs build their logic from lookup tables (LUTs), small memories that store the truth table of a Boolean function, paired with flip-flops for sequential logic. The configuration that defines this behavior is held in on-chip memory. The dominant commercial devices use static RAM (SRAM) cells, which accept unlimited reprogramming but must be reloaded at every power-up; flash-based parts retain their configuration without power; and antifuse parts are programmed once and cannot be changed. This reconfigurability gives FPGAs the performance of dedicated hardware with much of the adaptability of a programmable system, supporting rapid prototyping, in-field updates, and hardware acceleration of demanding tasks across telecommunications infrastructure, data centers, aerospace systems, and scientific instruments.
Unlike an application-specific integrated circuit (ASIC), which requires expensive photomasks and a fabrication run measured in months, an FPGA is configured in seconds on the designer's bench. That difference reshapes the engineering trade-off: ASICs reward very high volumes with the lowest unit cost, power, and area, whereas FPGAs win on time to market, low and medium volumes, and any application that must be updated after deployment. The sections that follow look inside the device, examine the flow that turns a hardware description into a working bitstream, and survey where FPGAs are used; the articles listed below then treat architecture, the design flow, implementation techniques, and high-level synthesis in depth.
Inside an FPGA
An FPGA is organized as a two-dimensional array of configurable logic blocks embedded in a sea of programmable interconnect. Each logic block contains one or more lookup tables, which realize combinational functions, together with flip-flops that store state and dedicated carry logic that speeds up addition and counting. Contemporary high-performance families use six-input lookup tables, while smaller and older devices use four-input tables; a single block groups several tables and flip-flops so that it can implement a slice of a larger circuit. The routing network, a hierarchy of wires and programmable switches, connects these blocks, and in a large design the interconnect consumes more silicon area and more of the timing budget than the logic itself.
Building an entire system from lookup tables alone would be wasteful, so modern FPGAs surround the logic fabric with hardened blocks that implement common functions efficiently. Block RAM provides dense on-chip memory, while the lookup tables themselves can be configured as small distributed memories. Digital signal processing (DSP) slices supply fast multiply-accumulate units for filtering and arithmetic. Clock-management circuitry based on phase-locked loops generates and aligns the many clocks a design needs. Around the periphery, configurable input/output blocks interface to external signals, and high-end parts add multi-gigabit serial transceivers, reaching beyond one hundred gigabits per second per lane in the fastest devices, alongside hardened memory controllers, PCI Express endpoints, and Ethernet interfaces.
Configuration Technologies
The behavior of an FPGA is defined by configuration memory that controls every lookup table and every routing switch. Three technologies dominate, and the choice shapes cost, boot time, security, and radiation tolerance.
SRAM-based devices store the configuration in static RAM. They accept unlimited reprogramming and share the same leading-edge process as high-density logic, which makes them the largest and most capable parts on the market. Because SRAM is volatile, the configuration must be reloaded from an external nonvolatile memory at every power-up, which adds boot time and an external component; the stored bits are also susceptible to upset by radiation, a concern in aerospace and high-altitude systems.
Flash-based devices hold the configuration in nonvolatile flash cells. They retain their design without power, start almost instantly, and draw less standby current, which suits low-power and instant-on applications, though they typically offer lower capacity than the largest SRAM parts. Antifuse devices are programmed exactly once by permanently forming connections. They cannot be reused, but they are compact, tamper-resistant, and inherently immune to configuration upset, which makes them attractive for high-reliability, security-sensitive, and radiation-hardened systems.
From Hardware Description to Bitstream
Designing for an FPGA begins not with a program but with a description of digital hardware. Engineers capture behavior at the register-transfer level in a hardware description language such as VHDL, Verilog, or SystemVerilog, specifying the registers, combinational logic, and data paths that make up the circuit. Synthesis translates this description into a netlist of the FPGA's own primitives: lookup tables, flip-flops, block RAM, and DSP slices.
The tools then map that netlist onto the physical device. Place-and-route assigns each element to a specific location and programs the interconnect to wire them together, guided by timing constraints that state how fast each clock must run. Static timing analysis checks every path against those constraints to confirm that the design will meet timing. A final step generates the bitstream, the binary file that sets every configuration bit, which is loaded into the device to bring the circuit to life. High-level synthesis raises the entry point of this flow by compiling algorithms written in C, C++, or OpenCL directly into register-transfer logic, letting software engineers target the fabric without writing it by hand.
FPGAs and ASICs
An FPGA and an ASIC represent two answers to the same question of how to implement a digital circuit. The ASIC commits a design to fixed silicon: it delivers the highest speed, the lowest power, and the smallest die, but it demands a large upfront investment in photomasks and engineering, often millions of dollars at advanced process nodes, and a fabrication cycle measured in months. Any error discovered after tape-out requires a costly new mask set.
The FPGA trades some of that efficiency for flexibility. The same part can be configured in seconds, corrected as often as needed, and updated in the field after a product ships. This makes FPGAs the natural choice for low and medium volumes, for rapidly evolving standards, and for systems with long service lives. Per-unit cost favors the ASIC only after volumes grow large enough to amortize its fixed costs, so many products begin life on an FPGA and migrate to an ASIC once the design stabilizes and demand justifies the move. FPGAs also serve as prototyping and emulation platforms that verify an ASIC design in real hardware long before the first wafer is made.
System-on-Chip FPGAs
Many modern FPGAs are no longer pure logic fabrics. System-on-chip (SoC) FPGAs place one or more hardened processor cores on the same die as the programmable logic, joining software flexibility to hardware acceleration. AMD's Zynq family and Altera's SoC devices pair Arm processor cores with FPGA fabric, while Microchip's PolarFire SoC couples a RISC-V processor to flash-based logic. Software runs on the processor, and the fabric implements the accelerators, interfaces, and real-time functions that a general-purpose core handles poorly.
The tightest integrations go further. AMD's Versal devices add an array of vector-oriented processing engines aimed at signal processing and machine-learning workloads, linked to the logic and the processors by a coherent on-chip network. These heterogeneous platforms let a single chip span control, connectivity, and high-throughput computation, and they turn the boundary between processor and reconfigurable hardware into a design choice rather than a fixed partition.
Applications
FPGAs occupy the applications where performance, flexibility, and moderate volume meet. In telecommunications, they process high-speed data streams in wireless base stations and optical transport equipment and adapt as standards evolve. In data centers, they accelerate network packet processing, storage compression, search, and machine-learning inference, and they can be reprogrammed as workloads change. Aerospace, defense, and space systems rely on FPGAs for low-volume, long-lifetime designs that must sometimes be patched after deployment, using radiation-tolerant flash and antifuse parts where reliability is paramount.
The same adaptability serves many other fields. Automotive systems use FPGAs for advanced driver-assistance sensor fusion; industrial equipment uses them for motion control and machine vision; and test, measurement, and scientific instruments use them to acquire and process data at rates a general-purpose processor cannot sustain. Broadcast and professional video equipment relies on FPGAs for real-time image processing, and chip designers use them to emulate ASICs and prototype new architectures before fabrication.
Origins and the Industry
The FPGA grew out of earlier programmable logic devices in the mid-1980s. The Xilinx XC2064, introduced in 1985, is generally credited as the first commercial FPGA; it offered 64 configurable logic blocks and on the order of a thousand equivalent gates, a modest capacity by present standards but a decisive proof that reconfigurable hardware was practical. By replacing fixed wiring with programmable interconnect, these early parts let engineers revise a design repeatedly without committing to a fabrication run, sharply reducing development risk. Four decades of process scaling have since grown the largest devices to millions of logic cells alongside the hardened memory, arithmetic, and transceiver blocks described above.
The industry that produces these devices is highly concentrated. AMD, which acquired Xilinx in 2022, and Altera lead the market; Altera returned to independence in 2025, when Intel, its owner since 2015, sold a controlling stake to the investment firm Silver Lake. Lattice Semiconductor specializes in small, low-power FPGAs, and Microchip supplies flash-based and antifuse parts favored in reliability- and security-critical systems, while newer suppliers compete in the high-volume, low-cost segment. Each major vendor provides its own design toolchain, and the choice of device usually commits a project to that vendor's software and intellectual-property ecosystem.