Application-Specific Integrated Circuits

An application-specific integrated circuit (ASIC) is a chip designed for a particular use rather than for general-purpose computation. By fixing a function in silicon, an ASIC can achieve far better performance, lower power consumption, and smaller area than a programmable part running the same task. That efficiency comes at the cost of flexibility: once the masks are fabricated, the logic cannot be changed. ASICs power high-volume and performance-critical products, from the processors in smartphones and the controllers in solid-state drives to network switch fabrics and accelerators for artificial intelligence and cryptocurrency mining.

ASICs occupy one end of a spectrum of implementation choices. Full-custom designs hand-craft transistors and interconnect for maximum performance and density, but demand enormous engineering effort. Standard-cell designs, the most common approach today, assemble pre-characterized logic cells from a library and customize every mask layer, balancing performance against design productivity. Gate arrays and structured ASICs prefabricate a base wafer and personalize only the upper metal layers, trading some efficiency for lower cost and faster turnaround. Field-programmable gate arrays sit at the flexible extreme, configured after manufacture and well suited to low volumes and rapidly changing requirements.

The economics of custom silicon are dominated by non-recurring engineering (NRE) costs. A full photomask set at a leading-edge process node costs several million to tens of millions of dollars, and the total NRE for a complex system-on-chip—including design tools, verification, and validation—can reach hundreds of millions. These fixed costs are amortized across every unit shipped, so ASICs make economic sense only when production volumes are high enough or when no programmable alternative can meet the performance, power, or area targets. Getting the chip right before the masks are committed is therefore essential, which makes design methodology, verification, physical implementation, and manufacturability the central disciplines of ASIC engineering.

Articles in This Category

ASIC Design Methodologies - Full-custom, standard-cell, gate-array, and structured-ASIC approaches, along with platform-based design, intellectual-property integration, and design for test.
ASIC Design for Manufacturing - Optimizing a layout for high yield through process-variation analysis, optical proximity correction, design for yield, scan chains, and built-in self-test.
Physical Design - Turning a gate-level netlist into a manufacturable layout through floorplanning, placement, clock-tree synthesis, routing, and power distribution, then closing timing and signing off with design-rule and layout-versus-schematic checks.
Verification and Validation - Proving a design correct before tape-out through functional and formal verification, assertion-based methods, coverage metrics, constrained-random testing, emulation, and post-silicon validation.
VLSI Design - Very-large-scale integration principles: standard-cell methodology, the RTL-to-GDSII flow, design rules, technology scaling, and the trade-offs among power, timing, and area.

About Application-Specific Integrated Circuits

The ASIC grew out of earlier efforts to reduce the cost and risk of custom logic. Gate arrays came first, offering wafers with a fixed sea of transistors that a designer personalized only in the upper metal interconnect layers, which lowered non-recurring cost and shortened turnaround. Standard-cell design followed as electronic design automation matured, letting engineers assemble a chip from libraries of pre-characterized cells and rely on automated synthesis, placement, and routing rather than hand-drawn transistors. Successive process generations pushed integration from a few thousand transistors to many billions, and the system-on-chip—combining processor cores, memory, analog blocks, and specialized accelerators on a single die—became the dominant form of high-end custom silicon.

Choosing an ASIC is fundamentally a make-or-buy decision weighed against programmable and off-the-shelf alternatives. A custom chip wins when volumes are large enough to amortize its non-recurring cost, or when no field-programmable gate array or standard product can meet the required performance, power, or area. Because that non-recurring cost climbs steeply at each new process node, modern practice leans heavily on reusing verified intellectual-property cores and, increasingly, on heterogeneous integration: partitioning a large system into smaller chiplets that are fabricated separately and joined inside an advanced package. These strategies spread cost and risk across reusable pieces, keeping custom silicon viable even as monolithic scaling grows more expensive. The articles in this category treat custom silicon as an engineering discipline in its own right—methodology, verification, physical implementation, and manufacturability. For the same technology seen from the product side, where an ASIC competes with a microcontroller, an FPGA, or an off-the-shelf system-on-chip inside a specific design, see ASICs in embedded system architecture.

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