Application-Specific Integrated Circuits
An application-specific integrated circuit (ASIC) is a chip designed for a particular use rather than for general-purpose computation. By fixing a function in silicon, an ASIC can achieve far better performance, lower power consumption, and smaller area than a programmable part running the same task. That efficiency comes at the cost of flexibility: once the masks are fabricated, the logic cannot be changed. ASICs power high-volume and performance-critical products, from the processors in smartphones and the controllers in solid-state drives to network switch fabrics and accelerators for artificial intelligence and cryptocurrency mining.
ASICs occupy one end of a spectrum of implementation choices. Full-custom designs hand-craft transistors and interconnect for maximum performance and density, but demand enormous engineering effort. Standard-cell designs, the most common approach today, assemble pre-characterized logic cells from a library and customize every mask layer, balancing performance against design productivity. Gate arrays and structured ASICs prefabricate a base wafer and personalize only the upper metal layers, trading some efficiency for lower cost and faster turnaround. Field-programmable gate arrays sit at the flexible extreme, configured after manufacture and well suited to low volumes and rapidly changing requirements.
The economics of custom silicon are dominated by non-recurring engineering (NRE) costs. A single photomask set at a leading-edge process node costs tens of millions of dollars, and the full NRE for a complex system-on-chip—including design tools, verification, and validation—can reach hundreds of millions. These fixed costs are amortized across every unit shipped, so ASICs make economic sense only when production volumes are high enough or when no programmable alternative can meet the performance, power, or area targets. Getting the chip right before the masks are committed is therefore essential, which makes design methodology, verification, physical implementation, and manufacturability the central disciplines of ASIC engineering.
ASIC Topics
These topics follow the arc of an ASIC project. Design methodologies establish how a specification becomes synthesizable register-transfer-level (RTL) code and a gate-level netlist. Verification and validation prove that the design behaves correctly before committing to silicon, since a functional bug discovered after tape-out can mean a costly re-spin. Physical design turns the netlist into a manufacturable layout through floorplanning, placement, clock-tree synthesis, and routing while meeting timing and power goals. Design for manufacturing ensures the layout can be produced with high yield, accounting for lithography limits, process variation, and reliability.