Switched-Capacitor Circuits

Switched-capacitor circuits represent a fundamental technique in analog integrated circuit design that enables discrete-time analog signal processing using only capacitors, switches, and operational amplifiers. By periodically transferring charge between capacitors at a clock-controlled rate, these circuits can emulate the behavior of resistors and implement precise analog functions without requiring the accurate resistors that are notoriously difficult to fabricate in standard CMOS processes. This approach has revolutionized the design of integrated filters, data converters, and precision analog circuits.

The elegance of switched-capacitor techniques lies in their ratio-metric nature: circuit performance depends on capacitor ratios rather than absolute values, and these ratios can be controlled with remarkable precision in integrated circuit fabrication. When combined with the accurate clock frequencies available from crystal oscillators or digital systems, switched-capacitor circuits achieve levels of accuracy and repeatability that would be impractical with continuous-time analog approaches. This article explores the principles, building blocks, and advanced techniques that make switched-capacitor circuits essential to modern analog design.

Fundamental Principles

The foundation of switched-capacitor circuit operation rests on a simple but powerful concept: a capacitor that is periodically switched between two voltage nodes transfers charge at an average rate equivalent to a resistor connecting those nodes. This equivalence enables the replacement of resistors with switched capacitors, fundamentally changing how analog circuits can be implemented in integrated form.

Resistor Emulation

Consider a capacitor C that is alternately connected between an input voltage Vin and a virtual ground (such as the inverting input of an operational amplifier) by complementary clock phases. During one clock phase, the capacitor charges to Vin, acquiring charge Q = C * Vin. During the next phase, this charge transfers to the virtual ground. If the clock frequency is fclk, the average current flowing is:

Iavg = Q * fclk = C * Vin * fclk

This is equivalent to a resistor with value:

Req = Vin / Iavg = 1 / (C * fclk)

This fundamental relationship shows that the equivalent resistance depends only on the capacitance and clock frequency, both of which can be controlled with high precision. Unlike physical resistors in integrated circuits, which may vary by 20% or more due to process variations, capacitor ratios can be matched to within 0.1% and clock frequencies can be controlled to parts per million.

Clock Phases and Timing

Switched-capacitor circuits operate using non-overlapping clock phases, typically denoted as phi1 and phi2. These clock signals must never be simultaneously high to prevent charge sharing and signal-dependent errors. The non-overlap period, during which both clocks are low, allows switches to fully open before others close, ensuring controlled charge transfer.

Key timing considerations include:

Non-overlap time: Must be sufficient for switches to fully turn off before complementary switches turn on, typically a few nanoseconds to tens of nanoseconds
Clock frequency: Determines the equivalent resistance and must be much higher than signal bandwidth to avoid aliasing
Duty cycle: Usually 50% for balanced operation, though some circuits use asymmetric clocks for specific purposes
Clock feedthrough: Capacitive coupling from clock signals to analog nodes must be minimized through careful design

Sampling and Discrete-Time Operation

Switched-capacitor circuits inherently operate in discrete time, sampling the input signal at the clock rate. This sampled-data nature has important implications:

Nyquist criterion: The clock frequency must be at least twice the highest input frequency to avoid aliasing
Anti-aliasing filtering: A continuous-time filter is typically required before the switched-capacitor circuit to remove frequencies above half the clock rate
Reconstruction filtering: A smoothing filter may be needed at the output to remove clock-rate components
Signal-to-noise considerations: Thermal noise is sampled onto capacitors, contributing kT/C noise that sets fundamental limits on dynamic range

Basic Switched-Capacitor Integrators

The integrator is the most fundamental building block in switched-capacitor circuit design. Just as continuous-time active filters are built from op-amp integrators, switched-capacitor filters and signal processors are constructed from switched-capacitor integrators. Understanding these basic structures is essential for comprehending more complex switched-capacitor systems.

Non-Inverting Integrator

The parasitic-sensitive non-inverting integrator uses a sampling capacitor Cs that connects to the input during one clock phase and to the integrating capacitor Ci during the complementary phase. During phi1, Cs charges to the input voltage. During phi2, the charge on Cs transfers to Ci, adding to the integrated output. The transfer function in the z-domain is:

H(z) = (Cs/Ci) * z^(-1) / (1 - z^(-1))

The z^(-1) term represents a one-sample delay, characteristic of discrete-time systems. The gain coefficient Cs/Ci depends only on the capacitor ratio, demonstrating the ratio-metric advantage of switched-capacitor circuits.

Inverting Integrator

The inverting integrator achieves a sign change in the integration by reversing the connection sequence of the sampling capacitor. The charge transferred to the integration capacitor has opposite polarity relative to the input, producing:

H(z) = -(Cs/Ci) * 1 / (1 - z^(-1))

Note that this inverting integrator has no z^(-1) delay in the numerator, making it delay-free. This distinction between delayed and delay-free integrators is crucial in designing switched-capacitor filters, where the proper combination of these types determines filter characteristics.

Differential Integrators

Modern switched-capacitor circuits predominantly use fully differential architectures to improve power supply rejection, increase dynamic range, and reduce even-order harmonic distortion. A differential integrator processes the difference between two input signals and produces a differential output. The structure uses matched sampling and integrating capacitors for each half of the differential signal path, with common-mode feedback circuits maintaining proper operating points.

Bilinear Integration

For improved frequency response accuracy, bilinear integrators use a modified clocking scheme that provides a transfer function closer to the ideal continuous-time integrator. The bilinear transform relationship s = (2/T) * (z-1)/(z+1) is approximated, where T is the clock period. This approach reduces the frequency warping effects inherent in standard forward or backward Euler integrators, particularly important for filters requiring precise frequency response at frequencies approaching the clock rate.

Sample-and-Hold Amplifiers

Sample-and-hold amplifiers (SHA) capture an analog signal at a precise instant and maintain that value for subsequent processing. In switched-capacitor systems, the SHA function is fundamental to the operation of data converters, multiplexed acquisition systems, and any application requiring time-coherent sampling of analog signals.

Basic Sample-and-Hold Operation

The simplest sample-and-hold uses a switch in series with the signal path and a capacitor to ground. During the sample (track) phase, the switch closes and the capacitor voltage follows the input. When the switch opens, the capacitor retains the sampled voltage for the hold phase. An output buffer prevents loading of the hold capacitor.

Key performance parameters include:

Acquisition time: Time required for the held voltage to settle to within a specified accuracy of a new input level after entering track mode
Aperture time: The uncertainty in the exact sampling instant, causing aperture jitter that limits high-frequency performance
Droop rate: The rate at which the held voltage decays due to leakage currents, limiting minimum hold time
Pedestal error: A fixed offset introduced during the sample-to-hold transition due to charge injection from the switch
Hold mode feedthrough: Coupling of input signal changes to the held output during hold mode

Charge Injection Compensation

When MOS switches turn off, charge from the channel is injected onto the hold capacitor, causing signal-dependent errors. Several techniques mitigate this effect:

Bottom-plate sampling: The switch connects to the bottom plate of the sampling capacitor, isolating the sensitive top plate from direct charge injection
Complementary switches: Using both NMOS and PMOS switches whose charge injections partially cancel
Dummy transistors: Half-size transistors that absorb charge injection from the main switch
Fully differential operation: Signal-dependent charge injection becomes a common-mode disturbance that is rejected by differential processing

Bootstrapped Switches

For high-linearity applications, bootstrapped switches maintain constant gate-to-source voltage regardless of input signal level. This technique eliminates the signal-dependent on-resistance variation of simple MOS switches, which would otherwise cause harmonic distortion. The bootstrap circuit charges a capacitor to the supply voltage, then connects this capacitor between gate and source during the on phase, providing a fixed overdrive voltage that tracks the input signal.

Track-and-Hold vs. Sample-and-Hold

The terms are often used interchangeably, but strictly speaking, a track-and-hold (T/H) continuously follows the input during track mode, while a sample-and-hold (S/H) may only briefly acquire the signal before holding. In practice, most modern implementations are track-and-hold circuits that provide continuous tracking until the hold command, offering lower acquisition time and better performance for rapidly changing signals.

Switched-Capacitor Filters

Switched-capacitor filters implement frequency-selective transfer functions using the integrator building blocks described earlier. By connecting integrators with appropriate feedback and feedforward paths, any standard filter response can be realized with accuracy determined by capacitor ratios rather than absolute component values.

First-Order Sections

A first-order low-pass filter requires a single integrator with resistive feedback in the continuous-time domain. In switched-capacitor form, both the input resistor and feedback resistor are replaced by switched capacitors. The resulting discrete-time transfer function provides low-pass behavior with cutoff frequency proportional to the clock frequency and inversely proportional to the capacitor ratios. First-order sections are used as building blocks for higher-order filters and as simple anti-aliasing or smoothing elements.

Biquadratic Sections

Second-order (biquad) sections form the core of most switched-capacitor filter designs. Common topologies include:

Two-integrator loop: The most common structure, using two integrators in a feedback loop to create a second-order transfer function with controllable pole frequency and Q
Fleischer-Laker biquad: A widely used topology that provides low-pass, band-pass, and high-pass outputs simultaneously from a two-integrator loop
Tow-Thomas equivalent: A switched-capacitor implementation of the continuous-time Tow-Thomas biquad, offering good tunability
State-variable structure: Provides multiple filter outputs and allows independent control of frequency and Q

Higher-Order Filter Design

Higher-order filters are constructed by cascading biquad sections, with each section contributing a pair of poles to the overall response. The design process involves:

Prototype selection: Choose the continuous-time filter prototype (Butterworth, Chebyshev, elliptic, etc.) that meets specifications
Frequency transformation: Convert the prototype to the desired cutoff frequency and filter type (low-pass, high-pass, band-pass)
Bilinear transformation: Map the continuous-time poles and zeros to the z-domain, accounting for frequency warping
Section allocation: Group poles and zeros into biquad sections, considering dynamic range and sensitivity
Coefficient calculation: Determine capacitor ratios that realize the required transfer function coefficients

Filter Design Considerations

Practical switched-capacitor filter design must address several factors:

Clock-to-cutoff ratio: Typically 50:1 to 200:1 to minimize frequency warping and aliasing effects
Capacitor spread: The ratio between largest and smallest capacitors should be minimized to reduce area and improve matching
Op-amp requirements: Adequate gain, bandwidth, and slew rate for the clock frequency and signal levels
Dynamic range optimization: Scaling of section gains to maximize signal levels while preventing clipping
Sensitivity: The variation of filter response with component tolerances should be minimized through proper topology selection

Gain Stages and Amplifiers

Switched-capacitor techniques enable the implementation of precision amplifiers whose gain is determined by capacitor ratios rather than resistor matching. This is particularly valuable in integrated circuits where resistors are difficult to fabricate accurately but capacitor ratios can be controlled to better than 0.1%.

Basic Switched-Capacitor Amplifier

The fundamental switched-capacitor amplifier uses a sampling capacitor Cs and a feedback capacitor Cf around an operational amplifier. During the sampling phase, Cs acquires the input voltage. During the amplification phase, the charge transfers to Cf, producing an output voltage:

Vout = -Vin * (Cs / Cf)

The gain depends only on the capacitor ratio, providing accuracy unattainable with continuous-time resistive feedback amplifiers in integrated form. Gains from less than unity (attenuation) to several hundred can be implemented with appropriate capacitor ratios.

Programmable Gain Amplifiers

Programmable gain amplifiers (PGAs) use selectable capacitor arrays to provide digitally controlled gain settings. Common implementations include:

Binary-weighted capacitor arrays: Capacitors with values in powers of two, selected by digital control bits
R-2R equivalent structures: Capacitor networks that provide fine gain resolution with small capacitor spread
Charge redistribution: Gain adjustment through selective charge sharing between capacitors

PGAs are essential in data acquisition systems where input signals span a wide dynamic range and must be scaled to match the input range of subsequent stages.

Residue Amplifiers for ADCs

In pipelined analog-to-digital converters, residue amplifiers amplify the difference between the input and the reconstructed digital approximation for processing by subsequent stages. These amplifiers require:

Precise gain: Typically powers of two (2x, 4x, 8x) for binary-weighted conversion
High linearity: Nonlinearity directly causes ADC distortion
Fast settling: Must settle to required accuracy within a clock phase
Low noise: Noise contribution should not limit converter resolution

Multiply-by-Two Amplifiers

The multiply-by-two (MDAC - multiplying digital-to-analog converter) stage is fundamental to pipelined converters. It performs simultaneous digital-to-analog conversion and residue amplification. The structure samples the input onto capacitors, subtracts a DAC voltage determined by the digital code, and amplifies the difference. Careful design ensures gain accuracy of 2x to better than 0.01% in high-resolution converters.

Common-Mode Feedback

Fully differential switched-capacitor circuits require common-mode feedback (CMFB) to establish and maintain the proper DC operating point at the amplifier outputs. Without CMFB, the high impedance at differential outputs would cause the common-mode level to drift unpredictably, potentially saturating the amplifier.

Common-Mode Feedback Requirements

The CMFB circuit must sense the common-mode output voltage, compare it to a reference, and adjust the amplifier bias to minimize the error. Key requirements include:

Continuous-time sensing: Must maintain common-mode control at all times, including during switched-capacitor transitions
Adequate bandwidth: The CMFB loop must be fast enough to respond to common-mode disturbances
Stability: The CMFB loop must be stable under all operating conditions
Low power: Should not significantly increase overall power consumption
No differential interference: Must not degrade the differential signal path

Continuous-Time CMFB

Continuous-time CMFB circuits use resistive dividers or source-coupled pairs to sense the output common-mode voltage. The sensed voltage controls the tail current or output stage bias of the differential amplifier. Advantages include inherent stability and continuous control, but resistive sensing can load the outputs and affect bandwidth. Source-coupled pair sensing avoids loading but requires careful design to maintain linearity.

Switched-Capacitor CMFB

Switched-capacitor CMFB circuits sample the output voltages onto capacitors and compare the average to a reference. This approach eliminates resistive loading and naturally integrates with the switched-capacitor signal processing. However, the sampled nature means common-mode control is only updated periodically, requiring adequate capacitive filtering to maintain control between sampling instants.

A typical SC-CMFB circuit uses four capacitors: two sample the differential outputs during one phase, and during the next phase, their charges combine on a common node that drives the bias control. The reference voltage is injected through additional capacitors to set the desired output common-mode level.

Hybrid CMFB Approaches

Some designs combine continuous-time and switched-capacitor CMFB to achieve both low loading and continuous control. A continuous-time circuit provides coarse control to prevent saturation, while a switched-capacitor circuit provides precise common-mode regulation. This approach is particularly useful in high-speed applications where purely switched-capacitor CMFB may not respond quickly enough.

Offset Compensation

Operational amplifier offset voltage can significantly degrade the accuracy of switched-capacitor circuits, particularly in high-gain applications and precision data converters. Several techniques exploit the discrete-time nature of switched-capacitor circuits to cancel or reduce offset effects.

Auto-Zeroing

Auto-zeroing (AZ) stores the amplifier offset on a capacitor during a calibration phase, then subtracts this stored offset during normal operation. The basic sequence involves:

Offset sampling: The amplifier is configured with its input shorted (or connected to a reference), and the output offset is stored on a capacitor
Signal processing: During normal operation, the stored offset is subtracted from the signal path, canceling the offset contribution

Auto-zeroing can reduce effective offset from millivolts to microvolts, enabling precision performance from standard CMOS amplifiers. The technique is widely used in instrumentation amplifiers, precision comparators, and data converter front-ends.

Ping-Pong Auto-Zeroing

Continuous-time signal processing with auto-zeroing is achieved using two amplifiers in a ping-pong configuration. While one amplifier processes the signal, the other is being auto-zeroed. The amplifiers alternate roles at the clock rate, providing continuous operation with offset-compensated performance. This technique doubles component count but eliminates dead time during offset calibration.

Chopper Stabilization

Chopper stabilization modulates the input signal to a frequency where amplifier offset and low-frequency noise are absent, then demodulates after amplification. In switched-capacitor implementations, the chopping function is naturally integrated with the clock phases. The effective offset and 1/f noise are translated to the chopping frequency, where they can be filtered out.

The combination of chopping and auto-zeroing provides the best offset and noise performance, reducing effective offset to the nanovolt range and eliminating low-frequency noise below the chopping frequency.

Offset Storage Considerations

The effectiveness of offset compensation depends on the storage capacitor and amplifier characteristics:

Capacitor size: Larger capacitors provide lower kT/C noise but require more area and settling time
Leakage: Stored offset voltage must be maintained throughout the operating phase
Offset drift: Temperature-dependent offset changes must be slow compared to the refresh rate
Amplifier bandwidth: Must be adequate to fully settle during the offset sampling phase

Parasitic-Insensitive Structures

Real integrated capacitors have parasitic capacitances to the substrate and other nearby conductors. These parasitics can cause significant errors in switched-capacitor circuits unless the topology is designed to be insensitive to them. Parasitic-insensitive structures ensure that circuit performance depends only on intentional capacitors, not on layout-dependent parasitics.

Sources of Parasitic Capacitance

Parasitic capacitances in integrated switched-capacitor circuits arise from several sources:

Bottom-plate parasitic: The capacitor electrode closer to the substrate couples to the grounded substrate through the insulating layers
Top-plate parasitic: The upper electrode has smaller but still significant coupling to surrounding conductors
Switch capacitance: Source, drain, and gate capacitances of MOS switches
Interconnect capacitance: Metal routing between components adds parasitic loading

Bottom-plate parasitics are typically 10-20% of the intentional capacitance, making them a dominant source of error if not properly handled.

Parasitic-Insensitive Integrator

The classic parasitic-insensitive integrator connects the bottom plate of the sampling capacitor to a low-impedance node (either the input voltage source or the op-amp virtual ground) at all times. The bottom-plate parasitic capacitance then charges and discharges to fixed voltages, contributing no net charge transfer to the integration capacitor.

The key principle is that parasitic capacitors connected to fixed voltages or virtual grounds do not participate in signal-dependent charge transfer. By ensuring all parasitics see only constant voltages or are connected to driven nodes, their effect on circuit accuracy is eliminated.

Fully Differential Parasitic Insensitivity

Fully differential structures provide additional parasitic rejection by making parasitic effects common-mode. When parasitics couple equally to both differential outputs, the differential signal remains unaffected. This requires careful symmetric layout to ensure matched parasitic loading on both signal paths.

Design Guidelines

Achieving parasitic insensitivity requires attention to circuit topology and layout:

Bottom-plate switching: Always connect the larger bottom-plate parasitic to low-impedance nodes
Clock sequencing: Design switch timing to ensure parasitics see only fixed voltages during critical phases
Symmetric layout: Match parasitic loading in differential circuits through careful physical design
Shielding: Use grounded shields to control parasitic coupling paths
Minimal interconnect: Keep sensitive nodes physically small to minimize parasitic capacitance

Correlated Double Sampling

Correlated double sampling (CDS) is a powerful technique that cancels offset, low-frequency noise, and certain other error sources by taking the difference between two correlated samples. Originally developed for CCD image sensors, CDS has become essential in high-performance switched-capacitor circuits and data converters.

Basic CDS Operation

The CDS technique captures two samples separated in time: a reference sample containing only the error to be canceled, and a signal sample containing both the desired signal and the same error. Subtracting the reference from the signal sample cancels the common error component while preserving the signal.

For amplifier offset cancellation:

First sample: Sample the amplifier output with input grounded, capturing offset and kT/C noise
Second sample: Sample the amplifier output with signal applied, capturing signal plus offset plus kT/C noise
Subtraction: The difference contains only the signal, with offset and correlated noise canceled

Noise Considerations

CDS affects the noise spectrum in important ways:

Low-frequency noise cancellation: Noise components that are correlated between the two samples (such as 1/f noise) are attenuated
High-frequency noise enhancement: Uncorrelated noise components (thermal noise at frequencies higher than half the sampling rate) may increase by up to a factor of square root of two
Optimal sampling interval: The time between samples affects the correlation and thus the noise transfer function

The noise transfer function of CDS is approximately (2 * sin(pi * f * Tcds))^2, where Tcds is the time between samples. This creates a high-pass characteristic that attenuates low-frequency noise but passes (and slightly amplifies) high-frequency components.

CDS in Data Converters

CDS is extensively used in analog-to-digital converters:

Pipelined ADCs: Each stage uses CDS to cancel interstage amplifier offset and reduce low-frequency noise
Delta-sigma modulators: CDS in the front-end reduces integrator offset and noise effects
SAR ADCs: CDS during the sampling phase cancels comparator offset for improved accuracy

Implementation Considerations

Effective CDS implementation requires careful attention to timing and circuit design:

Settling time: The circuit must fully settle before each sample to ensure error components are properly correlated
Sample interval: Must be short enough that errors remain correlated, typically within a single clock period
Clock feedthrough matching: Asymmetric clock feedthrough creates uncorrelated errors that CDS cannot cancel
Capacitor matching: Mismatched sampling capacitors cause incomplete cancellation

Advanced Techniques

Modern switched-capacitor circuit design employs numerous advanced techniques to achieve performance levels approaching fundamental limits. These methods address specific challenges in noise, linearity, speed, and power consumption.

Charge-Domain Processing

Rather than processing voltages, some switched-capacitor circuits operate directly on charge packets. Charge-domain signal processing offers advantages in certain applications:

Linear charge transfer: Charge moves between capacitors without nonlinear amplifier settling
Low-voltage operation: Reduced headroom requirements compared to voltage-mode processing
Natural decimation: Charge accumulation provides inherent averaging and filtering

Time-Interleaved Operation

Time-interleaving uses multiple switched-capacitor channels operating in parallel with staggered timing to increase effective sample rate. Each channel operates at a fraction of the overall rate, relaxing bandwidth and settling requirements. Challenges include matching between channels to avoid interleaving spurs:

Offset mismatch: Different DC offsets cause tones at submultiples of the sample rate
Gain mismatch: Unequal gains create similar spurious components
Timing mismatch: Skew between channel sampling instants causes signal-dependent errors
Bandwidth mismatch: Different frequency responses distort the interleaved output

Background calibration techniques can measure and correct these mismatches during normal operation.

Noise-Shaping Techniques

Noise shaping, fundamental to delta-sigma converters, can be applied in other switched-capacitor contexts to move quantization or thermal noise out of the signal band. Integrators in a feedback loop cause noise to be high-pass filtered while the signal remains low-pass filtered, improving in-band signal-to-noise ratio at the expense of out-of-band noise that can be subsequently filtered.

Low-Voltage Design Techniques

As supply voltages decrease with advancing process technology, switched-capacitor circuits face headroom challenges. Techniques for low-voltage operation include:

Clock bootstrapping: Maintains switch overdrive regardless of supply voltage
Floating battery switches: Generate gate voltages that track signal levels
Charge pumps: Generate boosted voltages for switch drive
Low-threshold devices: Use native or low-Vt transistors for switches
Inverter-based amplifiers: Replace op-amps with simpler structures that work at lower supplies

Practical Design Considerations

Successful switched-capacitor circuit design requires attention to numerous practical factors beyond the basic circuit topology.

Capacitor Implementation

Integrated capacitors for switched-capacitor circuits are typically implemented as:

Metal-insulator-metal (MIM): Two metal layers separated by a thin dielectric, offering good linearity and matching
Poly-insulator-poly (PIP): Two polysilicon layers separated by oxide, common in analog CMOS processes
Metal-oxide-metal (MOM): Interdigitated metal fingers using interlayer capacitance, available in digital processes without special options
MOS capacitors: Gate-to-channel capacitance, highest density but voltage-dependent

Switch Implementation

MOS switches must be designed for the application requirements:

On-resistance: Must be low enough for adequate settling within the clock phase
Off-leakage: Must be low enough to maintain charge on sampling capacitors
Charge injection: Minimized through sizing, complementary switches, or dummy devices
Clock feedthrough: Reduced by minimizing gate-to-source/drain overlap capacitance
Linearity: Signal-dependent on-resistance causes distortion; bootstrapping improves linearity

Op-Amp Requirements

Operational amplifiers in switched-capacitor circuits must meet specific requirements:

DC gain: Must be high enough that gain error is negligible; typically 60-80 dB for precision applications
Unity-gain bandwidth: Determines settling time; must be several times the clock frequency
Slew rate: Must handle maximum signal transitions without limiting
Output swing: Must accommodate maximum signal amplitudes plus settling overshoot
Noise: Contributes to overall circuit noise; input-referred noise density matters

Clock Generation

Non-overlapping clock generation is critical for proper switched-capacitor operation:

Non-overlap time: Must be sufficient for switches to fully turn off, including worst-case process and temperature variations
Rise and fall times: Faster edges reduce clock feedthrough but may cause substrate noise
Duty cycle: Asymmetric duty cycles may be needed for certain circuits
Jitter: Clock timing uncertainty degrades performance at high frequencies

Applications

Switched-capacitor circuits are fundamental to many analog and mixed-signal applications:

Data Converters

Most modern analog-to-digital and digital-to-analog converters use switched-capacitor techniques:

Pipelined ADCs: Use switched-capacitor residue amplifiers between stages
SAR ADCs: Employ switched-capacitor DACs for successive approximation
Delta-sigma ADCs: Use switched-capacitor integrators in the modulator loop
Current-steering DACs: Often include switched-capacitor sample-and-hold at the output

Integrated Filters

Switched-capacitor filters provide precise frequency response in integrated form:

Anti-aliasing filters: Before ADCs to prevent aliasing of out-of-band signals
Reconstruction filters: After DACs to smooth quantization steps
Channel select filters: In communication receivers to isolate desired channels
Audio processing: Equalization, crossover networks, and signal conditioning

Precision Analog

Applications requiring high accuracy benefit from ratio-metric switched-capacitor precision:

Instrumentation amplifiers: Precise, programmable gain with auto-zero capability
Voltage references: Trimming and temperature compensation circuits
Sensor interfaces: Capacitive sensor readout and bridge amplifiers
Power management: Precision voltage monitoring and regulation control

Conclusion

Switched-capacitor circuits have transformed analog integrated circuit design by enabling precision analog functions to be implemented using only capacitors, switches, and operational amplifiers. The ratio-metric nature of these circuits, where performance depends on capacitor ratios rather than absolute values, provides accuracy and repeatability that would be impossible with traditional continuous-time approaches in integrated form.

From basic integrators and sample-and-hold amplifiers to sophisticated filters and data converter subsystems, switched-capacitor techniques provide the building blocks for modern analog signal processing. Advanced methods including parasitic-insensitive topologies, correlated double sampling, and common-mode feedback enable these circuits to achieve performance approaching fundamental limits.

Understanding switched-capacitor principles is essential for anyone working in analog and mixed-signal integrated circuit design. As process technologies continue to scale and supply voltages decrease, switched-capacitor techniques adapt through innovations in low-voltage operation, time-interleaving, and charge-domain processing, ensuring their continued relevance in the most advanced electronic systems.