Electronics Guide

Thermal Energy and Carrier Statistics

Thermal energy, characterized by the product of Boltzmann's constant and absolute temperature (kT), sets the energy scale for electronic processes in semiconductors. At room temperature (approximately 300 K), kT equals about 26 millielectronvolts, a value that appears throughout semiconductor device equations.

The intrinsic carrier concentration in a semiconductor follows the relationship:

n_i = sqrt(N_c x N_v) x exp(-E_g / (2 x kT))

Where N_c and N_v are the effective densities of states in conduction and valence bands, and E_g is the bandgap energy. This exponential dependence causes intrinsic carrier concentration to approximately double for every 11 degrees Celsius temperature increase in silicon. While this effect is negligible in heavily doped regions, it becomes significant in lightly doped regions and determines the temperature behavior of leakage currents.

The Fermi-Dirac distribution function, which governs carrier occupation of energy states, also depends on temperature. Higher temperatures broaden the distribution, allowing carriers to occupy higher energy states and affecting transport properties throughout the device.

Temperature Coefficient Basics

Temperature coefficients quantify how parameters change with temperature. The most common form is the fractional temperature coefficient (TC), expressed in parts per million per degree Celsius (ppm/C):

TC = (1/X) x (dX/dT) x 10^6 ppm/C

Where X is the parameter value at a reference temperature. A resistor with TC = +100 ppm/C increases by 0.01% for each degree Celsius temperature rise.

For some parameters, particularly semiconductor junction voltages, an absolute temperature coefficient is more appropriate:

TC = dX/dT (units of V/C or mV/C)

The base-emitter voltage of a silicon bipolar transistor, for example, has a temperature coefficient of approximately -2 mV/C, largely independent of the initial voltage value.

Temperature coefficients themselves can vary with temperature, leading to second-order effects that become important over wide temperature ranges. Precision components often specify both first-order (linear) and second-order (parabolic) temperature coefficients.

Junction Voltage Temperature Dependence

The forward voltage of a p-n junction decreases with increasing temperature at a rate of approximately 2 mV/C for silicon. This behavior arises from the temperature dependence of the intrinsic carrier concentration and the thermal voltage kT/q.

The diode equation gives the junction current as:

I = I_s x (exp(qV / (n x kT)) - 1)

Where I_s is the saturation current (strongly temperature dependent) and n is the ideality factor. For a fixed current, the required forward voltage decreases with temperature because the saturation current increases faster than the thermal voltage term.

More precisely, the junction voltage temperature coefficient at constant current is:

dV/dT = (V - V_g0 - alpha x T) / T

Where V_g0 is the extrapolated zero-temperature bandgap voltage (approximately 1.2 V for silicon) and alpha accounts for temperature dependence of the bandgap. At typical forward voltages around 0.6 to 0.7 V, this yields the characteristic -2 mV/C coefficient.

This temperature coefficient has profound implications for analog circuits:

• Transistor biasing: Base-emitter voltages decrease with temperature, changing collector currents in fixed-bias configurations
• Voltage references: Simple diode references drift substantially; compensation techniques are essential
• Current sources: Voltage-programmed current sources exhibit significant temperature variation
• Comparator thresholds: Reference voltages derived from junctions drift with temperature

Bipolar Transistor Parameters

Bipolar transistors exhibit several temperature-dependent parameters beyond the base-emitter voltage:

Current gain (beta): Beta typically increases with temperature at low to moderate collector currents due to reduced base recombination. The temperature coefficient is typically +0.5% to +1%/C. At high currents, high-level injection effects can reverse this trend.

Saturation voltage (V_CE(sat)): Increases slightly with temperature due to increased base resistance and reduced conductivity.

Transition frequency (f_T): Decreases with temperature because carrier transit times increase as mobility decreases.

Collector-base breakdown voltage: Increases with temperature due to increased carrier scattering that reduces impact ionization.

For matched transistor pairs, the difference in base-emitter voltages at unequal collector currents provides a proportional-to-absolute-temperature (PTAT) voltage:

Delta_V_BE = (kT/q) x ln(I_C1 / I_C2)

This PTAT voltage increases linearly with absolute temperature and forms the basis for bandgap voltage references and temperature sensors.

MOSFET Parameters

MOSFETs exhibit temperature behavior dominated by two competing mechanisms: threshold voltage variation and mobility degradation.

Threshold voltage: Decreases with temperature at approximately -2 to -4 mV/C, depending on doping levels and oxide thickness. This decrease arises from the temperature dependence of the Fermi potential and the increased intrinsic carrier concentration.

Carrier mobility: Decreases with temperature approximately as T^(-1.5) to T^(-2) due to increased phonon scattering. This mobility reduction is the dominant effect at high gate overdrive voltages.

The drain current in saturation combines these effects:

I_D = (mu x C_ox x W) / (2 x L) x (V_GS - V_th)^2

At low overdrive voltages, the threshold voltage reduction causes current to increase with temperature. At high overdrive voltages, the mobility reduction dominates, causing current to decrease with temperature. At a specific bias point called the zero-temperature-coefficient (ZTC) point, these effects cancel and the current is temperature independent.

The ZTC point typically occurs at a gate overdrive of 0.2 to 0.4 V, depending on the process. Operating at this point provides first-order temperature stability but requires careful bias design.

Subthreshold operation: In weak inversion, MOSFET current varies exponentially with gate voltage, similar to bipolar transistors. The subthreshold slope has a fundamental limit of kT/q per decade of current, which increases with temperature, degrading off-state performance.

JFET Characteristics

Junction field-effect transistors (JFETs) offer some advantages for temperature-stable design:

Pinch-off voltage: The JFET pinch-off voltage has a negative temperature coefficient, typically -2 to -3 mV/C, similar to a p-n junction.

Zero-bias drain current (I_DSS): Decreases with temperature due to mobility degradation, typically at -0.5% to -1%/C.

Transconductance: Decreases with temperature as mobility decreases.

Like MOSFETs, JFETs exhibit a ZTC point where drain current is temperature independent. This point occurs when the decreasing pinch-off voltage and decreasing mobility produce equal but opposite effects on drain current. Operating at the ZTC bias provides excellent temperature stability for current sources and input stages.

Bandgap Temperature Dependence

The silicon bandgap follows an approximately linear relationship over the practical temperature range:

E_g(T) = E_g0 - alpha x T

Where E_g0 is approximately 1.17 eV and alpha is approximately 0.27 meV/K for silicon. This linear approximation is adequate for many applications but introduces errors at temperature extremes.

More accurate models include quadratic and higher-order terms:

E_g(T) = E_g0 - (alpha x T^2) / (T + beta)

Where alpha and beta are material-specific constants. This Varshni formula captures the behavior more accurately across wide temperature ranges, particularly at low temperatures where the linear model fails.

The bandgap temperature dependence directly affects junction voltages, leakage currents, and the reference voltage in bandgap circuits. Even well-designed bandgap references exhibit some residual temperature dependence due to bandgap curvature effects.

Bandgap Voltage Reference Principle

Bandgap voltage references exploit the complementary temperature coefficients of junction voltage (negative) and thermal voltage (positive) to achieve temperature stability. The basic principle combines a V_BE voltage (negative TC) with a properly scaled PTAT voltage (positive TC):

V_ref = V_BE + K x (kT/q) x ln(N)

Where K is a gain factor and N is the ratio of current densities in two transistors. Choosing K appropriately makes the positive and negative temperature coefficients cancel at the reference temperature.

The resulting reference voltage is close to the silicon bandgap extrapolated to zero temperature, approximately 1.2 to 1.25 V. This is not coincidental but reflects the fundamental physics underlying both the V_BE temperature dependence and the bandgap energy.

First-order bandgap references achieve temperature coefficients of 20 to 100 ppm/C, limited by process variations and the assumption of linear temperature dependence. Higher performance requires curvature compensation.

Curvature Compensation Techniques

The residual temperature dependence of bandgap references arises from the nonlinear (curved) relationship between V_BE and temperature. Several techniques compensate for this curvature:

Squared PTAT compensation: Adding a component proportional to T^2 can cancel the curvature term. This is implemented by squaring a PTAT signal using analog multipliers or translinear circuits.

Piecewise-linear compensation: Different correction slopes are applied in different temperature ranges using temperature-dependent switching circuits.

Resistor ratio temperature compensation: Using resistors with different temperature coefficients to create a correction term that varies nonlinearly with temperature.

Base-emitter voltage summation: Combining V_BE voltages from transistors operating at different current densities to generate higher-order correction terms.

Advanced curvature-compensated references achieve temperature coefficients below 10 ppm/C over military temperature ranges (-55 to +125 C), with the best designs achieving 1 to 3 ppm/C.

Physical Mechanisms

Carrier mobility depends on scattering mechanisms that impede carrier motion. The dominant mechanisms have different temperature dependencies:

Phonon (lattice) scattering: At moderate temperatures, thermal vibrations of the crystal lattice scatter carriers. This scattering increases with temperature, reducing mobility approximately as T^(-1.5) to T^(-2).

Ionized impurity scattering: Carriers scatter from ionized dopant atoms. This mechanism is more important at low temperatures and in heavily doped regions. Impurity scattering actually decreases with increasing temperature because faster-moving carriers spend less time near each impurity.

Surface scattering: In MOSFETs, carriers in the inversion layer scatter from the rough Si-SiO2 interface. Surface scattering is relatively temperature independent.

The overall mobility combines these mechanisms according to Matthiessen's rule:

1/mu_total = 1/mu_phonon + 1/mu_impurity + 1/mu_surface

At room temperature and above, phonon scattering typically dominates, leading to the familiar inverse-temperature dependence of mobility.

Impact on Device Parameters

Mobility reduction with temperature affects multiple device parameters:

Transconductance (g_m): For both bipolar and field-effect transistors, transconductance is proportional to mobility and decreases with temperature. This reduces voltage gain and bandwidth at elevated temperatures.

On-resistance (R_DS(on)): In power MOSFETs, on-resistance is inversely proportional to mobility. On-resistance approximately doubles from 25 C to 125 C, significantly affecting power dissipation calculations.

Transit frequency (f_T): Device speed depends on carrier transit times, which increase as mobility decreases. High-frequency performance degrades at elevated temperatures.

Noise: Some noise mechanisms are related to mobility fluctuations, potentially increasing noise at elevated temperatures.

For analog circuits, the mobility temperature dependence means that gain, bandwidth, and slew rate all decrease at high temperatures. Designs must ensure adequate performance at the maximum operating temperature.

Design Implications

Several design strategies accommodate mobility variations:

• Margin allocation: Specify circuit performance at maximum temperature, accepting overdesign at room temperature
• Bias current scaling: Increase bias current at high temperature to maintain transconductance; PTAT bias currents naturally provide this
• ZTC biasing: Operate MOSFETs and JFETs at the zero-temperature-coefficient point where mobility and threshold variations cancel
• Gain-bandwidth product consideration: Account for reduced bandwidth at elevated temperatures in stability analysis

Physical Origin

MOSFET threshold voltage depends on several temperature-dependent factors:

Fermi potential: The Fermi level position relative to the intrinsic level determines the body effect term in threshold voltage. As temperature increases, the Fermi potential decreases because intrinsic carrier concentration increases.

Work function difference: The work function difference between gate and semiconductor has a weak temperature dependence.

Fixed oxide charge: Oxide charges are relatively temperature independent, but their effect on threshold voltage changes as other terms vary.

The dominant contribution comes from the Fermi potential variation, giving threshold voltage temperature coefficients typically between -1 and -4 mV/C for silicon MOSFETs.

Impact on Circuit Operation

Threshold voltage variation affects circuits in several ways:

Current source variation: In a simple current mirror with fixed gate bias, the threshold voltage shift changes the gate overdrive and thus the output current. A threshold shift of -2 mV/C at a gate overdrive of 200 mV changes current by approximately 1%/C.

Amplifier operating points: Bias voltages designed for a specific threshold voltage may leave insufficient headroom or drive transistors into triode region at temperature extremes.

Logic thresholds: In analog circuits using MOSFETs as switches or in comparators, threshold variations shift switching points.

Subthreshold leakage: Below threshold, current increases exponentially as threshold voltage decreases, significantly increasing off-state currents at elevated temperatures.

Compensation Approaches

Several techniques mitigate threshold voltage temperature dependence:

• Self-biased structures: Circuits where the gate voltage tracks threshold variations maintain consistent overdrive across temperature
• Current-source biasing: Forcing a fixed current through the transistor adjusts V_GS automatically to compensate for threshold shifts
• Matched differential pairs: When both transistors in a differential pair experience the same threshold shift, common-mode rejection eliminates the effect on differential operation
• Body biasing: Adjusting substrate bias with temperature can compensate for threshold variations
• ZTC biasing: Operating at the zero-temperature-coefficient point inherently compensates for threshold variations

Junction Leakage

Reverse-biased p-n junctions conduct a small leakage current that increases exponentially with temperature. The dominant mechanisms include:

Diffusion current: Minority carriers generated within a diffusion length of the junction are swept across by the junction field. This current is proportional to the intrinsic carrier concentration squared, which roughly doubles every 11 C:

I_leakage proportional to n_i^2 proportional to exp(-E_g / kT)

A common approximation is that junction leakage doubles every 10 C, a useful rule of thumb for design.

Generation current: Carriers generated within the depletion region also contribute to leakage. This generation current is proportional to n_i and has a weaker temperature dependence than diffusion current. Generation current dominates in silicon at room temperature and below.

Surface leakage: Current flowing along semiconductor surfaces depends on surface condition and contamination, with variable temperature dependence.

For a typical silicon junction, leakage current might be 1 nA at 25 C, rising to 100 nA at 85 C and 1 microampere at 125 C. This exponential increase has profound implications for circuit design at elevated temperatures.

MOSFET Subthreshold Leakage

When a MOSFET is nominally off (V_GS less than V_th), subthreshold conduction still allows current to flow. This leakage current increases exponentially with temperature due to two effects:

Threshold voltage reduction: Lower threshold at high temperature means larger (V_GS - V_th) in subthreshold, exponentially increasing current.

Subthreshold slope degradation: The subthreshold slope (mV per decade of current change) increases with temperature, meaning current changes more gradually with gate voltage.

Combined, these effects can increase subthreshold leakage by three to four orders of magnitude between room temperature and maximum operating temperature. Modern submicron MOSFETs with low threshold voltages are particularly susceptible.

For analog circuits, subthreshold leakage can discharge sample-and-hold capacitors, create offset currents in high-impedance nodes, and contribute to standby power dissipation.

Gate Leakage

In modern processes with thin gate oxides, quantum-mechanical tunneling allows current to flow through the gate dielectric. Gate leakage increases with temperature, though less dramatically than junction leakage:

Direct tunneling: Dominant in very thin oxides, with weak temperature dependence.

Fowler-Nordheim tunneling: Occurs at higher oxide fields, with stronger temperature dependence due to barrier lowering effects.

Trap-assisted tunneling: Defects in the oxide provide intermediate states for tunneling, with significant temperature dependence.

Gate leakage is particularly problematic in analog circuits because it flows directly into high-impedance input nodes, creating offset voltages and discharging integration capacitors.

Design Countermeasures

Several strategies mitigate leakage effects at elevated temperatures:

• Larger bias currents: Ensure signal currents substantially exceed worst-case leakage currents at maximum temperature
• Shorter hold times: Reduce the time that capacitors must hold charge in sample-and-hold circuits
• Leakage compensation: Use matched dummy structures to cancel leakage currents
• Guarding: Surround sensitive nodes with guard rings at the same potential to intercept leakage currents
• Larger transistors: In some cases, using larger transistor geometries reduces leakage density
• Process selection: Choose processes optimized for low leakage when high-temperature operation is required

Thermal Resistance and Temperature Rise

Self-heating is characterized by thermal resistance, the temperature rise per unit power dissipation:

Delta_T = P_diss x R_th

Where R_th is the thermal resistance from junction to ambient (or another reference point). Thermal resistance depends on die size, packaging, heat sinking, and airflow.

For integrated circuits, different structures on the same die may have different local temperatures due to power distribution and thermal gradients. A high-power output stage may be significantly hotter than a precision reference circuit on the same chip.

Self-heating is particularly significant in:

• Power devices: High currents create substantial power dissipation in output stages and regulators
• Small packages: Limited thermal paths increase thermal resistance
• SOI devices: The buried oxide layer impedes heat flow, increasing local heating
• High-frequency circuits: Dynamic power dissipation adds to static dissipation

Impact on Device Characteristics

Self-heating modifies device behavior in several ways:

Output characteristics: In a MOSFET, self-heating reduces drain current at high V_DS and high I_D because the temperature rise decreases mobility. The output curves may show negative slope regions where increased V_DS reduces I_D through self-heating.

Thermal time constants: Self-heating effects have associated time constants, typically microseconds to milliseconds depending on die thickness and package. Pulsed measurements can separate intrinsic device behavior from thermal effects.

Matching: In matched transistor pairs, unequal power dissipation creates temperature differences that degrade matching. This is particularly problematic in current mirrors and differential pairs.

Stability: The delayed response of temperature to power changes introduces phase shifts in feedback loops that can affect stability.

Modeling Self-Heating

Accurate circuit simulation requires models that include self-heating effects:

Lumped thermal model: A simple thermal resistance and capacitance represent heat flow from junction to ambient. The thermal RC time constant models the dynamics of temperature response.

Multi-node thermal networks: For more accuracy, multiple thermal nodes represent different parts of the device and package, connected by thermal resistances.

Electrothermal simulation: Couples electrical and thermal simulation iteratively, allowing accurate prediction of self-heating effects in complex circuits.

Model parameters are extracted from measurements at different power levels and pulse conditions, or from thermal simulations of the physical structure.

Design Strategies

Several approaches mitigate self-heating problems:

• Thermal symmetry: Place matched devices symmetrically relative to heat sources so both experience the same temperature
• Thermal isolation: Physically separate precision circuits from power-dissipating sections
• Distributed power: Spread power dissipation across larger areas to reduce local heating
• Common-centroid layout: Interleave matched devices to average out thermal gradients
• Dummy devices: Add non-functional devices to balance thermal environments
• Adequate heat sinking: Reduce overall thermal resistance to minimize junction temperature rise

Conditions for Thermal Runaway

Thermal runaway requires that the temperature coefficient of power dissipation exceed the thermal dissipation capability:

dP/dT greater than 1/R_th

If power increases faster with temperature than heat can be removed, temperature rises uncontrollably.

Several situations are particularly susceptible:

Bipolar transistors in common-emitter configuration: With fixed base voltage, collector current increases with temperature (due to decreasing V_BE), increasing power. The positive temperature coefficient of beta compounds the effect.

Parallel power devices: A device that runs slightly hotter draws more current (due to reduced V_BE), heating further while other devices cool and take less current. Current hogging in one device leads to its destruction.

Voltage regulators: If output voltage decreases with temperature while load current increases, power dissipation may increase, particularly with current-limiting engaged.

Prevention Techniques

Several circuit techniques prevent thermal runaway:

Emitter resistors: Adding resistance in the emitter of bipolar transistors provides negative feedback. As current increases, the voltage drop across the emitter resistor reduces the effective base-emitter voltage, limiting further current increase. Even small resistor values (0.1 to 1 ohm) dramatically improve thermal stability.

Current-sense feedback: Active circuits that monitor current and reduce drive as current increases prevent thermal runaway. This is standard practice in power supplies and motor drives.

Thermal sensors: Temperature sensors near power devices can trigger protective action before dangerous temperatures are reached.

Paralleling with ballast resistors: When paralleling power devices, individual source or emitter resistors ensure current sharing by providing negative feedback.

SOA limiting: Safe operating area protection circuits prevent operation in conditions where thermal runaway is possible.

Safe Operating Area

The safe operating area (SOA) defines the voltage-current region where a device can operate without failure. SOA boundaries arise from several mechanisms:

Current limit: Maximum current set by bond wire or metal capability.

Power limit: Hyperbolic boundary set by maximum junction temperature and thermal resistance.

Second breakdown (bipolar): Current focusing in bipolar transistors at high voltage leads to localized heating and failure.

Voltage limit: Breakdown voltage sets the maximum voltage.

The power-limited boundary is most relevant for thermal runaway. For pulsed operation, the effective thermal resistance is lower, and higher power is permissible for short pulses. SOA curves often show different boundaries for different pulse durations.

Designers must ensure that under all operating conditions, including startup, fault, and transient conditions, the device operating point remains within the SOA.

Thermal Design Margins

Reliable designs include thermal margins:

• Maximum ambient temperature: Specify the highest expected ambient temperature and design for this worst case
• Derating: Operate devices below their maximum ratings, typically 50% to 80% of maximum power
• Safety margin: Ensure that even under worst-case conditions, junction temperature remains well below maximum rated temperature
• Aging allowance: Account for increased thermal resistance as thermal interface materials age

PTAT and CTAT Current Sources

Current sources with specific temperature dependence form the foundation of many compensation schemes:

PTAT (Proportional to Absolute Temperature): Generated by forcing a current proportional to the difference in V_BE between transistors at different current densities. The PTAT current increases linearly with temperature:

I_PTAT = (kT/q) x ln(N) / R = (Delta_V_BE) / R

If R has positive temperature coefficient, the temperature dependence is enhanced; if negative, it is reduced.

CTAT (Complementary to Absolute Temperature): Generated from a V_BE-based voltage divided by a resistor. The negative temperature coefficient of V_BE creates a current that decreases with temperature.

Combining PTAT and CTAT currents in appropriate proportions yields currents with arbitrary temperature coefficients, including zero TC for temperature-stable bias.

Temperature-Compensated Bias Circuits

Several bias circuit topologies provide temperature compensation:

V_BE multiplier: By adjusting the multiplication factor with temperature-dependent elements, the output voltage temperature coefficient can be controlled. This is commonly used in power amplifier bias circuits.

Constant-g_m bias: For MOSFETs, forcing drain current to scale with temperature appropriately maintains constant transconductance. This requires a bias current that decreases with temperature to compensate for mobility reduction.

Bandgap-referenced bias: Using a bandgap voltage reference to generate bias voltages provides temperature-stable biasing for precision circuits.

Self-biased structures: Circuits where bias conditions are determined by device ratios rather than absolute voltage values tend to be inherently temperature stable.

Gain Compensation

Temperature-induced gain variations can be compensated by several methods:

Temperature-dependent feedback: Using thermistors or other temperature-sensitive elements in feedback networks adjusts gain to compensate for amplifier gain variations.

AGC (Automatic Gain Control): Closed-loop systems that monitor output amplitude and adjust gain maintain consistent output level regardless of component variations.

Matched device ratios: When gain depends on ratios of similar components, temperature effects tend to cancel if both components are at the same temperature.

Chopper stabilization: By modulating signals to higher frequencies and demodulating after amplification, chopper techniques avoid low-frequency gain errors including temperature drift.

Digital Temperature Compensation

Modern systems increasingly use digital techniques for temperature compensation:

Temperature sensor: An on-chip or system temperature sensor measures the actual operating temperature.

Characterization data: Factory calibration determines how circuit parameters vary with temperature and stores correction data in nonvolatile memory.

Digital correction: A digital processor applies corrections based on measured temperature and stored calibration data.

DAC adjustment: For analog outputs, DACs can trim bias currents, reference voltages, or gain settings in response to temperature.

Digital compensation can correct for complex, nonlinear temperature dependencies that are difficult to address with analog techniques alone. It also enables post-manufacturing calibration that corrects for individual device variations.

Thermal Management Integration

Effective temperature compensation includes thermal management considerations:

• Sensor placement: Temperature sensors should measure the temperature of the circuits they are compensating, not package or ambient temperature
• Thermal equilibrium: Compensation accuracy depends on thermal equilibrium; rapid temperature changes may cause temporary errors
• Power supply stability: Temperature-compensated circuits may be sensitive to supply voltage variations; stable supplies enhance compensation effectiveness
• Matched thermal paths: Components that must match should have matched thermal environments

Resistor Temperature Coefficients

Different resistor types have different temperature characteristics:

Carbon composition: High positive TC, typically +1000 to +2000 ppm/C, with significant voltage coefficient. Generally avoided in precision applications.

Carbon film: Negative TC, typically -200 to -500 ppm/C. Moderate stability and cost.

Metal film: Low TC, typically +/-25 to +/-100 ppm/C. Good stability, widely used in precision circuits.

Wirewound: Low TC, typically +/-20 to +/-50 ppm/C, but can have significant inductance limiting high-frequency use.

Thin-film on ceramic: Very low TC, +/-5 to +/-25 ppm/C, excellent stability for precision applications.

Integrated resistors: Polysilicon resistors have TC around +1000 ppm/C; diffused resistors around +1500 ppm/C. On-chip resistor ratios are more stable than absolute values.

For precision circuits, the ratio between resistors matters more than absolute values. Using resistors from the same manufacturing lot, same type, and same physical location on a PCB improves ratio stability.

Capacitor Temperature Effects

Capacitor temperature behavior varies dramatically by dielectric type:

C0G/NP0 ceramic: Temperature coefficient of +/-30 ppm/C, the best ceramic dielectric for precision and stability.

X7R ceramic: Capacitance varies +/-15% over -55 to +125 C range. Acceptable for bypass and coupling but not precision.

Y5V ceramic: Capacitance varies +22% to -82% over temperature. Only suitable for bulk bypass applications.

Film capacitors: Polypropylene has TC around -200 ppm/C; polystyrene around -120 ppm/C. Both offer good stability.

Aluminum electrolytic: Capacitance increases with temperature; ESR decreases. Large variation over temperature, primarily for power supply filtering.

For oscillators, filters, and other frequency-determining applications, C0G ceramic or film capacitors are essential for temperature stability.

Inductor Considerations

Inductors exhibit temperature effects primarily through their wire resistance and magnetic core properties:

Copper wire resistance: Increases approximately 0.4%/C, increasing losses at elevated temperatures.

Ferrite cores: Permeability varies with temperature, typically decreasing at high temperatures. The Curie temperature represents complete loss of magnetic properties.

Air core: No magnetic material temperature dependence, but higher wire resistance affects Q factor.

Powdered iron cores: Generally more stable with temperature than ferrites but with lower permeability.

Temperature Testing Methods

Several approaches are used for temperature testing:

Temperature chambers: Enclose the entire circuit in a temperature-controlled environment. Provides uniform temperature but requires equilibration time and may not represent actual operating conditions.

Hot plates and cold plates: Heat or cool specific components or circuit sections. Faster response than chambers but creates thermal gradients.

Forced-air heating/cooling: Temperature-controlled air streams provide rapid temperature changes for thermal cycling tests.

Liquid baths: Immersion in temperature-controlled fluids provides rapid, uniform heating or cooling, though not all circuits can be immersed.

Self-heating tests: Operating circuits at elevated power levels to induce self-heating reveals thermal design issues.

Characterization Procedures

Thorough temperature characterization includes:

• Soak testing: Allow circuits to reach thermal equilibrium at each temperature before measurement
• Multiple temperature points: Test at minimum, room, and maximum temperatures at minimum; additional points reveal nonlinear behavior
• Thermal cycling: Repeated temperature excursions reveal intermittent failures and mechanical stress effects
• Operating life tests: Extended operation at elevated temperature accelerates aging mechanisms
• Parameter extraction: Measure key parameters at multiple temperatures to determine temperature coefficients

Correlation to Field Conditions

Laboratory testing must correlate to actual field conditions:

• Ambient temperature range: Understand the actual operating environment, not just specification limits
• Internal temperature rise: Account for self-heating and enclosure effects that raise component temperatures above ambient
• Thermal transients: Field conditions may include rapid temperature changes not captured in steady-state testing
• Solar loading: Outdoor equipment may experience solar heating effects
• Altitude effects: Reduced air pressure at altitude impairs convective cooling