Electronics Guide

Physics of Subthreshold Conduction

When a MOSFET operates in subthreshold, the drain current follows an exponential relationship with gate-source voltage:

I_D = I₀ e^{(V_GS − V_TH) / nV_T} (1 − e^{−V_DS / V_T})

where I₀ is a technology-dependent parameter, V_TH is the threshold voltage, n is the subthreshold slope factor (typically 1.3 to 1.5), and V_T is the thermal voltage kT/q, approximately 25.9 mV at 300 kelvin. The second factor saturates once V_DS exceeds roughly four times V_T, about 100 mV, after which the drain current depends almost entirely on V_GS.

The inverse of that exponential slope is the subthreshold swing, the gate voltage change required to move the drain current by one decade:

S = nV_T ln 10

With n equal to 1 the thermal term alone gives about 60 mV per decade at 300 kelvin, and a real device with n between 1.3 and 1.5 needs roughly 78 to 90 mV per decade. The 60 mV figure is a thermodynamic floor for any conventional MOSFET, not a process limitation, and because it scales with absolute temperature it degrades to about 71 mV per decade at 85 degrees Celsius. That floor governs how much leakage a design must tolerate for a given threshold voltage, and it is the reason tunnel field-effect transistors and negative-capacitance devices, which are not bound by it, remain active subjects of research.

This exponential characteristic means that small changes in gate voltage produce large relative changes in current, providing high transconductance efficiency. The transconductance-to-current ratio g_m/I_D reaches its maximum value in weak inversion:

g_m/I_D = 1 / nV_T

With n near 1.3 this ratio approaches 30 V⁻¹, against roughly 2 to 5 V⁻¹ in strong inversion for the same technology. No bias arrangement in a MOSFET exceeds it, which is why weak inversion is the starting point for any circuit that must buy transconductance with the least possible current.

Advantages of Subthreshold Design

Operating in weak inversion provides several key benefits for ultra-low power circuits:

• Maximum transconductance efficiency: Each unit of bias current produces the maximum possible transconductance, enabling amplification with minimum power
• Reduced supply voltage: Circuits operate from supplies well below 1 V, and the switching energy of any associated digital logic falls in proportion to the square of the supply
• Exponential current control: The exponential I-V characteristic enables precise current ratios for analog computation and biasing
• Low leakage currents: Properly designed subthreshold circuits can achieve operating currents in the picoampere to nanoampere range

Challenges and Trade-offs

Subthreshold operation introduces significant challenges that must be addressed:

• Reduced speed: The transit frequency f_T drops sharply in weak inversion, limiting bandwidth to kilohertz or low megahertz range
• Process sensitivity: Exponential dependence on threshold voltage makes circuits highly sensitive to process variations
• Temperature sensitivity: Both the thermal voltage and threshold voltage vary with temperature, affecting circuit behavior
• Noise performance: While g_m/I_D is maximized, the absolute g_m is low, potentially limiting noise performance in voltage-mode circuits
• Matching requirements: Transistor mismatch causes proportionally larger current variations than in strong inversion

Design Techniques for Subthreshold Circuits

Successful subthreshold design requires specific techniques:

• Large device sizing: Using larger transistors reduces mismatch effects and 1/f noise, though at the cost of increased capacitance
• Current-mode signal processing: Processing signals as currents avoids the noise penalty of low gm in voltage-mode circuits
• Ratio-based design: Exploiting the exponential characteristic for precise current ratios that track with process and temperature
• Self-biased structures: Creating bias networks that automatically maintain desired operating points across variations

Weak Inversion Amplifiers

Amplifiers designed for weak inversion operation take advantage of the high g_m/I_D ratio:

• Source-coupled pairs: Differential pairs in weak inversion provide exponential transfer characteristics useful for certain applications
• Current-mirror OTAs: Operational transconductance amplifiers using current mirrors achieve high gain with nanowatt power consumption
• Folded-cascode architectures: Provide high gain and good output swing even at sub-1 V supplies
• Bulk-driven inputs: Using the body terminal as input allows operation at supply voltages below the threshold voltage

Weak Inversion Filters

Filters can be implemented using weak inversion transconductors with external capacitors:

The unity-gain frequency of a transconductor-C integrator is:

f₀ = g_m / 2πC = I_D / 2πnV_TC

With nanoampere bias currents and picofarad capacitors, cutoff frequencies in the hertz to kilohertz range are achievable, suitable for biomedical and environmental sensing applications. g_m-C filters in weak inversion can achieve total power consumption of tens to hundreds of nanowatts.

Log-Domain Circuits

Log-domain signal processing exploits the exponential transistor characteristic to perform linear operations on logarithmically compressed signals:

• Translinear principle: Products and quotients of currents map to sums and differences of voltages through the exponential relationship
• Log-domain filters: Implement linear transfer functions using only transistors and capacitors, with no resistors required
• Class AB operation: Log-domain circuits naturally provide class AB behavior, handling large signal swings efficiently

These circuits are inherently suited to weak inversion operation where the exponential relationship is most accurate.

Moderate Inversion as a Compromise

The moderate inversion region, between weak and strong inversion, offers a compromise between the benefits of each:

• Improved speed: Higher currents and higher f_T than weak inversion
• Better matching: Less sensitivity to V_TH variation than deep weak inversion
• Good efficiency: A g_m/I_D ratio still well above that of strong inversion

Many ultra-low power designs operate transistors in moderate inversion to balance power consumption against speed and variability requirements.

Threshold Voltage Modulation

The threshold voltage depends on the body-source voltage through the body effect:

V_TH = V_TH0 + γ(√(2φ_F + V_SB) − √(2φ_F))

where V_TH0 is the zero-bias threshold voltage, γ is the body-effect coefficient, and φ_F is the Fermi potential. In mature bulk CMOS γ typically falls between about 0.3 and 0.5 V^1/2, so a few hundred millivolts of body bias shifts the threshold by only a few tens of millivolts. Fully depleted silicon-on-insulator processes place a back gate beneath a thin buried oxide and deliver a considerably larger threshold shift per volt of bias, which has made body biasing a more powerful lever in those technologies than in bulk.

• Forward body bias (FBB): Applying a positive body-source voltage (for NMOS) reduces V_TH, raising current and speed at the cost of increased leakage
• Reverse body bias (RBB): Applying a negative body-source voltage increases V_TH, reducing leakage at the cost of reduced speed

Applications in Ultra-Low Power Design

Body biasing enables several power optimization strategies:

• Leakage reduction during standby: Applying RBB when circuits are inactive dramatically reduces static power consumption
• Performance boosting: FBB can temporarily increase speed when needed, enabling operation at lower nominal supply voltages
• Process compensation: Adjusting body bias compensates for process variation that affects V_TH
• Temperature compensation: Body bias can track temperature to maintain consistent performance
• Bulk-driven circuits: The body terminal serves as a signal input, enabling operation below the threshold voltage

Adaptive Body Biasing

Dynamic adjustment of body bias based on operating conditions optimizes the power-performance trade-off:

• Activity-based adaptation: Apply FBB during active periods and RBB during idle periods
• Closed-loop control: Feedback systems that adjust body bias to maintain a target performance metric
• Look-up table approaches: Pre-characterized body bias values for different operating conditions stored in memory

Implementation requires generation of body bias voltages, typically using charge pumps or voltage regulators, which consume some overhead power that must be accounted for in the overall power budget.

Implementation Considerations

Body biasing requires careful attention to several practical issues:

• Latch-up prevention: Forward body bias can trigger latch-up if the junction forward bias becomes too large; designers typically limit it to roughly 300 to 400 mV, and to less at high temperature, where the parasitic bipolar gain rises
• Triple-well process: Required for independent NMOS body biasing in bulk CMOS; standard twin-well limits flexibility
• Body bias generation: Charge pumps or regulators needed to generate bias voltages; their power consumption impacts effectiveness
• Noise coupling: Body terminal can couple substrate noise to the channel; careful layout and isolation required

Power Gating Fundamentals

Power gating uses a switch, typically a large MOSFET, between the circuit and the power supply:

• Header switch: PMOS transistor between V_DD and the circuit; provides clean ground reference
• Footer switch: NMOS transistor between circuit and ground; provides clean supply but noisy ground
• Virtual rails: The gated supply or ground rail is called virtual V_DD or virtual V_SS

When the switch is off, the circuit is completely isolated from the supply, reducing leakage to the switch off-state current.

Challenges for Analog Circuits

Power gating analog circuits is more complex than gating digital circuits:

• Settling time: Analog circuits require time to reach their correct operating points after power-on
• Charge injection: Switch transitions inject charge that can disturb sensitive analog nodes
• State retention: Some analog circuits must retain state (such as sample-and-hold values) during power-down
• Reference stability: Voltage and current references may require long settling times
• Continuous-time operation: Many analog functions require continuous operation, limiting gating opportunities

Techniques for Analog Power Gating

Several approaches address the unique requirements of analog power gating:

• Partial power gating: Keep critical bias circuits powered while gating power-hungry stages
• Rapid startup biasing: Special bias circuits that establish operating points quickly after power-on
• State retention elements: Capacitive or switched storage to preserve analog state during power-down
• Gradual power-up: Ramped power-on to reduce transients and charge injection
• Duty-cycled operation: Periodically sample signals with brief active periods followed by long power-gated periods

Break-Even Time Analysis

Power gating is only beneficial if the gated period is long enough to offset the energy cost of switching:

The break-even time occurs when:

E_switch + E_startup = P_leakage × t_BE

where E_switch is the energy required to operate the power gate, E_startup is the energy consumed while the circuit returns to its operating point, P_leakage is the leakage power saved, and t_BE is the break-even idle time. Gating an idle period shorter than t_BE costs more energy than it saves.

Typical break-even times range from microseconds to milliseconds, depending on circuit complexity and technology node. Analog blocks with slow-settling references sit at the long end of that range, which is why duty-cycled analog front ends keep their bias networks alive and gate only the signal path.

Voltage-Power Relationships

The power consumed by a circuit depends on supply voltage through several distinct mechanisms. Switching power, short-circuit power, and leakage power are separate terms; folding one into another obscures the trade-off that voltage scaling actually makes.

• Dynamic switching power: P_dyn = αC_LV_DD²f, where C_L is the switched load capacitance, f is the clock frequency, and α is the activity factor, the average number of switching transitions per node per clock cycle. The activity factor is a separate quantity from the clock frequency and does not substitute for it: a node clocked at 100 MHz with α = 0.1 dissipates one-tenth the switching power of a node that toggles on every cycle. Random logic commonly sits near α = 0.1, while a clock network runs at α = 1 by definition
• Short-circuit power: The current that flows through both devices of a CMOS gate while its input traverses the transition region. It is not part of the switching term. It grows with input rise and fall time, and it disappears once V_DD falls below the sum of the NMOS and PMOS threshold voltages, so it is negligible in near-threshold and subthreshold designs. In a gate with well-controlled edge rates it contributes on the order of ten percent of the switching power
• Static (leakage) power: P_leak = I_leakV_DD. The dependence is worse than linear, because drain-induced barrier lowering makes the leakage current itself rise with V_DD
• Analog bias power: Proportional to V_DD for current-biased circuits, whose bias current is set by a reference rather than by the supply

The leakage term is itself a sum of unlike mechanisms, and they do not answer to the same remedies. Subthreshold leakage is drain-to-source conduction in a nominally off device, set by the threshold voltage and the subthreshold swing; reverse body bias, high-threshold devices, stack forcing, and power gating all reduce it. Gate leakage is carrier tunneling through the gate dielectric itself; body bias does nothing to it, and the remedy is physical, namely a thicker or higher-permittivity dielectric, which is why the industry adopted hafnium-based high-k gate stacks. Junction leakage across the reverse-biased source and drain diodes is smaller in most processes but grows with reverse body bias, so aggressive body biasing eventually trades one leakage path for another.

Reducing supply voltage provides the greatest savings in capacitance-dominated circuits, where the quadratic term dominates.

DVS for Analog Circuits

Applying DVS to analog circuits requires consideration of performance impacts:

• Headroom constraints: Cascode stages and stacked transistors require minimum voltage headroom
• Signal swing: Maximum signal amplitude decreases with supply voltage, potentially limiting dynamic range
• Gain sensitivity: Circuit gain may depend on supply voltage, requiring calibration or compensation
• Reference voltage: A conventional bandgap reference requires a minimum supply of roughly 1.0 to 1.2 V

Rail-to-rail designs and bulk-driven topologies extend the minimum operating voltage for analog circuits.

Implementation Approaches

DVS systems require voltage regulation and control logic:

• DC-DC converters: Switching regulators provide efficient voltage conversion; inductor-based or switched-capacitor types
• LDO regulators: Linear regulators offer lower noise but reduced efficiency
• Workload prediction: Algorithms predict required performance level to set voltage proactively
• Closed-loop control: Monitor actual performance and adjust voltage to maintain requirements

The voltage regulator efficiency and the overhead of control logic limit the minimum practical operating level.

Combined Voltage and Frequency Scaling

For sampled-data analog circuits, reducing both voltage and sampling frequency maximizes power savings:

• Energy per operation: The dynamic energy of an operation is E = αC_LV_DD², which carries no frequency term, so lowering the supply saves energy in proportion to the square of the supply whether the circuit runs fast or slow
• The cubic law and its limits: Power is αC_LV_DD²f, quadratic in voltage rather than cubic. The frequently quoted cubic dependence follows only when the frequency is taken proportional to the supply, f ∝ V_DD, and that proportionality is a rough approximation holding over part of the range. Near the threshold voltage the achievable frequency collapses far faster than linearly, and at high supply it flattens, so the cubic form belongs in a first estimate rather than in a specification
• Minimum energy point: A lower supply is not always better. Dynamic energy falls with the square of the supply, but the circuit also runs more slowly, so leakage current is integrated over a longer execution time and leakage energy per operation rises. The two curves cross at a minimum-energy point, which for typical CMOS processes lies in or just above subthreshold, in the region of a few hundred millivolts. Below that point the total energy per operation climbs again
• Near-threshold operation: Many designs deliberately stop above the true minimum-energy point and operate near the threshold voltage, accepting a modest energy penalty in exchange for roughly an order of magnitude more speed and far less sensitivity to process variation

For continuous-time analog circuits only voltage scaling applies, because there is no clock to slow down. Sampled-data approaches recover the full benefit of combined voltage and frequency scaling.

Energy Harvesting Sources

Different ambient energy sources have distinct characteristics:

• Photovoltaic: Solar cells deliver on the order of 10 mW/cm² of electrical output in direct sun, from roughly 100 mW/cm² of incident irradiance, falling to about 10 to 100 µW/cm² under indoor lighting; relatively steady but light-dependent
• Thermoelectric: TEGs generate power from a temperature differential; body-worn generators yield roughly a few to tens of µW/cm² at the small gradients of a few kelvin available on the human body, and the output rises approximately as the square of the temperature difference as the gradient increases
• Piezoelectric: Vibration harvesters provide power from mechanical motion; highly variable, typically 1 to 100 µW
• RF energy: Rectified radio waves; the available power density falls with the square of distance from the transmitter, leaving nanowatts to microwatts at practical ranges

Maximum Power Point Tracking

Energy sources have a maximum power point (MPP) where power extraction is optimized:

• Fractional open-circuit voltage: MPP voltage is approximately a fixed fraction of open-circuit voltage; simple but not optimal
• Perturb and observe: Periodically adjust operating point and measure power; tracks changing conditions
• Incremental conductance: Uses the slope of I-V curve to determine MPP direction

MPPT circuits themselves consume power and must be carefully designed to avoid consuming more than they enable harvesting.

Ultra-Low Power DC-DC Converters

Harvesting interfaces require DC-DC converters that operate efficiently at microwatt input power:

• Switched-capacitor converters: No inductors required; can achieve high efficiency at light loads with careful design
• Inductor-based boost converters: Required for very low input voltages (e.g., single TEG); need careful control of switching losses
• Charge pumps: Simple voltage multiplication; efficiency depends on number of stages and load current

Key design considerations include minimizing quiescent current, reducing switching losses at light loads, and maintaining efficiency across wide input voltage ranges.

Cold Start and Energy Storage

Harvesting systems must address startup without stored energy and manage intermittent availability:

• Cold start circuits: Begin operation with minimal input voltage, often using mechanical switches, charge pumps, or specialized oscillators
• Energy storage: Supercapacitors or rechargeable batteries buffer variations in harvested power
• Power management: Enable load circuits only when sufficient energy is available; implement graceful degradation
• Burst mode operation: Accumulate energy, then operate briefly at higher power levels

Bandgap Reference Fundamentals

Traditional bandgap references combine the negative temperature coefficient of a PN junction voltage with the positive temperature coefficient of thermal voltage difference:

V_REF = V_BE + KΔV_BE

where ΔV_BE is the difference between the base-emitter voltages of two junctions operated at different current densities, a quantity proportional to absolute temperature, and K is chosen so that the two temperature coefficients cancel. The sum settles near the extrapolated bandgap of silicon, about 1.2 V. A standard bandgap reference therefore needs a supply of at least 1.0 to 1.2 V and draws microamperes of current.

Sub-Bandgap References

Sub-bandgap references produce output voltages below 1.2 V, enabling operation from lower supplies:

• Resistive subdivision: Divide down a standard bandgap voltage; simple but adds noise and area
• Native PTAT references: Generate lower reference voltages directly; avoid the 1.2 V bandgap constraint
• Subthreshold MOS references: Use threshold voltage difference of transistors as the temperature-stable reference

Nano-Power Design Techniques

Achieving nanowatt power consumption in references requires:

• Subthreshold operation: Bias all transistors in weak inversion for minimum current
• High-resistance elements: Use MOS resistors in subthreshold or poly resistors for high resistance values
• Self-biased architectures: Eliminate the need for separate bias generation circuits
• Duty-cycled references: Sample the reference periodically rather than maintaining continuous operation
• CMOS-only implementation: Avoid bipolar transistors that require minimum current for proper operation

Performance Trade-offs

Nano-power references sacrifice some performance metrics:

• Temperature coefficient: Typically 20 to 100 ppm per degree Celsius, against 5 to 20 ppm per degree Celsius for a standard reference
• Line regulation: Greater sensitivity to supply voltage variations
• Noise: Higher noise spectral density due to low bias currents
• Settling time: Slower startup due to high impedance nodes

For many ultra-low power applications, these relaxed specifications are acceptable given the power savings achieved.

Operational Transconductance Amplifiers

OTAs are well-suited to micro-power design because their current output naturally interfaces with capacitive loads:

• Simple OTA: Single differential pair with current mirror load; minimum transistor count but limited gain
• Symmetric OTA: Balanced structure with improved CMRR and PSRR
• Folded-cascode OTA: High gain and wide output swing; suitable for sub-1 V supplies
• Current-mirror OTA: Class AB output stage improves large-signal performance

The key metric is gain-bandwidth product per unit power (GBW/P), which reaches maximum values in weak inversion.

Class AB and Adaptive Biasing

Class AB operation improves efficiency by adjusting bias current based on signal demands:

• Minimum quiescent current: Small standby current that increases only when large signals require it
• Slew rate enhancement: Temporary current boost during slewing improves large-signal response without increasing average power
• Dynamic biasing: Bias current tracks signal activity level

A well-designed class AB amplifier improves large-signal power efficiency by roughly ten- to one-hundredfold over a class A design handling the same peak signal.

Noise Optimization at Low Power

Low power consumption and low noise are conflicting requirements that must be balanced:

• Input-referred white noise: In weak inversion the channel current noise is diffusion-limited and shot-like, giving an input-referred power spectral density of approximately 2nkT/g_m. The familiar 4kTγ/g_m form, with γ near 2/3 for a long-channel device in saturation, applies in strong inversion. In either regime, lowering the noise means raising g_m, and g_m is bought with current
• Noise efficiency factor (NEF): Metric comparing an amplifier's input-referred noise to the minimum achievable for a given bias current; lower is better. The related power efficiency factor, PEF = NEF² × V_DD, is often quoted alongside it so that supply voltage is accounted for as well
• g_m/I_D optimization: Operating in weak inversion maximizes transconductance per unit current, improving noise efficiency
• Large input devices: Reduce 1/f noise contribution; requires larger area but not more power

The theoretical NEF lower bound is unity for a single ideal bipolar transistor, the case against which the metric was defined. Practical amplifiers use a differential input pair for common-mode rejection, which raises the floor to √2 for an ideal bipolar pair and to √2/κ for a subthreshold MOS pair, where κ is the gate-coupling factor 1/n. For the usual κ near 0.7 that floor is about 2.02. State-of-the-art micro-power neural and biopotential amplifiers approach it closely, and current-reuse and stacked-amplifier topologies, which spend a single bias current on several transconductors, have reported effective NEF values below unity.

Chopper Stabilization

Chopper stabilization modulates signals to higher frequencies, amplifies them, then demodulates, moving 1/f noise and offset out of the signal band:

• Offset cancellation: Effective offset can be reduced to microvolt levels
• 1/f noise elimination: Low-frequency noise is translated to the chopping frequency
• Power overhead: Chopping clocks and switches add some power consumption
• Ripple filtering: Output contains ripple at the chopping frequency that must be filtered

Chopping is particularly effective in micro-power amplifiers where 1/f noise would otherwise dominate due to low bias currents.

Duty Cycling and Event-Driven Operation

Many applications do not require continuous operation:

• Periodic sampling: Sample signals at the minimum rate required by the application
• Event-driven wakeup: Ultra-low power detector triggers full system operation only when events occur
• Hierarchical processing: Low-power front-end pre-screens data; higher-power processing only when needed

Aggressive duty cycling reduces average power by two to four orders of magnitude, at which point the sleep current and the wake-up energy, rather than the active draw, set the system average.

Near-Sensor Processing

Processing signals close to the sensor reduces the data that must be transmitted:

• Analog feature extraction: Extract relevant features in the analog domain before digitization
• Compression: Reduce data volume before transmission
• Local decision making: Transmit only results rather than raw data

Communication often dominates power consumption in wireless systems; reducing transmitted data provides substantial savings.

Voltage Domain Optimization

Using multiple voltage domains allows each circuit block to operate at its optimal voltage:

• Sensor interface: May require specific voltages for sensor biasing
• Analog processing: Moderate voltage for adequate headroom and dynamic range
• Digital processing: Minimum voltage consistent with performance requirements
• Transmission: Higher voltage for power amplifier efficiency

Level shifters between domains add some overhead but enable significant overall power savings.

Process Selection

Technology choice significantly impacts ultra-low power design:

• Low-leakage processes: High-V_TH device options reduce subthreshold leakage, at the cost of speed
• Specialized nodes: Some foundries offer processes optimized for ultra-low power
• Older technology nodes: Larger feature sizes often have better matching and lower leakage than advanced nodes

Layout Techniques

Physical design affects power consumption and variability:

• Common-centroid layout: Improves matching of critical device pairs
• Guard rings: Isolate sensitive circuits from substrate noise
• Minimized interconnect: Reduces parasitic capacitance
• Dummy devices: Improve uniformity at array edges

Testing and Characterization

Ultra-low power circuits present measurement challenges:

• Picoammeter measurements: Standard equipment may not resolve nanoampere currents accurately
• Probe loading: Test equipment capacitance can exceed circuit capacitance
• Leakage characterization: Must separate device leakage from measurement system leakage
• Statistical testing: Process variation has outsized impact; requires testing many samples