Electronics Guide

Basic Hybrid-Pi Elements

The fundamental hybrid-pi model consists of several key elements:

• Base-emitter resistance (r_π): Represents the dynamic resistance of the forward-biased base-emitter junction. It equals β/g_m or V_T/I_B, where β is the current gain, g_m is the transconductance, V_T is the thermal voltage (approximately 26 mV at room temperature), and I_B is the base DC current.
• Transconductance (g_m): The fundamental gain element, relating collector current to base-emitter voltage. g_m = I_C/V_T, where I_C is the collector DC current. At room temperature this gives approximately 38.5 mS for each milliampere of collector current, since V_T ≈ 26 mV.
• Output resistance (r_o): Accounts for the Early effect, the slight dependence of collector current on collector-emitter voltage. r_o = V_A/I_C, where V_A is the Early voltage (typically 50 to 200 V for silicon transistors).
• Base spreading resistance (r_bb′): The ohmic resistance of the base region between the external base contact and the active base region. Typically 10 to 100 ohms for small-signal transistors.

High-Frequency Hybrid-Pi Model

At higher frequencies, capacitive effects become significant and must be included:

• Base-emitter capacitance (C_π): The diffusion capacitance of the forward-biased junction plus depletion capacitance. Dominates at high frequencies and typically ranges from tens to hundreds of picofarads depending on bias current.
• Collector-base capacitance (C_μ): The depletion capacitance of the reverse-biased collector-base junction. Typically a few picofarads but critically important due to Miller multiplication.
• Collector-substrate capacitance (C_cs): Present in integrated transistors, representing capacitance to the substrate.

The transition frequency (f_T) characterizes high-frequency performance and is related to these capacitances by f_T = g_m/(2π(C_π + C_μ)). At f_T, the short-circuit current gain drops to unity.

Applying the Hybrid-Pi Model

To analyze a transistor amplifier using the hybrid-pi model:

1. Determine the DC operating point (Q-point) by solving the bias circuit with large-signal equations.
2. Calculate small-signal parameters from the Q-point values: g_m = I_C/V_T, r_π = β/g_m, r_o = V_A/I_C.
3. Replace the transistor with its hybrid-pi equivalent circuit.
4. Short-circuit DC voltage sources and open-circuit DC current sources.
5. Analyze the resulting linear circuit using standard techniques (KVL, KCL, node analysis, or mesh analysis).

Field-Effect Transistor Small-Signal Model

A field-effect transistor takes the same hybrid-pi form, with gate, source, and drain in place of base, emitter, and collector. A controlled current source g_mv_gs carries the gain. An output resistance r_o = 1/(λI_D) represents channel-length modulation, as the Early voltage does for the bipolar transistor, and the gate-source and gate-drain capacitances C_gs and C_gd take the places of C_π and C_μ. The model has no counterpart of r_π. An insulated MOSFET gate draws no DC current, and a JFET gate draws only the leakage of a reverse-biased junction, so at low frequencies the input is an open circuit. A MOSFET whose source is not tied to its body needs a second controlled source, g_mbv_bs, for the body effect; most discrete MOSFETs connect the two internally, and the term vanishes. The procedure above carries over unchanged once g_m and r_o are found from the drain current.

In saturation, differentiating the square law I_D = (1/2)μ_nC_ox(W/L)V_ov², where V_ov = V_GS − V_TH is the overdrive voltage, gives the MOSFET transconductance in two equivalent forms:

g_m = 2I_D/V_ov = √(2μ_nC_ox(W/L)I_D)

Here μ_n is the electron mobility, C_ox the gate-oxide capacitance per unit area, and W/L the ratio of channel width to length. A JFET obeys a square law of the same shape with V_GS − V_P in place of the overdrive, so its transconductance is 2I_D/(V_GS − V_P). A MOSFET biased at 1 mA with an overdrive of 0.2 V has g_m = 10 mS. Doubling its current at the same geometry raises g_m only by a factor of √2, to 14.1 mS, because the overdrive rises too. Both forms rest on the long-channel, strong-inversion square law. Near threshold the device enters weak inversion, where drain current is exponential in gate voltage and g_m levels off at I_D/(nV_T) instead of rising without limit as V_ov shrinks. In short-channel devices at large overdrive, velocity saturation and mobility degradation hold g_m below the square-law value.

With a drain resistor R_D, the common-source stage has a gain of the same form as the common-emitter stage:

A_v = −g_m(R_D ∥ r_o)

The 10 mS device with R_D = 4.7 kilohms and r_o = 50 kilohms, from λ = 0.02 per volt, gives a gain of about −43. C_gd bridges that gain exactly as C_μ does in the common-emitter stage, so the Miller effect described below applies unchanged, and the input capacitance is C_gs + C_gd(1 + g_m(R_D ∥ r_o)). Taking C_gs = 10 pF and C_gd = 2 pF, the 2 pF appears as 88 pF and the total is 98 pF. No r_π shunts the gate node, so the whole source resistance charges that capacitance. From a 100 kilohm source, with gate bias resistors large enough to neglect, the input pole falls near 16 kHz, although the same capacitances give the device an f_T of about 130 MHz. FETs are chosen precisely for such high-impedance sources, which is where the Miller effect costs them most, and a cascode is the usual remedy.

At equal bias current, a bipolar transistor has the higher transconductance. Its collector current is exponential in V_BE, so g_m/I_C = 1/V_T, about 38.5 mS per milliampere whatever the size of the device. The square law gives a FET g_m/I_D = 2/V_ov, only 10 mS per milliampere at 0.2 V of overdrive, so the bipolar transistor leads by the factor V_ov/(2V_T), almost four here, and a bipolar stage at the same current into the same load resistance has almost four times the gain. Lowering the overdrive narrows the gap but cannot close it. The square law would reach the bipolar figure only at V_ov = 2V_T, about 52 mV, where it already predicts more than weak inversion allows, and the weak-inversion ceiling of 1/(nV_T) still falls short by the slope factor n, typically 1.2 to 1.5. The shortfall is physical. The gate controls the surface potential of the channel only through the capacitive divider formed by the gate oxide and the depletion layer beneath it, so only the fraction 1/n of a change in gate voltage reaches the barrier that carriers must cross, whereas V_BE acts on the emitter junction directly. What the FET offers in exchange is its open-circuit gate. The Common-Source and Source Follower Circuits and FET Biasing Methods sections of Single-Stage Amplifier Configurations give the full treatment of FET stages and their bias.

H-Parameter Definitions

The h-parameters relate input and output voltages and currents in the following matrix form:

v₁ = h₁₁i₁ + h₁₂v₂

i₂ = h₂₁i₁ + h₂₂v₂

For a transistor in common-emitter configuration:

• h_ie (h_11e): Input impedance with output shorted. h_ie ≈ r_bb′ + r_π, so it falls with collector current and rises with β. At a collector current of 1 milliampere it is roughly 2.6 kilohms for β = 100 and 7.9 kilohms for β = 300.
• h_re (h_12e): Reverse voltage ratio with input open. Very small (10⁻⁴ range), often neglected in simplified analysis.
• h_fe (h_21e): Forward current gain with output shorted. This is the familiar β, typically 50 to 500 for small-signal transistors.
• h_oe (h_22e): Output admittance with input open. Approximately 1/r_o, which equals I_C/V_A and therefore rises in proportion to collector current. At 1 milliampere with an Early voltage of 100 V it is about 10 microsiemens.

Configuration Conversion

H-parameters change with transistor configuration. Conversion formulas relate common-emitter (CE), common-base (CB), and common-collector (CC) parameters:

For common-base from common-emitter, neglecting second-order terms:

• h_ib = h_ie/(1 + h_fe)
• h_rb = h_ieh_oe/(1 + h_fe) − h_re
• h_fb = −h_fe/(1 + h_fe)
• h_ob = h_oe/(1 + h_fe)

These conversions enable analysis of any configuration using parameters typically specified for the common-emitter case.

Simplified H-Parameter Analysis

For many practical applications, the approximate h-parameter model provides adequate accuracy:

• Set h_re = 0 (negligible reverse feedback)
• Set h_oe = 0 (infinite output resistance), which is safe while h_oeR_L stays below about 0.1, that is, while the load is small beside r_o

With these simplifications, a common-emitter stage with total collector load R_L, the collector resistor R_C in parallel with any external load, has:

• Voltage gain: A_v = −h_feR_L/h_ie, the negative sign denoting the phase inversion
• Current gain: A_i = h_fe
• Input impedance: Z_i = h_ie
• Output impedance: Z_o ≈ R_C, because the simplified model treats the resistance looking into the collector as infinite

That infinity belongs to the approximation, not to the transistor. Setting h_oe = 0 discards r_o = 1/h_oe, about 100 kilohms at 1 mA with an Early voltage of 100 V, and emitter degeneration raises the resistance looking into the collector further, toward a ceiling near (1 + β)r_o, as the output impedance analysis below shows. Z_o ≈ R_C therefore holds while R_C is small beside that resistance; otherwise Z_o is R_C in parallel with it.

Y-Parameter Model

Y-parameters express the relationship between port currents and voltages in admittance form:

i₁ = y₁₁v₁ + y₁₂v₂

i₂ = y₂₁v₁ + y₂₂v₂

Key y-parameters for RF transistors:

• y_ie: Input admittance (output shorted)
• y_re: Reverse transfer admittance (input shorted)
• y_fe: Forward transfer admittance (output shorted)
• y_oe: Output admittance (input shorted)

Y-parameters are frequency-dependent complex quantities, capturing both magnitude and phase information essential for high-frequency analysis.

S-Parameter Fundamentals

Scattering parameters relate incident and reflected waves at each port, making them ideal for RF and microwave measurements where wave behavior dominates:

b₁ = S₁₁a₁ + S₁₂a₂

b₂ = S₂₁a₁ + S₂₂a₂

Where a represents incident waves and b represents reflected waves. The s-parameters have physical interpretations:

• S₁₁: Input reflection coefficient (output terminated in Z₀)
• S₂₁: Forward transmission coefficient (forward gain)
• S₁₂: Reverse transmission coefficient (reverse isolation)
• S₂₂: Output reflection coefficient (input terminated in Z₀)

S-Parameter Advantages

S-parameters offer several advantages for high-frequency work:

• Easy measurement: Can be measured directly with a vector network analyzer without requiring short or open circuits at high frequencies (which are difficult to achieve)
• Cascading simplicity: S-parameter matrices can be converted to T-parameters (transfer parameters) for easy cascading of stages
• Stability analysis: Stability circles and stability factors are derived directly from s-parameters
• Matching network design: Smith chart techniques use reflection coefficients directly

Parameter Conversion

Conversion between parameter sets enables use of the most convenient form for each analysis task. For example, converting s-parameters to y-parameters (normalized to the characteristic admittance Y₀ = 1/Z₀):

y₁₁ = Y₀[(1 − S₁₁)(1 + S₂₂) + S₁₂S₂₁]/[(1 + S₁₁)(1 + S₂₂) − S₁₂S₂₁]

Similar formulas exist for all parameter conversions. CAD tools typically handle these conversions automatically.

Miller Effect Theory

When a capacitance C connects between the input and output of an inverting amplifier whose voltage gain is −A_v, with A_v the positive magnitude of that gain, the effective input capacitance is magnified:

C_in = C(1 + A_v)

For a common-emitter stage, the collector-base capacitance C_μ experiences Miller multiplication. If the stage has a voltage gain of 100, a 2 pF C_μ appears as 202 pF at the input. This dramatically increases the time constant at the input node and reduces bandwidth.

The output capacitance is also affected but less severely:

C_out = C(1 + 1/A_v)

For high-gain stages this approaches C, so the output effect is typically secondary.

Bandwidth Limitation

The Miller effect creates a dominant pole in the amplifier's frequency response. The input time constant is:

τ_in = R_source(C_π + C_μ(1 + g_mR_L))

Here R_source is the whole resistance at the base node, not the generator resistance alone: the signal source in parallel with the bias network, plus r_bb′, with that combination in parallel with r_π. R_L is likewise the total resistance at the collector, the collector resistor in parallel with r_o and the external load. This results in a −3 dB frequency of:

f_{3 dB} = 1/(2πτ_in)

As an example, take a stage biased at 1 mA, so that g_m = 38.5 mS and r_π = 2.6 kilohms at β = 100, with R_source = 1 kilohm, C_π = 50 pF, C_μ = 3 pF, and a voltage gain of 100. The Miller-multiplied input capacitance is approximately 350 pF, giving f_{3 dB} around 450 kHz, although the same capacitances give the transistor an f_T of about 115 MHz. The 1 kilohm is the base-node resistance with r_π already included. Neglecting r_bb′ and the bias network, a 1 kilohm generator in parallel with the 2.6 kilohm r_π leaves only 722 ohms at the base node, which shortens τ_in to 255 ns and raises the estimate to 624 kHz. Substituting the generator resistance alone would understate that bandwidth by more than a quarter.

That estimate keeps only the input time constant. The open-circuit time-constant method described below also charges C_μ through the load: the assumed gain of 100 implies R_L ≈ 2.6 kilohms, so τ_π = 50 ns and τ_μ = C_μ[R_source(1 + g_mR_L) + R_L] = 311 ns. Their sum of 361 ns gives 441 kHz. With the 722 ohm base node of the 1 kilohm generator, the same sum is 36 ns plus 227 ns, or 263 ns, for 606 kHz. In both cases the two estimates agree within a few percent, and the more complete one is the lower.

Cascode Configuration

The cascode configuration is the primary technique for reducing the Miller effect. By stacking a common-base stage above a common-emitter stage:

• The common-emitter stage sees a low impedance at its collector (approximately 1/g_m of the common-base transistor)
• The voltage gain of the common-emitter stage is approximately −1
• Miller multiplication of C_μ is reduced to a factor of approximately 2, rather than (1 + A_v)
• The common-base stage provides the voltage gain with inherently low input capacitance

The result is bandwidth improvement by a factor of 5 to 10 or more compared to a simple common-emitter stage with the same gain.

Neutralization Techniques

At RF frequencies, neutralization cancels the effect of C_μ over a narrow band by providing a compensating feedback path. The cancellation is exact only where the neutralizing network balances C_μ, so across a wide band the technique reduces the feedback rather than removing it:

• Capacitive neutralization: A capacitor from output to input through an inverting element (transformer or additional stage) provides feedback of opposite phase to cancel the C_μ feedback.
• Inductive neutralization: Uses mutual inductance to provide canceling feedback.

Neutralization requires careful adjustment and can cause instability if improperly implemented. It is most common in tuned RF amplifiers where the narrow bandwidth makes adjustment practical.

Compensation Techniques

Other Miller compensation approaches include:

• Miller compensation (in op-amps): Intentionally adding capacitance from output to input of a high-gain stage to create a dominant pole for stability, exploiting rather than fighting the Miller effect. The capacitor splits the poles: Miller multiplication drives the first pole down to form the dominant pole, while the shunt feedback it introduces drives the second pole up, widening the spacing between them and improving phase margin.
• Source/emitter degeneration: Adding resistance reduces voltage gain and hence Miller multiplication, trading gain for bandwidth.
• Feedback capacitance reduction: Using transistors with lower C_μ or operating at lower collector voltage (reducing the depletion width).

Low-Frequency Response

Low-frequency roll-off results from coupling and bypass capacitors. Each capacitor introduces a high-pass response:

• Input coupling capacitor (C_in): Forms a high-pass filter with the source and input resistance. f_L = 1/(2πC_in(R_s + R_in)).
• Output coupling capacitor (C_out): Forms a high-pass filter with the output resistance and load. f_L = 1/(2πC_out(R_out + R_L)).
• Emitter bypass capacitor (C_e): Must effectively short the emitter degeneration at signal frequencies. The resistance it sees is R_E in parallel with (r_e + R_B/β), where r_e = 1/g_m and R_B is the Thevenin resistance looking back from the base, the source resistance in parallel with the bias divider, giving f_L ≈ 1/(2πC_e[R_E ∥ (r_e + R_B/β)]). Because r_e is only a few tens of ohms, this pole is often the highest of the three.

A worked bias point shows the spread. Take I_C = 1 mA, which gives g_m = 38.5 mS, r_e = 26 ohms, r_π = 2.6 kilohms at β = 100, and r_o = 100 kilohms at an Early voltage of 100 V. The stage has a 47 kilohm and 10 kilohm divider, R_s = 1 kilohm, R_C = 4.7 kilohms, R_L = 10 kilohms, R_E = 1 kilohm, C_in = C_out = 1 µF and C_e = 10 µF. The input capacitor sees R_s plus R₁ ∥ R₂ ∥ r_π, which is 3.0 kilohms, for 54 Hz. The output capacitor sees r_o ∥ R_C plus R_L, which is 14.5 kilohms, for 11 Hz. The bypass capacitor sees only R_E ∥ (r_e + R_B/β), which is 34 ohms, for 472 Hz. The bypass pole sits roughly an order of magnitude above the other two, and holding it to 20 Hz with this emitter network would take about 240 µF.

The overall low-frequency cutoff is typically dominated by the highest individual cutoff frequency. For well-designed amplifiers, these should be staggered to avoid excessive phase shift accumulation.

High-Frequency Response

High-frequency roll-off results from transistor and parasitic capacitances:

• Input pole: Formed by the resistance at the base node (the source resistance in parallel with r_π) and the total input capacitance (C_π plus Miller-multiplied C_μ).
• Output pole: Formed by the output resistance and load capacitance plus C_μ.
• Additional poles: May arise from package parasitics, PCB traces, and bypass capacitor inductance.

The dominant high-frequency pole typically determines the −3 dB bandwidth. Additional poles cause steeper roll-off beyond the bandwidth and contribute excess phase shift.

Open-Circuit Time Constants

The open-circuit time constant (OCTC) method, also called the zero-value time-constant method, provides a systematic way to estimate bandwidth without detailed pole analysis:

1. Identify each capacitor in the circuit.
2. For each capacitor, calculate the resistance seen by that capacitor when all other capacitors are open-circuited.
3. Calculate the time constant τ_i = R_iC_i for each capacitor.
4. Sum all time constants: τ_total = sum of all τ_i.
5. Estimate bandwidth as f_H ≈ 1/(2πτ_total).

This method slightly underestimates bandwidth, yielding a conservative lower bound, because the sum of the open-circuit time constants equals the sum of the reciprocal pole frequencies and so charges the amplifier for poles beyond the dominant one. It provides good engineering accuracy with minimal computation.

A companion short-circuit time-constant method handles the low-frequency end. There each coupling and bypass capacitor is taken in turn with all the others shorted rather than opened, and the lower cutoff follows from the sum of the reciprocal time constants, f_L ≈ (1/2π) times the sum of 1/(R_iC_i). That sum errs in the opposite direction, overestimating f_L.

Bode Plot Analysis

Bode plots graphically represent frequency response with separate magnitude (in dB) and phase plots versus log frequency:

• Poles: Each real pole contributes −20 dB/decade slope above its frequency and −45 degrees phase at the pole frequency.
• Zeros: Each real zero contributes +20 dB/decade slope above its frequency and +45 degrees phase at the zero frequency.
• Complex poles/zeros: Contribute peaking or notching near the natural frequency, with the degree of peaking determined by the Q factor.

The asymptotic approximation method allows rapid sketching of Bode plots by drawing straight-line segments that change slope at pole and zero frequencies.

Input Impedance Analysis

Input impedance depends on configuration and feedback:

For a common-emitter stage driving a resistive load R_L:

Z_in = r_bb′ + r_π ∥ 1/(jω(C_π + C_μ(1 + g_mR_L)))

The Miller term is what makes common-emitter input impedance collapse as frequency rises, and it is the same term that sets the input pole in the bandwidth calculation above.

At low frequencies where capacitive effects are negligible:

Z_in ≈ r_bb′ + r_π = r_bb′ + β/g_m

With emitter degeneration resistor R_E:

Z_in = r_bb′ + r_π + (1 + β)R_E

The (1 + β) multiplication of R_E demonstrates impedance transformation by the transistor, significantly increasing input impedance.

Output Impedance Analysis

Output impedance is found by applying a test voltage or current at the output with the input appropriately terminated:

For a common-emitter stage:

Z_out = r_o ∥ R_C

With emitter degeneration:

Z_out ≈ r_o(1 + g_mR_E) ∥ R_C

Emitter degeneration significantly increases the resistance looking into the collector, approaching r_o(1 + g_mR_E), which can be several megohms. The boost does not grow without limit, because the degeneration factor is more exactly 1 + g_m(R_E ∥ r_π) and so saturates near 1 + β. With r_o = 100 kilohms, β = 100 and R_E = 1 kilohm the factor is 28.8 rather than the 39.5 the simpler form predicts, giving 2.9 megohms rather than 4.0, and no value of R_E pushes it past about (1 + β)r_o. This is the principle behind cascode current sources and other high-impedance current sources.

Configuration Comparison

The three basic configurations offer different impedance characteristics:

• Common-emitter: Moderate input impedance, r_π = β/g_m in parallel with the bias network; moderate output impedance, r_o ∥ R_C, which R_C usually sets because degeneration raises only the r_o term; both voltage gain and current gain, with inversion
• Common-base: Low input impedance, approximately 1/g_m in parallel with the emitter resistor. More exactly it is (r_o + R_L)/(1 + g_mr_o), which rises above 1/g_m as the collector load grows. The resistance looking into the collector is very high, so R_C again sets the stage output impedance. Current gain is just below unity, and voltage gain is comparable to that of the common-emitter stage
• Common-collector (emitter follower): Very high input impedance, r_π + (1 + β)R_L, which approaches βR_L once βR_L exceeds r_π; low output impedance, 1/g_m + R_B/(1 + β) in parallel with R_E, where R_B is again the source resistance in parallel with the bias divider, so a low-impedance source is a prerequisite for a low output impedance; voltage gain slightly below unity, with substantial current gain

Frequency-Dependent Impedance

Impedances become complex at high frequencies:

• Input impedance decreases as C_π and Miller-multiplied C_μ shunt the resistive components.
• Output impedance typically decreases due to collector-substrate and load capacitances.
• Phase shifts accompany the magnitude changes, potentially affecting stability.

For wideband amplifiers, impedance must be characterized across the entire operating frequency range, often using network analyzer measurements.

Stability Conditions

An amplifier is unconditionally stable if it remains stable for any passive load and source impedance (all impedances with positive real parts). Conditional stability means stability only for a restricted range of terminations.

Instability arises when feedback (intentional or parasitic) provides sufficient loop gain with appropriate phase to sustain oscillation. The Barkhausen criterion states that oscillation occurs when the loop gain magnitude equals unity and the phase shift equals 360 degrees (or equivalently, 0 degrees).

K-Factor (Rollett Stability Factor)

For two-port networks characterized by s-parameters, the Rollett stability factor K determines unconditional stability:

K = (1 − |S₁₁|² − |S₂₂|² + |Δ|²)/(2|S₁₂S₂₁|)

Where Δ = S₁₁S₂₂ − S₁₂S₂₁

Unconditional stability requires both K greater than 1 and |Δ| less than 1. K greater than 1 on its own is not sufficient, and quoting it alone is a common error, because the auxiliary condition is what excludes the networks that are potentially unstable despite a large K.

The K-factor is frequency-dependent and must be evaluated across the operating band. Many transistors are conditionally stable at some frequencies, requiring careful matching network design.

Stability Circles

When K is less than 1, stability circles on the Smith chart indicate the boundaries between stable and unstable regions:

• Source stability circle: Shows source reflection coefficients that cause instability.
• Load stability circle: Shows load reflection coefficients that cause instability.

Circle parameters (center and radius) are computed from the s-parameters. The stable region may be inside or outside the circle, determined by checking a known stable point (typically the origin, representing Z₀).

Design proceeds by ensuring matching networks place the source and load impedances within stable regions at all frequencies.

Mu-Factor

The mu-factor provides a single stability criterion without requiring the auxiliary condition |Δ| less than 1:

μ = (1 − |S₁₁|²)/(|S₂₂ − ΔS₁₁^*| + |S₁₂S₂₁|)

Here S₁₁^* denotes the complex conjugate of S₁₁. Unconditional stability requires μ greater than 1. The criterion is geometric: μ is the distance from the center of the load-plane Smith chart to the nearest point of the load stability circle, so μ greater than 1 places every passive load inside the stable region. That also makes μ a stability margin, since larger values indicate greater immunity to parameter variation.

Low-Frequency Stability

Feedback amplifiers require phase margin and gain margin analysis:

• Phase margin: The phase difference from −180 degrees when the loop gain magnitude equals 0 dB. Typically 45 to 60 degrees is adequate, with 60 degrees preferred; less than 30 degrees indicates marginal stability with noticeable ringing.
• Gain margin: The number of decibels by which the loop gain lies below 0 dB when the phase reaches −180 degrees. At least 6 dB is required, with 10 dB or more preferred for robust designs that tolerate component and temperature variation.

Stability is analyzed using Bode plots of the loop gain transfer function or Nyquist plots that directly show encirclement of the critical point.

Gain-Bandwidth Product Fundamentals

For a single-pole system, the gain-bandwidth product is constant:

GBW = A_mid f_{3 dB}

Where A_mid is the midband gain and f_{3 dB} is the −3 dB bandwidth. Which gain is meant matters. For a common-emitter stage driven from a current source, so that r_π alone loads the base node, the current gain β and the input pole give:

GBW ≈ g_m/(2π(C_π + C_μ(1 + g_mR_L)))

With R_L = 0 this reduces to f_T, which is why the transistor's f_T represents the maximum achievable current gain-bandwidth product, approached only when the Miller effect is eliminated and loading is optimized. Driven instead from a voltage source of resistance R_s, with r_bb′ and the bias network neglected, the voltage gain-bandwidth product is g_mR_L/(2πR_s(C_π + C_μ(1 + g_mR_L))), which approaches 1/(2πR_sC_μ) as the gain rises. In the 1 mA example above, a 1 kilohm generator gives a voltage gain of 72 and a bandwidth of 624 kHz, a product of 45 MHz against a limit of 53 MHz. At high gain the product is set by the source resistance and C_μ, not by f_T.

Multi-Stage Optimization

Cascading stages allows total gain to exceed what a single stage can provide, but bandwidth shrinks with each additional pole. For n identical stages each with bandwidth BW:

BW_total = BW √(2^1/n − 1)

This bandwidth shrinkage factor is 0.64 for two stages, 0.51 for three stages, and so on. Optimization involves:

• Distributing gain to minimize noise and maximize headroom
• Staggering pole frequencies (stagger-tuned design) to extend bandwidth
• Using feedback around multiple stages to trade excess gain for bandwidth recovery

Feedback for Bandwidth Extension

Negative feedback can exchange gain for bandwidth while maintaining the gain-bandwidth product:

If an amplifier with open-loop gain A and bandwidth BW has feedback applied to reduce gain by the factor (1 + Aβ), where β is the feedback factor (not the transistor current gain):

Closed-loop gain = A/(1 + Aβ)

Closed-loop bandwidth = BW(1 + Aβ)

The product of gain and bandwidth therefore remains unchanged. However, feedback also reduces distortion and sensitivity to component variations by the same factor, providing additional benefits.

Current-Mode and Transimpedance Techniques

Current-mode amplifiers can achieve higher bandwidths than voltage-mode designs by avoiding voltage swings that must charge parasitic capacitances:

• Current-feedback amplifiers: Achieve nearly constant bandwidth independent of gain by decoupling the feedback network from the gain-determining mechanism.
• Transimpedance amplifiers: Convert current to voltage with bandwidth determined by the feedback network rather than input capacitance.
• Current conveyors: Building blocks for current-mode signal processing with inherent high-frequency capability.

Device Selection for High GBW

Transistor selection significantly impacts achievable gain-bandwidth:

• f_T rating: Higher f_T transistors offer greater GBW potential. Modern RF transistors achieve f_T of tens to hundreds of GHz.
• Capacitance ratios: Low C_μ relative to C_π reduces Miller effect severity.
• Current handling: Higher operating current increases g_m and potentially bandwidth but increases power and may reduce r_o.
• Technology choice: SiGe HBTs, GaAs, and InP technologies offer higher f_T than silicon BJTs for demanding applications.

Computer-Aided Analysis

Modern amplifier design relies heavily on SPICE simulation:

• AC analysis: Computes small-signal frequency response using linearized models at the DC operating point.
• Noise analysis: Calculates input-referred noise and noise figure.
• Pole-zero analysis: Identifies the locations of transfer function poles and zeros.
• Stability analysis: Computes loop gain for feedback amplifiers.

Simulation should complement, not replace, hand analysis. Understanding the circuit analytically enables proper interpretation of simulation results and efficient optimization.

Measurement Validation

Key measurements to validate small-signal analysis:

• Frequency response: Swept-frequency measurement with a network analyzer or a spectrum analyzer with tracking generator.
• Input/output impedance: Network analyzer S-parameter measurement or impedance bridge.
• Gain accuracy: Precise measurement at specific frequencies using calibrated attenuators.
• Phase response: Critical for feedback amplifier stability assessment.

Common Analysis Pitfalls

Avoid these frequent mistakes:

• Neglecting base resistance: r_bb′ significantly affects high-frequency noise and bandwidth.
• Ignoring output resistance: r_o matters when loads are comparable to its value.
• Oversimplified models: At high frequencies, simple models may miss important effects.
• Parasitic elements: Package and PCB parasitics often dominate at high frequencies.
• Temperature effects: Parameters vary significantly with temperature, affecting all results.