Compact Modeling and Device Physics

A compact model is the mathematical bridge between the physics of a semiconductor device and the circuit simulator that must evaluate it. It reduces the behavior of a transistor, diode, or passive element to a closed-form set of equations, parameterized by a manageable number of coefficients, that returns terminal currents and charges as functions of the applied voltages, the device geometry, and the temperature. Every transistor-level simulation a designer runs is, at its core, the simulator solving Kirchhoff's laws around a network of these models, calling each one millions of times as it steps through bias points and time.

The word "compact" carries the central design tension. A device could be described by solving the underlying transport equations numerically on a mesh, as technology computer-aided design (TCAD) does, but such a calculation is far too slow to embed inside a circuit simulation that must converge thousands of operating points. A compact model instead captures the same physics in analytic form: accurate enough to predict measured silicon, smooth enough to converge, and cheap enough to evaluate at scale. The art of compact modeling lies in honoring all three constraints at once, and the discipline that supports it spans device physics, numerical analysis, statistics, and software engineering.

This article develops the subject from the physics outward. It begins with the role a compact model plays and the criteria a good one satisfies, then surveys the dominant MOSFET model families and the bipolar models that preceded them. It examines the physical effects that distinguish a modern model from a textbook square-law equation, the charge and capacitance description that governs dynamic behavior, and the parameter-extraction process that fits a model to a fabrication process. It closes with the Verilog-A language used to author behavioral and research models, the validation practices that establish trust, and a summary of the principles that recur throughout.

The Role of a Compact Model

A circuit simulator does not know what a transistor is. It knows only that certain network elements impose a relationship between the voltages at their terminals and the currents that flow through them. A compact model supplies that relationship. For each device instance the simulator passes in the current terminal voltages, and the model returns the currents, the stored charges, and the partial derivatives of those quantities with respect to every terminal voltage. The derivatives form the entries of the Jacobian matrix that the Newton-Raphson solver uses to find the operating point, which is why a model that fails to provide accurate, continuous derivatives will impede or prevent convergence.

A useful compact model satisfies several criteria simultaneously. It must be accurate, reproducing measured current-voltage and capacitance-voltage data across the full range of bias, geometry, and temperature the process will encounter. It must be continuous and differentiable to high order, because discontinuities in the current or its slopes appear to the solver as infinite derivatives and to a distortion analysis as spurious harmonics. It must be physical, so that its parameters correspond to measurable quantities and behave sensibly when extrapolated beyond the fitting range. It must be scalable, predicting the behavior of devices of different widths and lengths from a single parameter set rather than requiring a fresh fit for every geometry. And it must be efficient, since model evaluation dominates the runtime of large simulations.

These goals conflict. Greater accuracy tempts the modeler to add parameters and physical effects, which slows evaluation and complicates extraction. Greater physical fidelity can introduce equations that are expensive or numerically delicate. The history of compact modeling is largely a history of resolving these tensions: replacing piecewise expressions that switched between operating regions with single continuous equations valid across all of them, and grounding empirical fitting parameters in device physics so that they extrapolate rather than merely interpolate.

MOSFET Model Families

The metal-oxide-semiconductor field-effect transistor is the workhorse of modern integrated circuits, and its compact models have evolved through several generations as feature sizes shrank from micrometers to nanometers. The defining challenge has been the transition from weak inversion through moderate inversion to strong inversion: early models described these regions with separate equations and stitched them together, producing kinks that corrupted analog design, while modern models describe the channel charge with a single continuous expression.

The BSIM Family

The Berkeley Short-channel IGFET Model (BSIM) family, developed at the University of California, Berkeley, became the industry standard for digital and mixed-signal CMOS. BSIM3 and especially BSIM4 dominated bulk CMOS modeling for two decades, offering threshold-voltage-based formulations with extensive parameters for short-channel effects, gate leakage, and parasitics. As planar bulk transistors gave way to new architectures, the family extended to BSIM-CMG for multi-gate FinFET and gate-all-around devices and BSIM-IMG for independent multi-gate and fully depleted silicon-on-insulator transistors. The Compact Model Coalition, operating under the Si2 standards organization, maintains these models as public standards so that a parameter set behaves identically across competing simulators.

BSIM4 is sometimes characterized as a threshold-voltage model with a large empirical parameter count, a design choice that gave it the flexibility to fit aggressive processes but also made extraction laborious and gave some parameters limited physical meaning. Its ubiquity nonetheless made it the reference against which foundries delivered process design kits for many technology nodes.

The EKV Model

The EKV model, named for its originators Enz, Krummenacher, and Vittoz at the Swiss Federal Institute of Technology in Lausanne, took a different conceptual route. It referenced terminal voltages to the local substrate rather than to the source and built its formulation around the inversion charge, expressing drain current through a single equation continuous from weak to strong inversion. This charge-based, symmetric approach made EKV particularly attractive for low-power and analog design, where operation in moderate inversion and weak inversion is common and where the smoothness of the transconductance-to-current ratio across all regions is essential. The model emphasized a small set of physically meaningful parameters, which suited hand analysis and design intuition as well as simulation.

The PSP Model

PSP is a surface-potential-based MOSFET model developed jointly by Philips, later NXP, and Pennsylvania State University, from which its name derives. Rather than computing current from a threshold voltage, a surface-potential model solves for the electrostatic potential at the silicon surface and derives charge and current from it, which yields an inherently continuous description across all inversion regions and a faithful account of the moderate-inversion behavior that threshold-based models struggle to capture. PSP was selected as an industry standard model by the Compact Model Coalition and is noted for its accurate modeling of distortion and other nonlinear effects, a consequence of the high-order continuity that surface-potential formulations provide. Surface-potential models such as PSP and the HiSIM family from Hiroshima University represent the methodological successor to the threshold-voltage approach.

Bipolar Transistor Models

The bipolar junction transistor predates the MOSFET as an integrated device, and its compact modeling has a correspondingly long lineage. Bipolar transistors remain essential in precision analog, radio-frequency, and high-speed applications, and their models must capture injection, recombination, and high-injection transport across forward and reverse operation.

The Gummel-Poon Model

The Gummel-Poon model, introduced by Hermann Gummel and H. C. Poon at Bell Laboratories in 1970, became the foundational charge-control description of the bipolar transistor and the bipolar model built into virtually every SPICE implementation. Its central construct is the base charge, which links the collector current to the integrated majority-carrier charge in the base and thereby captures effects that the simpler Ebers-Moll model omits. Among these are the Early effect, in which the collector current rises with collector-emitter voltage because of base-width modulation, and high-injection roll-off, in which the current gain falls at high current densities. The model also represents base and emitter recombination through additional ideality-factor terms that bend the Gummel plot of collector and base current at low bias.

Advanced Bipolar Models

As bipolar and silicon-germanium heterojunction transistors pushed to higher speeds, the Gummel-Poon model proved insufficient for self-heating, distributed effects, and the steep doping profiles of modern devices. Two standardized successors emerged. VBIC, the Vertical Bipolar Inter-Company model, extended Gummel-Poon with improved Early-effect modeling, a parasitic substrate transistor, an integrated thermal network for self-heating, and better behavior across temperature. HICUM, the High-Current Model developed largely at the Dresden University of Technology, provided a physics-based description suited to high-frequency silicon-germanium technology, including transit-time and high-injection effects critical at the frequencies where such devices operate. Both are maintained as public standards and selected through the same Compact Model Coalition process that governs the MOSFET models.

Physical Effects in Modern Models

A textbook square-law MOSFET equation predicts the behavior of a long, wide, room-temperature device adequately and the behavior of a nanometer-scale device hardly at all. The difference is the accumulation of physical effects that grow important as dimensions shrink, and a modern compact model is in large part a catalog of these effects expressed in differentiable form.

Short-Channel Effects

When the channel length becomes comparable to the depletion widths of the source and drain junctions, the gate loses some of its exclusive control over the channel charge. The threshold voltage falls as the channel shortens, a roll-off captured by short-channel-effect parameters. Drain-induced barrier lowering (DIBL) further reduces the threshold as the drain voltage rises, because the drain field reaches into the channel and lowers the source-to-channel barrier. Velocity saturation limits the carrier velocity at high lateral fields, so the drain current saturates at a lower voltage and rises more nearly linearly with gate overdrive than the square law predicts. Channel-length modulation, the MOSFET analogue of the Early effect, gives the saturation current a finite output conductance as the effective channel shortens with drain voltage. Each of these effects has a corresponding set of parameters whose values the extraction process determines.

Mobility Effects

Carrier mobility is not a constant. The vertical field produced by the gate pulls carriers toward the oxide interface, where surface scattering reduces their mobility; this mobility degradation with gate voltage is modeled through field-dependent reduction parameters. Coulomb scattering from ionized impurities, phonon scattering that worsens with temperature, and surface-roughness scattering each contribute, and the model rolls them into effective expressions that depend on the transverse field and the temperature. Accurate mobility modeling is essential because it governs both the magnitude of the drain current and its temperature coefficient, the latter being the reason a circuit's bias point drifts as the die warms.

Leakage and Tunneling

At nanometer scales, currents flow where ideally none should. Subthreshold conduction, an exponential diffusion current below threshold, sets the off-state leakage and the slope of the log-current-versus-gate-voltage characteristic. When gate oxides thin to a few atomic layers, electrons tunnel directly through the dielectric, producing a gate leakage current that the model must represent. Band-to-band tunneling and gate-induced drain leakage add further off-state paths near the drain junction. These leakage mechanisms, negligible in older technologies, became first-order concerns for the standby power of dense digital circuits and therefore became standard components of the BSIM4 and later models.

Charge and Capacitance Modeling

Direct-current accuracy is only half of a compact model. Dynamic and high-frequency behavior depend on how charge is stored and redistributed as the terminal voltages change, and a model that fits the static current-voltage curves perfectly may still mispredict switching speed, settling, or radio-frequency gain if its charge description is wrong.

A physically sound model derives its capacitances from a single, consistent charge description rather than from independent capacitor elements. Terminal charges are defined as functions of the terminal voltages, and the capacitances are their partial derivatives. This charge-based formulation guarantees charge conservation, the property that no charge is created or destroyed as a device cycles through a loop of bias points; models that assigned capacitances independently could violate conservation and inject spurious charge during transient simulation. Because the gate, drain, source, and bulk charges each depend on all the terminal voltages, the full description is a matrix of capacitances, including the nonreciprocal transcapacitances that distinguish a four-terminal transistor from a network of two-terminal capacitors.

The intrinsic charges of the channel are augmented by parasitic and extrinsic capacitances: the overlap capacitances where the gate extends over the source and drain diffusions, the fringing fields around the gate edge, and the junction capacitances of the reverse-biased source and drain diodes, which themselves vary with the applied voltage. For radio-frequency operation, the model is further extended with a substrate resistance network and a gate resistance, because at high frequency the distributed nature of these parasitics shapes the input impedance and the maximum oscillation frequency. The fidelity of the capacitance and parasitic description ultimately determines whether a simulated oscillator runs at the right frequency or a simulated logic path meets its timing.

Model Parameter Extraction

A compact model is a template; a parameter set makes it describe a particular fabrication process. Extraction is the procedure that determines the dozens or hundreds of parameter values from measured data so that the model reproduces the silicon a foundry actually produces. It is among the most demanding tasks in the modeling flow, because the parameters are numerous, correlated, and unequally observable, and a naive global fit will find a mathematically optimal but physically meaningless solution.

Sound extraction proceeds in stages that mirror the physics. The modeler measures families of characteristic curves: transfer characteristics of drain current versus gate voltage at several drain and body biases, output characteristics of drain current versus drain voltage, capacitance-voltage curves, and the same measurements repeated across a range of device geometries and temperatures. Parameters are then extracted in a sequence that isolates each effect where it dominates. Threshold-related parameters are fit from low-drain transfer curves in subthreshold and near threshold; mobility and series-resistance parameters from the strong-inversion linear region; saturation and output-conductance parameters from the high-drain output curves; and the geometry-scaling parameters from the trend of these quantities across the measured length and width array. Capacitance parameters are extracted separately from the capacitance-voltage data, and temperature coefficients from measurements at multiple temperatures.

This staged, locally constrained approach keeps each parameter close to its physical meaning and prevents one effect from masquerading as another. Optimization routines refine the fit, but they are applied to small, well-conditioned parameter groups rather than to the entire set at once. The product is a nominal parameter set, often called a typical or center model. Production process design kits extend it with corner sets that represent slow and fast process extremes and with statistical descriptions, addressed by the methods of statistical analysis, that let a designer simulate the manufacturing spread rather than a single idealized device.

Verilog-A Behavioral Modeling

Standard compiled models such as BSIM and PSP are built into commercial simulators in optimized native code, but designers and researchers frequently need models that no standard provides: a novel device, a sensor, a behavioral abstraction of a block, or an experimental physical formulation. Verilog-A, the analog subset of the Verilog-AMS language, is the medium for authoring such models. It lets a modeler express device behavior in readable analog equations that the simulator compiles and solves alongside its built-in models.

A Verilog-A model declares the device terminals and parameters and then states, in an analog block, the relationships between branch voltages and currents. The central construct is the contribution operator, which asserts a relationship the simulator must satisfy implicitly, allowing the description of the bidirectional, simultaneously-solved equations that characterize analog circuits rather than the sequential assignments of a procedural language. The language supplies analog operators for the time derivatives and integrals that express charge storage and dynamic behavior, event constructs for detecting threshold crossings, and built-in functions for thermal noise, flicker noise, and other stochastic effects. Charge is contributed through the time-derivative operator applied to a charge expression, which is the Verilog-A way of declaring a capacitance while preserving charge conservation.

The discipline required to write a robust Verilog-A model recapitulates the criteria for any good compact model. The equations must be continuous and infinitely differentiable, because the simulator differentiates them automatically to build its Jacobian and any kink will impair convergence. Parameters should carry ranges and units. The model should behave sensibly at the boundaries of its validity. Verilog-A is also the reference language in which the Compact Model Coalition distributes its standard models, so that a single authoritative source defines the equations and any simulator can implement them identically. For production use a hand-written Verilog-A model is often slower than a native build, but it is indispensable for prototyping, for research, and for capturing devices outside the standard catalog.

Model Validation and Quality Assurance

A model and its parameters are hypotheses about how silicon behaves, and they are worth no more than the validation that tests them. Validation establishes that a model reproduces measured data, behaves numerically well, and remains trustworthy when used beyond the exact conditions it was fit to.

The first test is fit quality: the model with its extracted parameters must match the measured current-voltage and capacitance-voltage data across the full envelope of bias, geometry, and temperature, not merely at the points emphasized during extraction. Equally important is behavior between and beyond those points, where a model that interpolates well may still extrapolate absurdly. Benchmark suites probe this systematically. The Gummel symmetry test, for example, checks that a MOSFET model behaves correctly and smoothly as the drain and source voltages swap roles through zero, exposing the discontinuities at the origin that plagued earlier models and that corrupt the simulation of passive mixers and switched circuits. Other checks verify that the transconductance-to-current ratio is continuous from weak to strong inversion, that higher-order derivatives are smooth enough for distortion analysis, and that the output conductance is positive and well behaved.

Numerical quality assurance asks whether the model converges reliably, evaluates efficiently, and produces continuous derivatives everywhere in its operating space, including at the boundaries of bias regions and at extreme arguments where exponentials and logarithms can overflow. Foundry qualification adds a further layer: a process design kit is released only after its models are correlated against measured silicon from production wafers and shown to track the corners and the statistical spread observed in manufacturing. The validated model, together with its documented range of applicability and its known limitations, is what allows a designer to trust a simulation enough to commit a design to fabrication.

Summary

Compact modeling translates the physics of semiconductor devices into the analytic equations a circuit simulator can evaluate at scale, balancing accuracy, continuity, physical fidelity, scalability, and speed. MOSFET modeling progressed from threshold-voltage formulations such as the long-dominant BSIM family to charge-based and surface-potential models such as EKV and PSP that describe all inversion regions continuously, while bipolar modeling advanced from the foundational Gummel-Poon charge-control model to the VBIC and HICUM standards for high-speed devices. Modern models earn their accuracy by cataloging the short-channel, mobility, and leakage effects that the square law omits and by deriving capacitances from a charge-conserving description of the terminal charges. Parameter extraction, conducted in physics-guided stages, fits a model to a real process, and Verilog-A provides the language for authoring standard and custom models alike. Validation against measured silicon, including symmetry and continuity benchmarks, is what finally licenses a model for use, and the related topics place these models within the broader practice of simulating, designing, and qualifying analog and mixed-signal circuits.

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