Electronics Guide

Current mirrors and bias circuits form the essential infrastructure of analog integrated circuits, providing the precise current references and distribution networks that enable predictable circuit operation. In integrated circuit design, current sources are preferred over voltage sources for biasing because currents can be accurately copied and scaled across a chip, they provide high output impedance that improves circuit performance, and they are less sensitive to supply voltage variations. From the simplest two-transistor mirror to sophisticated wide-swing cascode structures, these circuits translate a single reference current into the multiple bias currents needed throughout an analog IC.

The challenge in bias circuit design lies in achieving accuracy, stability, and supply independence while consuming minimal silicon area and power. A well-designed biasing network must maintain consistent operating points across process variations, temperature changes, and supply voltage fluctuations. This article explores the hierarchy of current mirror topologies, from basic structures suitable for non-critical applications to high-performance designs for precision analog circuits, along with the self-biasing and startup techniques essential for robust operation.

Basic Current Mirror Principles

The fundamental current mirror exploits the matching properties of integrated transistors to replicate a reference current. When two transistors share identical physical dimensions and operating conditions, they carry equal currents. By forcing a known current through a diode-connected input transistor and connecting the gate (or base) of an output transistor to the same node, the output transistor mirrors the input current.

The Simple MOS Current Mirror

The basic NMOS current mirror consists of two matched transistors with their gates connected together and their sources tied to a common node (typically ground). The input transistor has its drain connected to its gate, forming a diode connection that sets the gate-source voltage. The output transistor, sharing this gate voltage, produces an output current related to the input current by the ratio of device dimensions:

I_out / I_ref = (W/L)_out / (W/L)_ref

This relationship assumes the transistors operate in saturation, where the drain current depends primarily on the gate-source voltage according to the square-law model. By adjusting the width-to-length ratios, designers can scale currents up or down with precision limited mainly by device matching and channel-length modulation effects.

Output Impedance Limitations

The simple current mirror's output impedance equals the output resistance of the mirror transistor, approximately:

r_out = 1 / (lambda * I_D) = V_A / I_D

where lambda is the channel-length modulation parameter and V_A is the Early voltage equivalent. For a typical process with lambda around 0.1 per volt and a 100 microampere bias current, output impedance might be only 100 kilohms. This limited impedance causes the output current to vary with the output voltage, degrading performance in circuits that require ideal current source behavior.

Matching Considerations

Current mirror accuracy depends critically on transistor matching. Sources of mismatch include:

• Threshold voltage variation: Random dopant fluctuations cause threshold differences that produce current errors, particularly at low overdrive voltages
• Mobility variation: Local stress and doping variations affect carrier mobility
• Dimension mismatch: Photolithographic variations in transistor width and length
• Temperature gradients: Thermal differences across the die affect device parameters

Matching improves with increased device area, higher overdrive voltage, and careful layout using common-centroid techniques with dummy devices at the array edges.

Cascode Current Mirrors

The cascode current mirror dramatically improves output impedance by stacking a common-gate transistor above the basic mirror transistor. This cascode device shields the mirror transistor from output voltage variations, maintaining a nearly constant drain voltage on the lower transistor regardless of the output node voltage.

Basic Cascode Structure

In a cascode mirror, each branch contains two transistors in series. The lower transistor operates as in a simple mirror, with its gate voltage set by the diode-connected reference. The upper transistor, the cascode device, has its gate connected to a bias voltage that holds the drain of the lower transistor at a fixed potential. The output impedance increases to approximately:

r_out = g_m2 * r_o1 * r_o2

where g_m2 is the transconductance of the cascode transistor, and r_o1 and r_o2 are the output resistances of the lower and upper transistors respectively. For typical device parameters, this represents an improvement of 50 to 100 times over the simple mirror.

Generating the Cascode Bias Voltage

The cascode bias voltage must position the drain of the lower transistor to keep it in saturation while leaving adequate voltage headroom for the cascode device and the load circuit. A common approach uses a diode-connected transistor carrying the reference current, with its gate connected to the cascode gates. The bias voltage automatically tracks process and temperature variations that affect threshold voltages.

The required cascode bias voltage is approximately:

V_bias = V_GS_cascode + V_DS_sat_lower = V_th + 2 * V_overdrive

This sets the minimum output voltage compliance at V_DS_sat_lower + V_DS_sat_cascode, or approximately twice the overdrive voltage above the source rail.

High-Compliance Cascode

The standard cascode mirror requires two saturation voltages of headroom, limiting use in low-voltage applications. High-compliance (or high-swing) cascode designs reduce this requirement by biasing the cascode transistors at the edge of saturation. The bias voltage is reduced to:

V_bias = V_GS_cascode + V_DS_sat_lower - V_overdrive = V_th + V_overdrive

This positions the lower transistor's drain just at the boundary of saturation, recovering one overdrive voltage of headroom. While this improves voltage compliance, it slightly degrades output impedance because the lower transistor operates at the edge of the triode region.

Wide-Swing Cascode Structures

Wide-swing cascode current mirrors achieve both high output impedance and maximum voltage compliance by carefully optimizing the bias conditions for each transistor. These structures are essential in low-voltage analog design where every millivolt of signal swing is precious.

Design Principles

The wide-swing cascode positions each transistor at exactly the edge of saturation, where V_DS equals V_overdrive. For an NMOS wide-swing cascode mirror, the minimum output voltage is simply:

V_out_min = 2 * V_overdrive

This represents the theoretical minimum for maintaining both transistors in saturation. Achieving this requires precise bias voltage generation that tracks the overdrive voltage as process, temperature, and supply conditions change.

Wide-Swing Bias Generation

Generating the correct wide-swing cascode bias requires a reference branch that operates under the same conditions as the mirror output. A common technique uses a matched transistor pair with one device diode-connected and the other configured as a cascode, both carrying the reference current. The voltage developed across this stack provides the correct bias for the main mirror's cascode transistors.

More sophisticated approaches use feedback loops that sense the drain voltage of the lower transistor and adjust the cascode bias to maintain the optimal operating point. These active biasing schemes provide better tracking across operating conditions but add complexity and potential stability concerns.

Triple Cascode and Beyond

For applications requiring extremely high output impedance, additional cascode levels can be stacked. A triple cascode provides output impedance proportional to (g_m * r_o)^2 * r_o, offering another factor of g_m * r_o improvement. However, each additional level consumes another overdrive voltage of headroom and adds complexity to bias generation. Triple cascodes find use primarily in high-impedance applications like charge integrators and precision sample-and-hold circuits where the ultimate output impedance justifies the headroom sacrifice.

Wilson and Improved Wilson Mirrors

The Wilson current mirror achieves high output impedance through negative feedback rather than cascode stacking. Originally developed for bipolar transistors by George Wilson, the topology translates well to MOS implementations and offers different tradeoffs than cascode structures.

Wilson Mirror Operation

The basic Wilson mirror uses three transistors arranged so that the output current flows through a transistor whose gate is driven by another transistor's drain. Any change in output current is sensed and fed back to oppose the change. In the MOS implementation:

• M1: Diode-connected input transistor carrying the reference current
• M2: Mirrors the reference current, with its drain connected to the gate of M3
• M3: Provides the output current, with its source connected to M2's drain

The feedback mechanism works as follows: if the output voltage rises, attempting to increase I_out through M3, this increase would also flow through M2, raising M2's drain voltage. The higher gate voltage on M3 partially compensates by increasing M3's conduction, but the feedback reduces the net sensitivity to output voltage variations.

Output Impedance Analysis

The Wilson mirror's output impedance is approximately:

r_out = g_m3 * r_o3 * r_o2 / 2

This is comparable to a simple cascode but achieved through a different mechanism. The Wilson topology offers the advantage of requiring only one diode-connected device in the reference branch, potentially saving headroom compared to a cascode with separate bias generation.

Improved Wilson Mirror

The basic Wilson mirror has a systematic offset error because M1 and M2 operate with different drain voltages, causing channel-length modulation to produce unequal currents. The improved Wilson mirror adds a fourth transistor that equalizes the drain voltages of M1 and M2, eliminating this error source.

In the improved structure, an additional transistor is placed in series with M1's drain, with its gate connected to M2's drain. This cascode-like addition forces the drain voltages of M1 and M2 to match, improving current matching to the level limited only by device mismatch rather than Early voltage effects.

Comparison with Cascode

Wilson and cascode mirrors each have advantages:

• Wilson advantages: Potentially simpler bias generation, inherent feedback for stability
• Cascode advantages: Higher output impedance for same transistor count, better high-frequency response due to absence of feedback loop
• Bandwidth considerations: The Wilson's internal feedback loop creates a pole that can limit high-frequency performance, while the cascode has a purely feedforward structure

Modern analog IC design tends to favor cascode structures for their superior high-frequency behavior, but Wilson mirrors remain useful in applications where their specific characteristics offer advantages.

Self-Biased References

Self-biased reference circuits generate stable currents or voltages without requiring an external reference. These circuits use positive feedback to establish an operating point where the circuit equations have a non-trivial solution. The challenge lies in ensuring reliable startup and stable operation across all conditions.

Beta Multiplier Reference

The beta multiplier is a fundamental self-biased current reference that produces a current proportional to a resistor value divided by transistor transconductance parameters. The circuit uses two NMOS transistors with different W/L ratios in a crossed-coupled configuration with a resistor in one branch.

The reference current is approximately:

I_ref = (2 / (mu_n * C_ox)) * (1 / R^2) * ((1 / sqrt(K)) - 1)^2 * (L / W)

where K is the ratio of the W/L values of the two transistors. The current depends on the resistor value, making this suitable for applications where process variations in both resistors and transistors tend to track. The temperature coefficient can be designed to be positive, negative, or zero by appropriate choice of the transistor size ratio.

Constant-g_m Bias

A variation of the beta multiplier establishes a current that keeps transconductance constant across temperature and process variations. By setting K equal to 4 and appropriate resistor sizing, the generated current produces a transconductance:

g_m = 2 / R

This constant-g_m biasing is valuable for circuits where bandwidth depends on transconductance, as it stabilizes the frequency response despite temperature and process variations.

Stability Considerations

Self-biased references have two equilibrium points: the desired operating point and the trivial solution where all currents are zero. The positive feedback that enables self-biasing can also make the circuit sensitive to disturbances. Key stability considerations include:

• Operating point selection: The circuit must reliably choose the desired equilibrium over the zero-current state
• Noise sensitivity: Positive feedback can amplify noise and cause jitter
• Supply coupling: Variations in supply voltage can modulate the operating point
• Startup transients: Power-on behavior must guarantee reaching the correct state

Careful design addresses these concerns through proper loop gain management and explicit startup circuits.

Startup Circuits and Considerations

Every self-biased reference requires a startup circuit to ensure the system exits the zero-current equilibrium and settles at the desired operating point. Without startup assistance, the reference might remain indefinitely in the off state or take unacceptably long to reach normal operation.

Startup Circuit Requirements

An effective startup circuit must:

• Detect the zero-current state: Identify when the reference is stuck at the unwanted equilibrium
• Inject starting current: Provide a momentary pulse or bias that pushes the reference toward normal operation
• Disengage after startup: Remove itself from the circuit once normal operation is established to avoid affecting steady-state performance
• Consume minimal static power: After startup, the circuit should draw negligible current

Common Startup Topologies

Several startup approaches are commonly employed:

Capacitor-based startup: A capacitor couples a transient from the supply ramp to inject charge into the reference during power-on. Once the supply stabilizes, the capacitor blocks DC and the startup path becomes inactive. This approach is simple but may not function correctly during slow supply ramps or brown-out conditions.

Threshold-sensing startup: A transistor biased near threshold monitors a reference node. When the reference is off, this transistor conducts and injects startup current. As the reference comes up, the node voltage changes and cuts off the startup device. This method provides robust detection of the zero-current state.

Current comparator startup: A differential stage compares the reference current to a small bleed current. When the reference current is below the threshold, startup circuitry activates. This approach offers precise control over startup behavior but requires additional circuitry.

Multiple Equilibrium Prevention

Some reference topologies have multiple non-zero equilibria in addition to the desired operating point. Startup circuits must be designed to favor the correct equilibrium. Analysis of the circuit's I-V characteristics and careful placement of startup injection points ensures the system converges to the intended state.

Power-On Reset Integration

Startup circuits often integrate with the chip's power-on reset (POR) system. The POR holds digital circuits in reset until the reference has stabilized, ensuring that bias currents are valid before normal operation begins. Coordination between reference startup and POR timing prevents glitches and ensures proper initialization.

Supply-Independent Biasing

Practical bias circuits must maintain consistent operating points despite variations in the power supply voltage. Supply-independent biasing uses feedback or cancellation techniques to reject supply disturbances and provide currents and voltages that remain stable as the supply varies.

Sources of Supply Sensitivity

Several mechanisms cause bias circuits to depend on supply voltage:

• Body effect: As supply voltage changes, source-to-bulk voltages change, modulating threshold voltages
• Drain voltage variation: Supply changes propagate to drain voltages, affecting currents through channel-length modulation
• Substrate coupling: Capacitive and resistive coupling through the substrate can inject supply noise
• Reference topology: Some reference structures have inherent supply dependence in their operating principles

Cascode Regulation

Cascode structures inherently provide supply rejection by shielding the bias transistor from supply variations. A well-designed cascode mirror with proper bias voltage generation can achieve power supply rejection ratios (PSRR) of 60 dB or more. The cascode device absorbs supply variations, maintaining a nearly constant drain voltage on the mirror transistor.

Regulated Cascodes

The regulated cascode, also known as the gain-boosted cascode, uses an amplifier in the cascode feedback loop to further improve supply rejection. The amplifier senses the drain voltage of the lower transistor and adjusts the cascode gate to maintain an exactly constant drain potential. This active regulation provides extremely high output impedance and supply rejection, limited primarily by the amplifier's gain and bandwidth.

The regulated cascode's output impedance is approximately:

r_out = A * g_m * r_o^2

where A is the amplifier gain. Values exceeding 10 megohms to 100 megohms are readily achievable, enabling precision applications like high-resolution data converters.

Supply Filtering

Low-frequency supply variations can be attenuated by filtering within the bias network. Large capacitors on bias voltage nodes create low-pass filters that reject supply ripple. In some designs, dedicated supply regulators power the bias circuitry from a cleaner internal supply derived from the main supply.

Temperature-Independent References

Many applications require bias currents that remain stable across the operating temperature range. Temperature-independent biasing combines current components with complementary temperature coefficients to achieve near-zero net temperature sensitivity.

Temperature Dependencies in MOS Devices

MOS transistor parameters vary significantly with temperature:

• Threshold voltage: Decreases approximately 1-2 mV per degree Celsius
• Carrier mobility: Decreases roughly as T^(-1.5) to T^(-2)
• Transconductance: Decreases due to mobility reduction, partially offset by threshold decrease

A current determined solely by V_GS^2 / R would have complex temperature behavior due to these competing effects.

PTAT and CTAT Currents

Temperature-independent references typically combine:

• PTAT (Proportional To Absolute Temperature): Current that increases linearly with temperature, generated from thermal voltage V_T = kT/q differences
• CTAT (Complementary To Absolute Temperature): Current that decreases with temperature, typically derived from V_BE or V_GS voltages

By summing appropriately scaled PTAT and CTAT components, the temperature coefficients cancel at the first order, leaving only higher-order residual variation.

Resistor Temperature Matching

The resistors used in reference circuits also have temperature coefficients. Polysilicon resistors typically have positive temperature coefficients of 500 to 2000 ppm per degree Celsius, while diffused resistors may have different characteristics. Temperature-independent design must account for resistor variations, either by choosing resistors with coefficients that aid cancellation or by using resistor ratios that are temperature-insensitive.

Curvature Compensation

First-order temperature compensation leaves residual curvature, causing the reference to vary slightly with the square or higher powers of temperature. For precision applications, curvature compensation adds a nonlinear correction term that cancels the residual variation. Techniques include using transistors at different current densities, adding piecewise-linear correction circuits, or exploiting nonlinear temperature dependencies of particular device parameters.

Programmable Current Sources

Many integrated circuits require adjustable bias currents for calibration, mode selection, or adaptive operation. Programmable current sources provide digitally or analog-controllable output currents while maintaining the accuracy and stability of fixed references.

Binary-Weighted Current Arrays

The most common programmable current source uses an array of current mirror outputs with binary-weighted W/L ratios. Digital control signals enable or disable individual array elements, producing an output current equal to the sum of the enabled elements:

I_out = I_unit * (b_0 * 2^0 + b_1 * 2^1 + ... + b_n * 2^n)

This architecture efficiently covers a wide current range with logarithmic resolution. Matching requirements increase with the number of bits, as the MSB transistor must match N times the unit current where N is 2^n.

Thermometer-Coded Arrays

Thermometer coding uses an array of identical unit current sources, each controlled by one bit of a thermometer-coded word. To produce current I, exactly I/I_unit sources are enabled. This approach offers improved matching because all elements are identical, but requires more control signals and larger decoder logic.

Segmented architectures combine binary weighting for fine bits with thermometer coding for coarse bits, balancing matching performance against complexity.

Current Trimming

Production variations often require current trimming to meet specifications. Common trimming approaches include:

• Laser trimming: Resistors or fuse links are trimmed during wafer test, permanently adjusting the reference
• Zener zapping: Anti-fuses are programmed by high-current pulses to add or remove current sources
• EEPROM calibration: Nonvolatile memory stores trim codes that configure the current source on power-up
• OTP memory: One-time programmable fuses provide low-cost permanent trimming

Dynamic Current Scaling

Power-conscious designs often scale bias currents based on operating mode. Programmable current sources enable reducing bias during standby or low-performance modes, then restoring full current for active operation. The reference and distribution network must support smooth transitions without causing circuit upset or excessive settling time.

Current Steering DACs

Current steering digital-to-analog converters represent a specialized application of current mirror and programmable source techniques. These circuits convert digital codes to analog output currents with high speed and precision, finding use in video, communications, and test equipment.

Current Steering Principles

In a current steering DAC, the digital input controls switches that direct currents from an array of weighted sources to either the output node or a dummy load. The sum of currents steered to the output produces the analog output current. Key advantages include:

• High speed: Switches only redirect existing currents; no charging or discharging of large capacitances
• Constant power: Total current from the array remains constant regardless of code, minimizing supply variation
• Differential outputs: Natural provision of complementary outputs for differential signaling

Unit Element Matching

DAC accuracy depends critically on matching between current source elements. Random mismatches cause differential and integral nonlinearity errors. For an N-bit DAC, the unit element matching requirement is approximately:

sigma_I / I less than 1 / (2^N * sqrt(12))

For a 10-bit DAC, this demands matching better than 0.3%, challenging but achievable with careful layout and adequate device sizing. Larger transistors exhibit better matching due to averaging of random variations over larger areas.

Switching Transients

Code transitions in current steering DACs produce transient glitches due to timing skew between switches and charge injection from the switch transistors. Major/minor code transitions (like 0111 to 1000) are particularly problematic because many switches change simultaneously with potential timing differences.

Glitch reduction techniques include:

• Careful switch design: Minimizing and matching switch transistor sizes
• Complementary switches: Using NMOS and PMOS switches to cancel charge injection
• Return-to-zero operation: Resetting to a mid-scale code between samples to equalize glitches
• Segmented architecture: Using thermometer coding for MSBs to reduce simultaneous transitions

Settling Time

High-speed DAC applications demand fast settling to the final output value. The settling time depends on the output node capacitance and the output impedance of the current sources. Wide-bandwidth current sources with moderate output impedance often outperform high-impedance sources that settle slowly, despite the latter's better DC accuracy.

Current Distribution Networks

Large analog ICs require distribution of bias currents from a central reference to circuits spread across the die. The distribution network must maintain current accuracy despite IR drops, thermal gradients, and coupling from noisy circuits.

Master-Slave Distribution

A common approach uses a master current source that generates the reference current, distributed through a bias voltage to slave current mirrors throughout the chip. The master-slave architecture offers:

• Voltage distribution: A single bias voltage is routed across the die, with local mirrors generating currents. This is insensitive to IR drops in the distribution lines since the voltage drop is absorbed by the mirror transistors.
• Scalability: Adding more slave mirrors does not load the reference, provided the bias line capacitance remains manageable
• Matching: Slave mirrors must match each other and the master, requiring consistent device sizing and layout

Bias Line Considerations

The bias voltage line routing affects circuit performance:

• Capacitance: Long lines have significant capacitance that can slow bias settling and couple high-frequency noise
• Resistance: While DC drops are tolerable, AC voltage drops cause frequency-dependent bias modulation
• Shielding: Bias lines should be shielded from switching digital signals to prevent noise coupling
• Decoupling: Local capacitors on bias lines filter high-frequency disturbances

Multiple Reference Domains

Some designs use separate bias references for different circuit sections to prevent coupling between sensitive and noisy areas. Precision analog circuits might have their own quiet bias network isolated from digital interface circuitry. Care is needed when signals cross between bias domains, as operating point differences can cause systematic errors.

Practical Design Examples

Real-world current mirror and bias circuit design involves tradeoffs between performance, area, power, and complexity. Several examples illustrate common design patterns.

Low-Voltage Cascode Mirror

For a 1.8V supply with 200 mV overdrive transistors, a wide-swing cascode mirror provides approximately 1.4V output compliance (1.8V minus two overdrives) while achieving output impedance around 10 megohms. The bias voltage is generated by a matched stack operating at the same current, ensuring tracking across corners.

High-PSRR Reference

A regulated cascode reference for a precision ADC uses a folded-cascode amplifier with 80 dB gain to regulate the cascode voltage. The resulting output impedance exceeds 100 megohms, with PSRR better than 80 dB at low frequencies. Careful compensation of the amplifier prevents instability while maintaining adequate bandwidth.

Temperature-Compensated Bias

A bias generator for a continuous-time filter combines a PTAT current from a delta-V_BE circuit with a CTAT current from a V_BE divided by a resistor. The sum, weighted by resistor ratios, produces a flat temperature response from -40 to +125 degrees Celsius. Second-order curvature correction uses a squared-PTAT term generated from a translinear loop.

Design Methodology and Verification

Systematic design methodology ensures bias circuits meet specifications across all operating conditions.

Specification Development

Bias circuit specifications should include:

• Nominal current values: Required bias currents for each circuit block
• Accuracy requirements: Allowed variation from nominal values
• Temperature range: Operating temperature extremes and allowed variation
• Supply voltage range: Minimum and maximum supply with PSRR requirements
• Settling time: How quickly bias must stabilize after power-on or mode change
• Noise: Acceptable noise contribution to the bias currents

Corner and Monte Carlo Analysis

Thorough verification includes:

• Process corners: Fast, slow, and cross corners (fast-N/slow-P and vice versa)
• Temperature sweep: Full range simulation at multiple corners
• Supply variation: Minimum, nominal, and maximum supply at each corner
• Monte Carlo: Statistical analysis of device mismatch effects
• Startup simulation: Verification that the reference reliably starts from the off state

Layout Verification

Post-layout simulation with extracted parasitics reveals effects not visible in schematic simulation. Particular attention should be paid to parasitic resistance in high-current paths, capacitance on sensitive bias nodes, and substrate coupling from nearby circuits.

Conclusion

Current mirrors and bias circuits provide the essential infrastructure that enables analog integrated circuits to function reliably across process, voltage, and temperature variations. From the simple two-transistor mirror that introduces the concept of current replication to sophisticated wide-swing cascodes and self-biased references, these circuits embody the core principles of analog IC design: exploiting device matching, managing tradeoffs between performance parameters, and creating robust systems from imperfect components.

The progression from basic mirrors through cascode and Wilson topologies to temperature-compensated, supply-independent references illustrates how analog designers layer techniques to overcome fundamental limitations. Each advancement addresses specific weaknesses while introducing its own tradeoffs, requiring the designer to understand the application requirements and choose appropriate complexity levels.

As technology scaling continues to reduce supply voltages while demanding higher performance, the techniques presented here become ever more critical. Wide-swing structures maximize available signal swing, regulated cascodes provide the output impedance needed for precision circuits, and sophisticated biasing networks maintain stable operation despite shrinking margins. Mastery of current mirrors and bias circuits remains fundamental to successful analog IC design across all technology generations.

Related Topics

• Analog Integrated Circuit Design
• Bandgap References and Voltage Biasing
• Analog VLSI Fundamentals
• Voltage References
• Analog Electronics