Design for Testability

Introduction

Design for Testability (DFT) is a collection of design techniques that make analog circuits easier to test during manufacturing and throughout their operational lifetime. While digital circuits benefit from well-established scan chain and boundary scan methodologies, analog circuits present unique challenges due to their continuous signal nature, sensitivity to loading effects, and the complexity of verifying performance parameters rather than simple logic states.

The cost of finding defects increases dramatically as products move through the manufacturing process. A fault detected during wafer probe costs orders of magnitude less to address than one found during system-level testing or, worse, after deployment in the field. By incorporating testability considerations from the earliest stages of design, engineers can dramatically reduce test costs, improve fault coverage, and accelerate time-to-market while ensuring that only properly functioning devices reach customers.

Effective DFT for analog circuits requires balancing the benefits of improved test access against the potential penalties of added silicon area, increased power consumption, degraded performance due to parasitic loading, and additional design complexity. The goal is to achieve comprehensive fault coverage with minimal impact on the circuit's primary function and at acceptable cost.

Test Access Provisions

Test access provisions enable external test equipment to stimulate and measure internal circuit nodes that would otherwise be inaccessible. Proper test access is fundamental to achieving high fault coverage and reducing test time.

Analog Test Buses

Analog test buses provide multiplexed access to multiple internal nodes through a limited number of external pins:

Dedicated test pins: Reserved pins that connect to an internal analog multiplexer, allowing sequential access to multiple internal nodes
Shared pin architectures: Test access that shares pins with functional signals during test mode, preserving pin count for normal operation
Hierarchical access: Multi-level multiplexing that enables access to nodes within sub-blocks through a single test bus
Differential test buses: Paired test access paths that preserve common-mode rejection when measuring differential signals

The analog test bus must be carefully designed to minimize parasitic loading on sensitive nodes while providing sufficient bandwidth and accuracy for the required measurements.

Test Buffer Design

Buffers isolate internal nodes from the test bus and external loading:

Unity-gain buffers: High-input-impedance, low-output-impedance stages that replicate internal voltages without significant loading
Current buffers: Current conveyors or current mirrors that allow observation of internal currents without disrupting circuit operation
High-impedance inputs: Buffer input impedance must be much higher than the source impedance at the node being observed
Bandwidth considerations: Test buffers should have sufficient bandwidth to pass the signals of interest without distortion
Offset and gain errors: Buffer non-idealities must be characterized and accounted for during test measurement interpretation

Probe Pad Placement

Physical probe pads enable direct measurement during wafer-level testing:

Critical node access: Place probe pads at nodes where measurements provide maximum diagnostic information
Probe card compatibility: Arrange pads to match standard probe card configurations and pitch requirements
Minimum pad size: Ensure pads are large enough for reliable probe contact, typically 50 micrometers or larger
Routing considerations: Probe pad connections should not introduce significant parasitics that affect circuit performance
Production versus engineering pads: Some pads may be intended only for characterization during development and can be removed or disconnected in production

Multiplexer Design for Test

Analog multiplexers route internal signals to test outputs:

Low on-resistance: Minimize voltage drops and ensure adequate bandwidth through the multiplexer
Low leakage: Off-state leakage currents must not disturb the node being measured or other nodes in the circuit
Charge injection: Switching transients from multiplexer control signals should be minimized and allowed to settle before measurements
Crosstalk isolation: Adequate isolation between multiplexer channels prevents one signal from affecting another
T-gate switches: Complementary transmission gates using both NMOS and PMOS transistors provide rail-to-rail signal range with relatively constant on-resistance

Built-In Test Features

Built-in test (BIT) features integrate test stimulus generation and response analysis directly on the chip, reducing dependence on external test equipment and enabling testing in situations where external access is limited.

On-Chip Stimulus Generation

Internal circuits that generate test signals eliminate the need for external signal sources:

Reference voltage generators: Precision on-chip references provide known voltage levels for comparison and calibration
Current source arrays: Programmable current sources inject known currents into test points
Oscillators: On-chip oscillators generate test frequencies for AC measurements
Ramp generators: Linear voltage ramps enable measurement of transfer characteristics and linearity
Digital-to-analog converters: On-chip DACs generate arbitrary analog stimulus patterns under digital control
Noise sources: Controlled noise generators test filtering and signal processing functions

On-Chip Response Analysis

Internal measurement circuits capture and evaluate circuit responses:

Comparators: Compare analog responses against threshold levels to produce digital pass/fail results
Window comparators: Verify that signals fall within acceptable upper and lower bounds
Analog-to-digital converters: On-chip ADCs digitize analog measurements for external processing or internal signature analysis
Peak detectors: Capture maximum signal amplitude for AC testing
RMS-to-DC converters: Measure signal power for noise and distortion evaluation
Phase detectors: Measure phase relationships between signals

Built-In Self-Test Architectures

Complete BIST systems combine stimulus generation and response evaluation:

Loopback testing: Connect outputs back to inputs to verify end-to-end signal path integrity
Signature analysis: Compress analog responses into digital signatures for comparison against expected values
Oscillation-based test: Reconfigure circuits as oscillators whose frequency depends on circuit parameters
Checksum methods: Verify relationships between multiple circuit parameters
Concurrent testing: Perform tests during normal operation without interrupting function

Calibration and Trim Circuits

Built-in calibration corrects for manufacturing variations:

Offset cancellation: Measure and store correction values to null amplifier offsets
Gain adjustment: Programmable gain elements compensate for process variations
Frequency tuning: Adjust filter corner frequencies and oscillator frequencies to target values
Non-volatile storage: Fuses, EEPROM, or other non-volatile memory store calibration values
Dynamic calibration: Continuous background calibration during operation maintains accuracy over temperature and time

Boundary Scan for Analog

While IEEE 1149.1 boundary scan is primarily a digital standard, extensions such as IEEE 1149.4 address mixed-signal and analog testing, providing standardized test access for analog circuits.

IEEE 1149.4 Standard

The IEEE 1149.4 standard extends boundary scan to include analog test access:

Analog boundary modules: Specialized cells at analog pins that can connect, disconnect, or measure analog signals
Internal analog bus: Dedicated test buses (AB1 and AB2) that route analog signals to and from analog boundary modules
Test bus interface circuit: Central control logic that manages the analog test bus and coordinates with the digital TAP controller
Compatibility: Maintains backward compatibility with IEEE 1149.1 digital boundary scan

Analog Boundary Module Functions

Each analog boundary module provides multiple test capabilities:

Normal mode: Connects the pin directly to the core circuit with no test bus connection
Disconnect mode: Isolates the pin from the core circuit for testing interconnects independently
Connect mode: Routes the internal analog test bus to the pin while maintaining core connectivity
Measure mode: Connects internal nodes to the analog test bus for measurement

Test Bus Interface Circuit

The TBIC manages analog test bus operations:

Bus switches: Connect individual analog boundary modules to the shared analog test bus
VG voltage source: Provides a guard voltage for driven shields to reduce parasitic effects during measurement
Measurement accuracy: Bus interface design must ensure adequate accuracy for the intended measurements
Instruction set: Extended instructions control analog test modes through the standard JTAG interface

Implementation Considerations

Practical aspects of implementing analog boundary scan:

Area overhead: Analog boundary modules require significant silicon area compared to digital cells
Performance impact: Added switches and routing in the signal path can affect bandwidth and distortion
Pin count: Two dedicated pins for the analog test bus plus optional guard pin
Mixed-signal integration: Coordination between digital JTAG controller and analog test resources
Tool support: Verify that automatic test equipment and software support IEEE 1149.4 features

Observable Nodes

Node observability refers to the ability to monitor internal circuit states during testing. High observability enables rapid fault localization and comprehensive verification of circuit behavior.

Principles of Observability

Key concepts for achieving effective node observability:

Critical path monitoring: Identify and provide access to nodes that most directly indicate correct operation
Fault detection sensitivity: Choose observation points where faults produce the largest measurable effect
Diagnostic resolution: Multiple observation points enable distinguishing between different fault types and locations
Signal integrity: Observation methods must not significantly alter the signal being measured

Voltage Node Observation

Techniques for observing voltage nodes:

High-impedance probing: Connect observation buffers with input impedance much greater than node impedance
Capacitive coupling: AC-couple to nodes to observe signal variations without affecting DC bias
Voltage followers: Unity-gain buffers replicate voltages at observation outputs
Attenuator probes: Resistive dividers scale high voltages to measurable ranges with minimal loading

Current Observation

Methods for measuring currents within circuits:

Current sense resistors: Small resistors in series with current paths; measure voltage drop to infer current
Current mirrors: Replica current paths that produce scaled copies of internal currents at observation outputs
Hall sensors: Magnetic sensing of current flow without direct electrical connection (external measurement)
Transimpedance amplifiers: Convert current signals to voltages for observation

Selecting Observation Points

Strategic selection of which nodes to make observable:

Block boundaries: Interfaces between functional blocks reveal whether individual blocks operate correctly
Bias points: DC operating points of active devices indicate proper biasing
Reference nodes: Voltage and current references affect multiple circuits and warrant observation
Feedback nodes: Points within feedback loops help verify loop stability and gain
Supply currents: Total current consumption often correlates with overall circuit health
Temperature-sensitive nodes: Points where faults cause abnormal temperature dependence

Controllable Nodes

Node controllability refers to the ability to force internal nodes to specific states during testing. Good controllability enables comprehensive testing of circuit behavior under various conditions and simplifies fault isolation.

Principles of Controllability

Fundamental concepts for achieving effective control:

Independent control: Ability to set one node without constraining others enables isolated testing
Full range access: Control circuits should cover the complete operational range of the node
Minimal interference: Control mechanisms should be disconnectable to allow normal operation
Speed of control: Control circuits must be fast enough to support the required test sequences

Voltage Forcing

Techniques for controlling voltage nodes:

Switch injection: Analog switches connect external or on-chip sources to internal nodes
Override amplifiers: Low-output-impedance amplifiers that can drive nodes to specific voltages when enabled
DAC forcing: On-chip digital-to-analog converters provide programmable voltage sources
Resistive injection: Inject current through resistors to shift node voltages by controlled amounts

Current Forcing

Methods for controlling current flow:

Programmable current sources: Digitally controlled current sources inject test currents
Current steering: Switch current flow between normal paths and test loads
Load substitution: Replace normal loads with programmable test loads during test mode
Bias override: Force bias currents to specific values independent of normal bias circuitry

Signal Injection Points

Strategic placement of controllable injection points:

Input stages: Inject signals at amplifier inputs to test gain and frequency response
Feedback paths: Break feedback loops to characterize open-loop behavior
Intermediate stages: Inject at intermediate nodes to isolate front-end from back-end testing
Power supply rails: Control supply voltages to test power supply rejection
Reference inputs: Override reference values to verify reference-dependent behavior

Test Mode Implementation

Test modes configure the circuit for various testing scenarios, enabling access to internal nodes and activating built-in test features while maintaining isolation from normal operation.

Test Mode Control Architecture

Mechanisms for entering and controlling test modes:

Dedicated test pins: Specific pins reserved for test mode control, clearly separating test from functional operation
Encoded test entry: Special sequences on functional pins that unlock test modes, preventing accidental activation
Register-based control: Configuration registers accessed through serial or parallel interfaces select test modes
Fuse-enabled testing: Test features available only before production fuses are programmed
JTAG integration: Test mode control through IEEE 1149.1 or 1149.4 interfaces

Test Mode Types

Common categories of test modes:

Parametric test mode: Enable measurement of DC parameters such as offsets, gains, and threshold levels
AC test mode: Configure for frequency response, bandwidth, and distortion measurements
Loopback test mode: Connect outputs to inputs for end-to-end path verification
Bypass test mode: Allow external signals to bypass certain blocks for isolated testing
Calibration mode: Enable trim and calibration operations
Debug mode: Provide enhanced observability for failure analysis and characterization
Stress test mode: Apply elevated voltages or currents for accelerated life testing

Mode Transition Considerations

Managing transitions between operating modes:

Glitch prevention: Ensure mode transitions do not cause transients that could damage circuits or corrupt data
Settling time: Allow adequate time for circuits to stabilize after mode changes
State preservation: Consider whether internal states should be maintained or reset during mode transitions
Power sequencing: Some test modes may require specific power-up sequences
Reset behavior: Define whether test modes survive system resets or return to normal operation

Test Mode Security

Protecting test modes from unauthorized access:

Access control: Require authentication or special equipment to enter certain test modes
Fuse disabling: Permanently disable sensitive test features after production testing
Limited observability: Restrict which nodes remain accessible in field-serviceable products
Tamper detection: Monitor for unauthorized test mode entry attempts
Data protection: Ensure test modes cannot be used to extract proprietary information

Fault Coverage Analysis

Fault coverage analysis quantifies the effectiveness of a test program in detecting potential defects. Understanding fault coverage helps optimize test development and provides confidence in product quality.

Analog Fault Models

Models that represent potential defects in analog circuits:

Catastrophic faults: Opens and shorts that completely disrupt circuit operation, often detectable by simple functionality tests
Parametric faults: Deviations in component values that cause specifications to be violated while maintaining basic functionality
Soft faults: Degradations that marginally affect performance and may only manifest under certain conditions
Stuck-at faults: Nodes fixed at supply or ground voltage, adapted from digital fault models
Bridging faults: Unintended connections between adjacent nodes
Delay faults: Timing variations that affect dynamic behavior

Fault Simulation

Simulation techniques that evaluate test effectiveness:

Monte Carlo analysis: Statistical simulation of process variations to identify which faults affect which specifications
Sensitivity analysis: Determine which component variations most strongly affect each measured parameter
Fault injection: Simulate specific fault conditions and verify that tests detect them
Boundary analysis: Evaluate test effectiveness at the edges of acceptable parameter ranges
Worst-case analysis: Identify component combinations that produce worst-case behavior

Coverage Metrics

Quantitative measures of test effectiveness:

Defect coverage: Percentage of modeled defects detected by the test program
Specification coverage: Percentage of device specifications verified by testing
Node coverage: Fraction of internal nodes exercised during testing
Parameter coverage: Range of parameter variations explored by the test
Condition coverage: Percentage of operating conditions (temperature, supply voltage) tested

Test Escapes and Defect Level

Understanding and minimizing test escapes:

Test escape: A defective device that passes all tests and ships to customers
Defect level: The proportion of shipped devices that are actually defective, typically measured in defects per million (DPM)
Yield and coverage relationship: Higher yields require less perfect fault coverage to achieve the same defect level
Coverage improvement: Focus on increasing coverage for the most likely defect types based on failure analysis data
Cost-benefit analysis: Balance the cost of additional testing against the cost of test escapes

Test Time Optimization

Production test time directly impacts manufacturing cost. Optimizing test time while maintaining adequate fault coverage is essential for competitive products.

Test Time Components

Understanding where test time is spent:

Setup time: Time required to establish test conditions including power supply settling and temperature stabilization
Measurement time: Time for the actual parameter measurement including signal acquisition and averaging
Processing time: Calculation of derived parameters and pass/fail determination
Handler time: Mechanical time for device positioning, contacting, and sorting
Communication overhead: Data transfer between tester and device under test

Parallel Testing

Testing multiple devices or parameters simultaneously:

Multi-site testing: Test multiple devices in parallel using replicated test hardware
Concurrent measurements: Measure independent parameters simultaneously using multiple test channels
Pipelined testing: Overlap stimulus generation, measurement, and data processing
Gang testing: Apply the same stimulus to multiple devices and measure responses in parallel

Test Optimization Techniques

Methods to reduce test time:

Test ordering: Perform tests in an order that minimizes setup time between tests
Adaptive testing: Skip tests based on results of earlier tests that indicate correct operation
Limit reduction: Reduce the number of data points collected while maintaining statistical confidence
Specification correlation: Test parameters that correlate with multiple specifications rather than testing each specification directly
DSP-based testing: Use digital signal processing to extract multiple parameters from a single measurement
Built-in self-test: Move test functions on-chip to reduce tester interaction time

Test Flow Optimization

Optimizing the overall test program structure:

Test binning: Sort devices by performance level rather than simple pass/fail, capturing yield for lower-performance applications
Early termination: Stop testing as soon as a fatal failure is detected
Statistical process control: Reduce testing when process data indicates stable, in-specification production
Test program generation: Automated tools that create optimized test sequences from specification lists
Continuous improvement: Regular analysis of test data to identify opportunities for optimization

Test Cost Tradeoffs

Balancing test time against other factors:

Test equipment cost: Faster testers and more test channels increase capital cost
Coverage versus time: More thorough testing takes longer but reduces test escapes
Wafer sort versus final test: Early testing catches faults sooner but may miss package-related defects
Production volume: High-volume products justify more investment in test time reduction
Reliability requirements: Safety-critical applications may require more extensive testing regardless of time cost

DFT Design Process

Integrating testability into the design process from the beginning yields better results than attempting to add test features after the design is complete.

Early Planning

Testability considerations during initial design phases:

Testability specifications: Define fault coverage targets and test time budgets alongside functional specifications
Test strategy development: Determine the mix of external testing, built-in test, and production screen methods
Pin allocation: Reserve pins for test access early to avoid pin count conflicts later
Architecture review: Evaluate proposed architectures for inherent testability

Design Implementation

Incorporating testability during detailed design:

Concurrent DFT design: Design test access circuits alongside functional circuits
Observability and controllability audit: Review each block for adequate test access
Test feature simulation: Verify that test circuits function correctly and do not impact normal operation
Layout considerations: Place probe pads and test circuits to minimize impact on critical paths

Verification and Validation

Confirming testability meets requirements:

Fault simulation: Verify that the test program achieves required fault coverage
Test program development: Create and debug test programs using simulation before silicon
Silicon validation: Confirm test functionality on first silicon and characterize test circuit performance
Correlation studies: Verify that test results correlate with actual device performance

Production Support

Ongoing testability activities during production:

Test program maintenance: Update tests as specifications change or new failure modes are discovered
Failure analysis support: Use test access features to diagnose field returns
Yield improvement: Analyze test data to identify systematic issues and guide process improvements
Test cost reduction: Continuously optimize test time while maintaining quality