Electronics Guide

Algorithm Parameters That Shape the Datapath

Accelerator architecture follows directly from the parameters fixed in the NIST standards, so those numbers deserve to be stated plainly. ML-KEM (FIPS 203) and ML-DSA (FIPS 204) both operate on polynomials of 256 coefficients in a negacyclic ring, meaning arithmetic is reduced modulo X^256 + 1. Both scale security by increasing the module dimension rather than the polynomial length: ML-KEM-512, ML-KEM-768, and ML-KEM-1024 use module rank k = 2, 3, and 4, while ML-DSA-44, ML-DSA-65, and ML-DSA-87 use matrix dimensions of 4-by-4, 6-by-5, and 8-by-7 polynomials. One 256-point transform engine therefore serves every parameter set of both algorithms, and only the control logic and buffering change.

The moduli differ substantially. ML-KEM uses q = 3329, a 12-bit prime, so coefficients fit in 12 bits and products in 24. ML-DSA uses q = 8380417, which equals 2²³ - 2¹³ + 1, a 23-bit prime that demands a 23-by-23-bit multiplier and 46-bit intermediate products. A unified engine serving both algorithms must be sized for the larger modulus and wastes capacity when running ML-KEM; separate datapaths keep each one tight at the cost of area. This choice is one of the first decisions in a combined ML-KEM/ML-DSA accelerator.

Data sizes set interface and buffer requirements. ML-KEM-768 uses a 1184-byte encapsulation key, a 2400-byte decapsulation key, and a 1088-byte ciphertext, yielding a 32-byte shared secret. ML-DSA-65 uses a 1952-byte public key and produces 3309-byte signatures. SLH-DSA-SHA2-128s pairs a 32-byte public key with a 7856-byte signature. Compared with a 32-byte elliptic-curve public key and a 64-byte ECDSA signature, these figures explain why memory architecture, not arithmetic, often limits post-quantum accelerator performance in constrained systems.

Number Theoretic Transform Accelerators

The Number Theoretic Transform (NTT) is the computational foundation of efficient lattice-based cryptography. NTT enables polynomial multiplication in quasi-linear time rather than the quadratic time of naive multiplication, making it essential for practical performance of ML-KEM, ML-DSA, and related algorithms. NTT accelerators provide the most significant performance improvement for lattice-based post-quantum implementations.

The NTT is the discrete Fourier transform carried out over a finite field rather than over the complex numbers. A polynomial with n coefficients is evaluated at powers of a primitive root of unity in the field, after which polynomial multiplication becomes coefficient-wise multiplication of the transformed values, followed by an inverse transform to recover the product. Because the ring is negacyclic, the transform is twisted by powers of a 2n-th root of unity so that reduction modulo X^n + 1 is absorbed into the transform itself.

Whether a full transform is possible depends on the modulus, and the two lattice standards differ here in a way that directly affects hardware. ML-DSA's prime admits a primitive 512th root of unity, so the 256-coefficient transform runs to completion through eight layers, reducing multiplication to 256 independent modular products. ML-KEM's prime 3329 admits a 256th root of unity but no 512th root, so the transform stops after seven layers and leaves 128 degree-one polynomials. Multiplying those residues requires a small base-case routine of three modular multiplications and one addition per pair, which the accelerator must implement alongside the butterfly network.

Butterfly units form the basic computational element of NTT accelerators. Each butterfly performs an addition and subtraction combined with multiplication by a twiddle factor (power of a root of unity). The Cooley-Tukey decomposition arranges butterflies in log(n) stages, with n/2 butterflies per stage. Hardware implementations may execute butterflies sequentially, in parallel, or in various pipelined configurations based on area and throughput requirements.

Modular arithmetic within butterflies requires efficient reduction. Hardware multipliers produce double-width products that must be reduced modulo q, and the reduction method significantly affects latency and area. Montgomery reduction keeps operands in a transformed representation and replaces division with multiplications and shifts, which suits pipelines that perform long chains of multiplications. Barrett reduction estimates the quotient with a precomputed reciprocal and returns results in the ordinary representation, which suits isolated operations. Plantard-style reduction, developed for the small moduli of ML-KEM, trades a wider precomputed constant for a shorter critical path and has been adopted in several lightweight designs. Lazy reduction, in which results are allowed to grow within a bounded range across several butterfly stages before a full reduction, removes reduction hardware from the inner loop at the cost of wider intermediate registers.

Memory architecture is critical for NTT accelerator performance. NTT accesses polynomial coefficients in patterns determined by the transform structure, with different stages accessing different stride patterns. Efficient memory interfaces minimize stalls due to bank conflicts or bandwidth limitations. On-chip memory reduces latency but limits polynomial size; off-chip memory supports larger polynomials but introduces access latency.

Polynomial Arithmetic Units

Beyond NTT, lattice-based cryptography requires additional polynomial arithmetic operations including coefficient-wise operations, polynomial addition, and sampling operations. Dedicated hardware for these operations complements NTT acceleration to provide complete lattice cryptography support.

Coefficient-wise operations include addition, subtraction, and multiplication modulo q. While individually simple, these operations occur frequently and benefit from wide datapaths that process multiple coefficients in parallel. SIMD-style processing units apply the same operation across coefficient vectors, improving throughput for operations that do not require the structural complexity of the NTT. Because ML-KEM coefficients occupy 12 bits and ML-DSA coefficients 23 bits, the natural vector width differs between algorithms, and a shared unit must either pad the narrower type or pack coefficients at two densities.

Polynomial addition and subtraction are straightforward coefficient-wise operations that benefit primarily from memory bandwidth and parallelism. The key optimization is ensuring that polynomial storage and access patterns align with computational unit widths, avoiding partial operations that waste hardware capability.

Sampling operations generate polynomial coefficients from specified distributions, and they consume a large share of the cycle budget. ML-KEM builds its public matrix by rejection sampling uniform coefficients from a SHAKE-128 stream seeded with public values, and it draws secret and error polynomials from centered binomial distributions with parameters of two or three, derived from a SHAKE-256-based pseudorandom function. ML-DSA uses analogous uniform and bounded-uniform samplers. Hardware samplers generate coefficients in parallel and feed polynomial storage directly from the hash core, which removes a substantial amount of data movement.

The distinction between public and secret sampling matters for side-channel design. Rejection sampling of the public matrix has a data-dependent iteration count, but the data is derived from a public seed, so variable timing there reveals nothing. Sampling of secret and error polynomials must not exhibit value-dependent timing or power signatures. Treating both cases identically wastes performance; treating them interchangeably risks leakage, so the accelerator's control logic should distinguish them explicitly.

Compression and decompression operations prepare polynomials for transmission or storage, reducing bit widths through controlled rounding. ML-KEM compresses the two ciphertext components to ten and four bits per coefficient at the 512 and 768 parameter sets, and to eleven and five bits at ML-KEM-1024. Each compression is a rounded division by q, which dedicated hardware implements as a multiply-and-shift with a precomputed reciprocal rather than a divider. Serialization then packs the compressed coefficients into a byte stream at widths that do not align with byte boundaries, so barrel shifters and packing buffers are a small but necessary part of the datapath.

Matrix and Vector Operations

Lattice-based cryptography operates on matrices and vectors of polynomials, requiring coordination of multiple polynomial operations. Matrix-vector multiplication, the core operation in ML-KEM key generation and encapsulation, multiplies a k-by-k matrix of polynomials by a k-element vector, producing a k-element vector result. At ML-KEM-768, k = 3, so a single matrix-vector product involves nine polynomial multiplications and six polynomial additions; ML-DSA-65 works with a 6-by-5 matrix and thirty polynomial products. These are the dominant arithmetic workloads in each algorithm.

Matrix-vector multiplication requires n polynomial multiplications and n-1 polynomial additions for each of the m result elements. The operations can be arranged for various resource-throughput trade-offs: minimal hardware performs one polynomial operation at a time; maximum throughput hardware performs all mn multiplications in parallel. Practical designs fall between these extremes based on area and performance requirements.

Scheduling matrix operations affects memory access patterns and hardware utilization. Row-major processing completes each result element before starting the next, requiring storage for one result polynomial and one row of matrix polynomials. Column-major processing processes matrix columns in sequence, accumulating partial results for all output elements simultaneously. Hybrid schedules can optimize for specific memory architectures.

Hardware sharing between matrix operations and other algorithm phases improves resource efficiency. The same NTT units used for polynomial multiplication can handle key generation, encapsulation, and decapsulation with appropriate control logic. Careful scheduling ensures continuous hardware utilization across algorithm phases.

Generating the public matrix on demand rather than storing it is a decisive memory optimization. The matrix is expanded deterministically from a 32-byte seed, so a constrained implementation can regenerate each entry as the schedule reaches it and never hold the full matrix. At ML-KEM-1024 the matrix would otherwise occupy several kilobytes of coefficient storage. The cost is that the hash core must keep pace with the arithmetic core, which is why sampler throughput frequently determines the achievable matrix-multiplication rate rather than multiplier count.

Hash Function Acceleration

Post-quantum algorithms use hash functions extensively for key derivation, message hashing, and in hash-based signature schemes. The hash functions specified in NIST standards, particularly SHA-3 (Keccak) and SHAKE extendable-output functions, benefit from dedicated hardware acceleration.

SHA-3 and SHAKE are built on the Keccak-f[1600] permutation, which transforms a 1600-bit state through 24 rounds of five step mappings: theta, rho, pi, chi, and iota. Hardware implementations range from compact iterative designs that process one round per cycle, to unrolled designs that fold two or more rounds into a single cycle, to slice-serial architectures that process the state a few bits at a time to minimize area. The choice depends on area budget, throughput requirements, and whether hash operations sit on the critical path. In many lattice accelerators the Keccak core is the largest single block, because sampling demands more hash output than the arithmetic units consume coefficients.

Hash-based signatures such as SLH-DSA (FIPS 205, derived from SPHINCS+) place extreme demands on the hash unit. Because signing traverses a hypertree of Merkle trees and a FORS few-time-signature layer, a single signature costs on the order of hundreds of thousands to more than a million invocations of the underlying function, with the small-signature parameter sets the most expensive. FIPS 205 defines instantiations over both SHAKE (Keccak) and SHA-2, so a flexible accelerator may need to support either family. Hardware acceleration is therefore not an optimization but a prerequisite: hash-unit throughput determines signing latency almost entirely.

The structure of hash-based signatures rewards parallelism rather than deeper pipelining of a single hash. The chains of a WOTS+ one-time signature are independent of one another, and sibling nodes of a Merkle tree can be computed simultaneously, so several hash cores operating in parallel scale nearly linearly until memory bandwidth intervenes. Verification is far cheaper than signing, which makes SLH-DSA attractive for secure-boot and firmware-signature checking, where the signing occurs once offline and the verifier is a small embedded device.

Hash function accelerators must support multiple modes of operation. SHAKE functions produce variable-length output needed for key derivation and sampling. SHA3-256 and SHA3-512 produce fixed-length outputs for message hashing. A unified accelerator supports all required modes through configurable parameters.

Memory interfaces between hash accelerators and the rest of the cryptographic system affect overall performance. High-bandwidth interfaces enable streaming of data through hash operations without bottlenecks. Integration with polynomial samplers that consume hash output directly reduces data movement between components.

FPGA Implementation Approaches

Field-Programmable Gate Arrays (FPGAs) provide flexible platforms for post-quantum cryptography acceleration, enabling rapid prototyping, customization, and deployment in applications requiring reconfigurability. FPGA implementations must navigate the trade-offs inherent in programmable logic while achieving acceptable performance.

DSP block utilization significantly affects FPGA performance for post-quantum workloads. Modern FPGAs include hardened DSP slices optimized for multiply-accumulate operations, and mapping NTT butterflies onto them provides substantial speedup over a logic-only implementation. Operand width is the deciding factor: a DSP slice offering a 27-by-18-bit multiplier absorbs an ML-KEM 12-bit coefficient multiplication with room to spare, and can even pack two such multiplications into one slice, whereas ML-DSA's 23-bit operands exceed the narrow port and require either two slices or a decomposition into partial products. An accelerator that must serve both algorithms should be budgeted against the ML-DSA case.

Block RAM provides on-chip storage for polynomial coefficients and intermediate values. FPGA block RAM organization into fixed-width, fixed-depth blocks constrains memory architecture design. Efficient polynomial storage requires matching coefficient sizes and polynomial lengths to available block RAM configurations.

High-level synthesis (HLS) tools enable rapid development of PQC accelerators from C or C++ descriptions. While HLS-generated designs may not achieve the efficiency of hand-optimized RTL, they significantly reduce development time and enable exploration of design alternatives. Critical paths can be hand-optimized after HLS establishes baseline functionality.

Partial reconfiguration capabilities of some FPGAs enable algorithm agility, loading different accelerator configurations to support various algorithms or security levels. This is particularly valuable during the transition period when algorithm choices may evolve. Reconfiguration time and configuration storage requirements must be considered for practical deployment.

ASIC Design Considerations

Application-Specific Integrated Circuits (ASICs) provide maximum performance and efficiency for post-quantum cryptography acceleration, suitable for high-volume applications or those requiring ultimate performance. ASIC design requires larger upfront investment but amortizes across production volume.

Custom arithmetic circuits can be optimized for the specific prime moduli used in standardized algorithms. Barrett or Montgomery reduction circuits tuned for q = 3329 (ML-KEM) or q = 8380417 (ML-DSA) achieve better area and timing than general-purpose modular arithmetic. The sparse binary form of the ML-DSA modulus, 2²³ - 2¹³ + 1, is especially convenient: reduction reduces to a short sequence of shifts, additions, and subtractions with no general multiplier at all. Single-cycle butterfly operations built on such circuits enable high NTT throughput at modest area.

Memory hierarchy design in ASICs can precisely match algorithm requirements. On-chip SRAM provides fast access to coefficient storage with size tailored to maximum polynomial dimensions. Custom memory layouts avoid the fixed configurations of FPGA block RAM. Memory bandwidth can be designed to match computational throughput, avoiding bottlenecks.

Pipeline depth optimization balances latency against throughput for specific algorithm structures. Deep pipelines maximize clock frequency and throughput but increase latency for individual operations. Shallow pipelines provide lower latency at reduced throughput. The optimal balance depends on application requirements and whether operations can be pipelined.

Power optimization through clock gating, power domains, and voltage scaling is more controllable in ASICs than FPGAs. Unused accelerator components can be clock-gated or power-gated when not needed. Voltage scaling can trade performance for power efficiency based on current workload. These optimizations extend battery life in portable devices and reduce cooling requirements in data centers.

Instruction Set Extensions

Instruction set extensions add post-quantum cryptography support to general-purpose processors, providing acceleration without requiring separate accelerator hardware. This approach is particularly valuable for systems that cannot accommodate dedicated accelerators or need flexibility to run diverse workloads.

Vector instructions accelerate coefficient-wise polynomial operations through SIMD processing. Arm Neon and SVE, the RISC-V vector extension, and the AVX2 and AVX-512 families on x86 all process many 16-bit or 32-bit coefficients per instruction, and the reference optimized implementations of ML-KEM and ML-DSA rely heavily on them. Vector units also batch Keccak: because a single Keccak permutation offers little internal parallelism, running two, four, or eight independent permutations in adjacent vector lanes is the standard way to raise sampling throughput. Efficient utilization requires mapping polynomial operations to vector sequences with minimal shuffling overhead, which is where hand-written assembly still outperforms compilers.

Dedicated instructions for modular reduction, butterfly operations, or NTT can provide substantial speedup compared to general-purpose instruction sequences. Adding such instructions requires careful analysis of which operations provide the greatest benefit relative to instruction encoding cost and implementation complexity.

Existing cryptographic instruction extensions help, but only where the hash family matches. Intel SHA extensions and the baseline Arm cryptographic extension accelerate SHA-1 and SHA-2, which benefits the SHA-2 instantiations of SLH-DSA but does nothing for Keccak. Keccak acceleration on Arm comes instead from the optional Armv8.2 SHA-3 instructions, which add the EOR3, RAX1, XAR, and BCAX operations that map directly onto the theta, rho, and chi steps of the permutation. Because these instructions are optional, portable software must retain a vectorized fallback and select at run time, and hardware architects specifying a core for post-quantum work should confirm that the option is present rather than assume it.

Compiler support is essential for practical use of instruction set extensions. Intrinsics provide direct access to new instructions from C code. Automatic vectorization can exploit vector extensions for suitable code patterns. Library implementations using extensions enable application benefits without requiring application code changes.

Constant-Time Implementation in Hardware

Hardware implementations must maintain constant-time execution to prevent timing side-channel attacks. Unlike software where constant-time implementation requires careful programming discipline, hardware can enforce constant-time behavior through structural design choices that eliminate timing variation regardless of processed data.

Fixed-cycle arithmetic operations complete in the same number of cycles regardless of operand values. Early termination optimizations that might reduce cycles for certain inputs must be avoided. Modular multiplication and reduction should complete in fixed time even when inputs could allow shortcuts.

Memory access patterns must be data-independent to prevent cache-timing attacks on systems with shared cache hierarchies. When the accelerator shares cache with other system components, address-based timing variations can leak secret information. Constant-time memory access patterns or dedicated memory without cache sharing eliminate this vulnerability.

Control flow must not depend on secret values in timing-visible ways. Conditional operations should use selection circuits (multiplexers) rather than conditional branches. All paths through the hardware should take the same time, with results selected at the end based on conditions.

Pipeline behavior must be carefully designed to avoid timing variations. Pipeline stalls due to data dependencies should not reveal secret values. Instruction-level parallelism should not vary based on processed secrets. These properties are more naturally achieved in dedicated accelerators than in general-purpose processors where software runs.

Not every source of variable timing is a leak, and treating them all alike is expensive. ML-DSA signing uses the Fiat-Shamir-with-aborts construction, so it repeats the signing loop until a candidate signature satisfies the rejection bounds, and the number of iterations varies from one signature to the next. The design requirement is that each individual iteration be constant-time with respect to the secret key and that rejected candidates never leave the accelerator, not that the total iteration count be fixed. Systems that need bounded worst-case latency, such as real-time control or automotive networks, must instead budget for the tail of that distribution and provide a defined behavior when an iteration limit is reached.

Power and Electromagnetic Countermeasures

Hardware accelerators require protection against power analysis and electromagnetic analysis attacks. Dedicated hardware enables countermeasures that are difficult or impossible to implement effectively in software, providing stronger protection against these physical attacks.

Masking techniques split secret values into random shares processed separately, preventing correlation between power consumption and secrets. Hardware masking can be implemented at the gate level, ensuring that protection extends to all operations on secret data. The overhead is area and latency for additional shares and share recombination.

Dual-rail logic encodes each bit as a pair of complementary signals, maintaining constant switching activity regardless of data values. Transitions always involve one signal rising and one falling, masking the power signature of individual bit values. The area cost is roughly double that of single-rail logic plus the routing complexity of complementary signals.

Random noise injection adds uncorrelated activity to mask the power signature of cryptographic operations. Noise generators can be integrated into the accelerator, consuming power that obscures the signal from useful operations. The noise must be truly random and uncorrelated with the cryptographic computation to be effective.

Shielding and layout techniques reduce electromagnetic emanations from sensitive circuits. Metal layers above and around cryptographic logic block EM emissions. Balanced routing ensures that complementary signals travel similar paths, reducing differential emissions. These physical design techniques complement algorithmic countermeasures.

Fault injection deserves separate attention, because lattice signatures are unusually sensitive to it. A single injected fault during ML-DSA signing can produce a signature that verifies incorrectly yet reveals information about the secret polynomials, so an attacker with glitching capability need not observe power at all. The standard countermeasure is cheap relative to the risk: verify each signature with the public key before releasing it, and suppress the output if verification fails. Redundant computation, checksum verification of NTT results, and sensors for voltage, clock, and laser disturbance provide additional layers. These techniques are treated in more depth in the side-channel resistance article.

Integration Architectures

Post-quantum cryptography accelerators must integrate with host systems through appropriate interfaces and protocols. Integration architecture affects both performance and security, determining how efficiently the host can utilize accelerator capabilities and how well secrets are protected in transit.

Memory-mapped interfaces expose accelerator registers and memory to the host processor's address space. This approach provides flexible access but may expose sensitive data on shared buses. Protected memory regions and access controls limit which software can interact with the accelerator and access key storage.

DMA (Direct Memory Access) enables efficient bulk data transfer between host memory and accelerator without processor involvement. For operations on large amounts of data, DMA reduces overhead compared to processor-mediated transfers. Security considerations include ensuring DMA cannot access memory regions outside the accelerator's authorized scope.

Dedicated interconnects provide isolated communication paths between the accelerator and specific system components. This approach improves security by limiting attack surface but requires additional routing resources. High-security applications may justify dedicated interconnects for key management and cryptographic operations.

Coprocessor architectures tightly couple the accelerator with a processor core, enabling efficient instruction-level interaction. The processor issues cryptographic operations through coprocessor instructions, with results returned through coprocessor registers. This model suits applications requiring fine-grained mixing of general computation and cryptographic operations.

Resource-Constrained Implementations

Many deployment scenarios require post-quantum cryptography in severely resource-constrained devices including IoT sensors, smart cards, and other embedded systems. Hardware acceleration for these platforms must achieve acceptable performance within extreme area and power budgets.

Iterative architectures minimize area by reusing hardware across multiple operations. A single butterfly unit can compute entire NTT transforms by iterating through coefficient pairs. Memory can be reused by processing algorithm phases sequentially. The trade-off is increased latency compared to parallel architectures.

Algorithm selection affects resource requirements significantly. ML-KEM and ML-DSA share the same building blocks, so an accelerator that supports one supports the other at modest incremental cost. SLH-DSA has entirely different characteristics: it needs almost no arithmetic beyond a hash core, which suits a device that already contains one, but its signing cost and multi-kilobyte signatures make it better suited to verification than to signing on a constrained node.

Algorithms still moving through standardization change this calculus. FN-DSA, the Falcon-based signature scheme drafted as FIPS 206, produces the smallest public keys and signatures of the NIST signature candidates, which is attractive where bandwidth is scarce. Its signing procedure, however, depends on Gaussian sampling over floating-point arithmetic that is difficult to implement in constant time, and constrained hardware without a double-precision unit must emulate it. HQC, selected in March 2025 as an additional key-encapsulation mechanism to complement ML-KEM, is code-based: its arithmetic is binary-polynomial multiplication and error-correcting-code decoding, sharing nothing with the NTT datapath. A design that anticipates supporting a code-based fallback should plan for a second arithmetic block rather than expect reuse.

Parameter selection within algorithms provides resource-performance trade-offs. Lower security levels (e.g., ML-KEM-512 versus ML-KEM-1024) require smaller keys and less computation, suitable for applications where the lower security margin is acceptable. Constrained implementations should support at least the minimum security level needed for their application.

Shared resources between cryptographic and application functions maximize utilization of limited hardware. A microcontroller with cryptographic extensions uses the same arithmetic units for both functions. Care must be taken to clear sensitive data between uses and prevent application code from accessing cryptographic state.

Performance Benchmarking

Meaningful performance comparison of post-quantum hardware accelerators requires consistent benchmarking methodologies. Benchmarks should capture metrics relevant to target applications while enabling fair comparison across different implementations and platforms.

Throughput measurements indicate operations completed per unit time, typically expressed as operations per second for key generation, encapsulation/decapsulation, or signing/verification. Throughput benchmarks should specify input sizes, security levels, and whether pipeline filling effects are included.

Latency measurements indicate the time from operation initiation to result availability. For interactive applications, latency may be more important than throughput. Latency should be measured from input availability through output validity, including any preprocessing and postprocessing.

Area metrics express hardware resource consumption. For FPGAs, this includes lookup tables (LUTs), flip-flops, DSP blocks, and block RAM. For ASICs, gate count or silicon area indicates resource consumption. Area-time products provide efficiency metrics for comparing implementations with different resource-performance trade-offs.

Energy measurements indicate power consumption over time, critical for battery-powered and thermally constrained applications. Energy per operation enables comparison independent of clock frequency. Power gating and voltage scaling effects should be included for implementations using these techniques.

Comparability depends on shared conventions as much as on careful measurement. Community frameworks help: pqm4 provides a common harness for post-quantum benchmarks on Arm Cortex-M4 microcontrollers, and a published hardware application programming interface for post-quantum cryptography defines uniform input and output protocols so that FPGA designs from different groups can be compared on equal terms. Reports should state the target device and technology node, the clock frequency achieved after place and route rather than a synthesis estimate, the parameter set, and whether side-channel countermeasures are enabled, since masking alone can multiply both area and latency severalfold.

Summary

Hardware acceleration enables practical deployment of post-quantum cryptography by addressing the increased computational requirements of quantum-resistant algorithms. NTT accelerators provide the foundation for efficient lattice-based cryptography, with polynomial arithmetic units, matrix operations, and hash acceleration completing the implementation. FPGA and ASIC platforms offer different trade-offs between flexibility and efficiency, while instruction set extensions bring acceleration to general-purpose processors.

Constant-time implementation, power-analysis resistance, fault detection, and electromagnetic shielding must be incorporated into accelerator designs to prevent physical attacks from undermining mathematical security. Integration architectures balance performance against security in the connection to host systems. Resource-constrained implementations bring post-quantum security to embedded and IoT devices, and consistent benchmarking methodologies allow the resulting designs to be compared honestly.

The practical lesson for a hardware designer is that post-quantum acceleration is rarely limited by multipliers. Hash throughput feeds the samplers, the samplers feed the arithmetic, and the kilobyte-scale keys and signatures strain memory and interfaces. Designs that balance the hash core, the sampler, and the transform engine against one another, and that leave room for the algorithm set to change during a transition expected to run for a decade or more, will age better than those tuned narrowly to a single parameter set.

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