Electrostatic Discharge Protection
Electrostatic discharge, or ESD, is the sudden flow of current between two objects at different electrostatic potentials when they approach or touch. The potentials build up through the contact and separation of dissimilar materials, a process called triboelectric charging, and a person walking across a floor or a device sliding in a tube can accumulate thousands of volts. When that charge finds a path to a lower potential, it discharges in a few nanoseconds, delivering a current pulse that can reach several amperes. To the thin oxides and shallow junctions of modern integrated circuits, this pulse is destructive: it can puncture a gate dielectric, melt a metal interconnect, or fuse a junction in an instant.
ESD protection addresses the threat on two fronts. On-chip and board-level protection devices provide a safe discharge path that conducts the pulse harmlessly to ground or across the supply, clamping the voltage at the protected node below the level that would damage the circuit. Equally important are handling controls, the procedures and equipment that prevent damaging charge from reaching unprotected devices during manufacturing, assembly, and service. ESD is a leading cause of electronic failure, and many failures are latent: a discharge weakens a device without causing immediate malfunction, so the part passes test and fails later in the field. This article describes the standardized models that characterize ESD events, the on-chip and board-level structures that protect against them, the facility controls that prevent damage, and the standards that govern qualification and handling.
The Nature of Electrostatic Discharge
Understanding how charge accumulates and discharges clarifies why ESD is both common and damaging, and why protection must address events that span an enormous range of voltage and current rise time.
Triboelectric Charging
When two materials make and break contact, electrons transfer from one surface to the other according to their relative positions in the triboelectric series, leaving one surface positively charged and the other negatively charged. Insulating materials retain this separated charge because it cannot flow away, so synthetic clothing, plastic packaging, and untreated work surfaces readily accumulate high potentials. Low humidity worsens the problem because dry air provides no surface conduction to bleed charge away. A charged conductor, such as a person or a metal tool, stores energy that discharges abruptly when it nears a grounded or oppositely charged object.
Why Discharges Damage Devices
An ESD event is brief but intense. The discharge current rises in well under a nanosecond for some event types and peaks at amperes, while the voltage at the device terminals can momentarily reach hundreds or thousands of volts. Two failure mechanisms dominate. Thermal failure occurs when the discharge current concentrates in a small volume, raising its temperature enough to melt silicon or metal, producing junction shorts or open interconnects. Dielectric failure occurs when the voltage exceeds the breakdown strength of a thin gate oxide, puncturing it and creating a permanent leakage path. Because feature sizes and oxide thicknesses shrink with each process generation, the intrinsic ESD robustness of advanced devices tends to fall, increasing reliance on dedicated protection.
Electrostatic Discharge Models
Because real discharges vary enormously, the industry defines standardized models that represent distinct event types with specified circuit parameters and waveforms. These models underpin component qualification, letting manufacturers assign a withstand rating and compare devices on a common basis.
Human Body Model
The human body model, or HBM, represents a charged person discharging through a fingertip into a device. It is defined by a charged capacitance of 100 picofarads discharging through a series resistance of 1500 ohms, values chosen to approximate the capacitance and resistance of a human body and limb. The resulting current pulse rises in a few nanoseconds and decays over a couple of hundred nanoseconds, with a peak current of roughly two-thirds of an ampere per kilovolt of charging voltage. HBM is the most widely used qualification model, and device datasheets commonly cite an HBM withstand voltage. Industry guidance sorts parts into classes by withstand voltage so that handling requirements can be matched to a component's robustness: a common rough division places parts that withstand at least two kilovolts in the most robust group and singles out parts below a few hundred volts as the most sensitive, with finer subdivisions in between. As protection structures shrink and supply voltages fall, many high-speed and radio-frequency parts now carry HBM ratings well under one kilovolt, demanding stricter handling.
Charged Device Model
The charged device model, or CDM, represents a device that has itself become charged, for example by sliding through a shipping tube or across an automated handler, and then discharges when one of its pins contacts a grounded surface. The discharge path has very low resistance and inductance, so the CDM current rises in well under a nanosecond and peaks at several amperes, but lasts only about a nanosecond. CDM is widely considered the most representative model for failures in modern automated assembly, because machine handling charges and discharges packaged parts far more than human contact does. Its extremely fast rise time stresses the protection differently from HBM, emphasizing the speed at which a clamp turns on and the resistance and inductance of the discharge path inside the package.
Machine Model
The machine model, or MM, represents a discharge from a charged conductive object such as a piece of metallic handling equipment. It uses a charged capacitance of 200 picofarads discharging with essentially no series resistance, producing an oscillatory waveform with a higher peak current than HBM at the same voltage. The machine model originated to represent automated equipment, but because its results correlate closely with HBM and it is difficult to reproduce consistently between test systems, the industry has largely retired it in favor of HBM and CDM as the two primary qualification models.
The System-Level Model
The component models above characterize bare devices during manufacturing and handling, where the environment is controlled. A separate, more severe model characterizes a finished product in the hands of a user, where an operator may discharge directly into a connector or the chassis. This system-level model, defined by the IEC standard discussed later, specifies a faster, higher-energy pulse than the component models and is applied to the assembled product rather than to individual components. A device that passes a component HBM rating is not necessarily protected against a system-level event, so external protection at exposed ports is required for robust product immunity.
On-Chip Protection Structures
Every input, output, and supply pin of an integrated circuit includes protection structures that route an ESD pulse safely around the sensitive internal circuitry. These structures must remain transparent during normal operation yet turn on fast and conduct hard during a discharge.
The Protection Network and Clamps
A typical input pin connects to a network of diodes that steer positive transients to the positive supply rail and negative transients to ground, so the pin voltage cannot rise above the supply or fall below ground by more than a diode drop. The steered current then flows along the supply rail to a power-rail clamp, a large device placed between the supply and ground that turns on during an ESD event and shunts the current across the rails, preventing the supply itself from rising to a damaging level. This rail-based scheme means that an ESD pulse arriving at any pin finds a low-impedance path to any other pin through the steering diodes and the rail clamp.
Device Types Used On-Chip
Several device structures serve as protection elements. Diodes provide fast, well-controlled steering and are the mainstay for routing current to the rails. Grounded-gate field-effect transistors conduct through a parasitic bipolar action when the drain voltage rises, providing a compact clamp. The silicon-controlled rectifier, or SCR, offers the highest protection efficiency per unit area because, once triggered, it latches into a low-voltage, high-current conducting state, much like a crowbar, allowing it to shunt large currents with a small footprint; designers add triggering structures to fire the SCR at a controlled voltage and ensure it turns on quickly. The power-rail clamp commonly uses a large transistor switched on by a transient-detecting trigger circuit that senses the fast rising edge of an ESD event and holds the clamp on for the duration of the pulse.
The Design Window
On-chip protection must operate within a design window bounded below by the normal operating voltage and above by the breakdown voltage of the circuitry it protects. The protection must not conduct or trigger during normal operation, so its turn-on voltage sits above the maximum operating voltage. It must turn on and clamp the node below the failure threshold of the internal devices, so its clamping voltage stays under that limit. As process scaling lowers operating voltages and oxide breakdown voltages together, this window narrows, making protection design progressively more demanding and requiring careful attention to the turn-on speed, holding voltage, and current capability of each structure. Latch-up is a particular concern for SCR-based clamps, whose low holding voltage must remain above the supply so that the clamp releases after the event rather than remaining latched on the supply.
Board-Level Protection
On-chip protection alone does not guarantee system immunity, because connectors and cables expose internal nodes to severe, system-level discharges far beyond component ratings. Board-level protection devices placed at these exposed interfaces absorb the energy externally, sparing the integrated circuits behind them.
TVS Arrays for Interface Protection
A transient voltage suppressor array integrates several TVS diodes in one package, providing a fast, low-clamping discharge path for each line of a multi-pin interface such as a data port. Placed close to the connector, the array clamps an incoming discharge to a level the downstream silicon can tolerate, diverting the pulse to ground before it reaches the protected inputs. Because the array sits between the connector and the integrated circuit, board layout matters greatly: short, direct connections from the protected line to the array and from the array to ground minimize the inductance that would otherwise allow voltage to overshoot during the very fast rising edge of an ESD pulse.
Low-Capacitance Devices for High-Speed Lines
High-speed data interfaces cannot tolerate the capacitance of an ordinary clamp, which would attenuate and distort the signal. Low-capacitance ESD protection devices use a steering-diode topology in which small, fast diodes route the transient to a robust internal clamp while presenting only a fraction of a picofarad to the signal line. This preserves signal integrity on multi-gigabit interfaces while still providing a hard discharge path. Selecting a protection device for a high-speed line therefore balances clamping performance against the capacitance the line can tolerate.
Polymer and Multilayer Suppressors
Where the lowest capacitance and the smallest size are paramount, polymer ESD suppressors and multilayer varistor devices offer alternatives. A polymer suppressor places a voltage-sensitive material across a gap that remains nonconductive until an ESD voltage triggers it to conduct, then recovers; its capacitance is extremely low, suiting the fastest signal lines, though its clamping is looser than that of a diode array. These devices complement diode-based protection by addressing situations where capacitance must be minimized at the expense of a tighter clamp.
Handling Controls and the ESD-Protected Area
Even well-protected devices can be damaged during handling if charge is allowed to accumulate and discharge near them. A disciplined program of facility controls prevents damaging events by keeping personnel, tools, and surfaces at a common, controlled potential and by limiting how fast charge can move.
The ESD-Protected Area
An ESD-protected area, or EPA, is a defined workspace in which all conductive and dissipative items are bonded to a common ground point so that no significant voltage differences develop between objects that may contact a device. Within the EPA, work surfaces, flooring, seating, and equipment are made of static-dissipative materials and connected to ground through a controlled resistance. The grounding resistance is chosen to bleed charge away safely without creating a hazardous low-resistance path to personnel; dissipative rather than fully conductive materials limit the discharge current. The EPA is marked, access is controlled, and insulating materials that cannot be grounded are removed or kept away from sensitive devices.
Personnel Grounding
People are a primary source of charge, so personnel grounding is central. A wrist strap connects a seated operator to the common ground point through a current-limiting resistor, typically about one megohm, which safely bleeds charge from the body while protecting the wearer from electrical hazard. For operators who move about, ESD-controlled footwear used together with a dissipative floor provides a path to ground. Because a wrist strap can fail open without obvious symptoms, continuous monitors or regular testing verify that the strap and its connection remain intact throughout use.
Materials, Packaging, and Ionization
Devices are stored and transported in protective packaging that prevents charging and shields against external discharge. Static-shielding bags use a conductive layer that forms a barrier around the contents, while dissipative and conductive containers prevent charge accumulation during handling. For situations where insulators cannot be eliminated, such as certain plastics and process materials near the work, air ionizers neutralize the charge on those insulators by supplying balanced positive and negative ions, removing a charge source that grounding cannot address. A complete program also controls humidity where practical, since higher humidity reduces triboelectric charging.
Standards and Qualification
A framework of standards defines how components are tested for ESD robustness, how finished products are evaluated for system-level immunity, and how facilities control ESD during handling. These standards give designers, manufacturers, and customers a common language for specifying and verifying protection.
Component Qualification: JEDEC and ANSI/ESDA
Component-level ESD testing is governed by jointly developed standards from the JEDEC Solid State Technology Association and the Electrostatic Discharge Association, or ESDA. The joint standard ANSI/ESDA/JEDEC JS-001 defines the human body model test method, specifying the discharge network, waveform, pin combinations, and pass criteria used to assign an HBM withstand rating. The companion standard ANSI/ESDA/JEDEC JS-002 defines the charged device model test method, addressing the very fast discharge from a charged package; it superseded the separate earlier JEDEC and ESDA CDM methods to give a single harmonized procedure. These methods let semiconductor manufacturers qualify parts and publish withstand ratings, and they underpin the classification levels that determine how robust a device is and therefore how carefully it must be handled. The machine model, once covered by its own method, has largely been dropped from qualification because its results track HBM and proved hard to reproduce between testers, leaving HBM and CDM as the two standardized component models.
System-Level Immunity: IEC 61000-4-2
IEC 61000-4-2 is the international standard for ESD immunity of finished equipment. It defines an ESD generator, often called an ESD gun, that delivers a pulse with a sub-nanosecond rise time representing a discharge from a charged person through a handheld metal object, a waveform more severe than the component models. The standard specifies contact discharge, applied directly to conductive surfaces, and air discharge, applied by approaching the equipment with the charged electrode, along with test levels corresponding to increasing voltages. Discharges are applied to accessible points and to nearby coupling planes, and the equipment is judged against performance criteria that distinguish normal operation, recoverable disturbance, and unacceptable failure. Passing this standard demonstrates that a product tolerates the discharges a user can deliver in the field.
Facility Control: ANSI/ESD S20.20
The control of ESD in manufacturing and handling is governed by the ANSI/ESD S20.20 standard, which specifies the requirements for an ESD control program covering the design, establishment, implementation, and maintenance of an ESD-protected area. It addresses grounding and bonding systems, personnel grounding, the qualification and verification of ESD control items such as wrist straps and work surfaces, and the marking and packaging of sensitive devices. A family of supporting test methods defines how to measure the resistance and performance of these control items so that compliance can be verified objectively. Adopting a recognized control program gives manufacturers a documented, auditable basis for protecting devices throughout production.
Summary
Electrostatic discharge threatens electronics with brief, intense current pulses that puncture oxides and melt junctions, and many of the resulting failures are latent, surfacing only after a part reaches the field. The industry characterizes these events with standardized models, the human body model and the charged device model being the two primary component models, while a more severe system-level model represents discharges into a finished product. Each model emphasizes different aspects of the threat, from the moderate rise time of HBM to the sub-nanosecond edge of CDM.
Robust protection combines on-chip and board-level measures with disciplined handling. On-chip structures, steering diodes, rail clamps, and SCR-based devices, route the pulse safely around sensitive circuitry within a narrowing design window. Board-level TVS arrays and low-capacitance devices protect exposed interfaces against severe system-level discharges that exceed component ratings. Surrounding these design measures, an ESD-protected area with grounded surfaces, personnel grounding, shielding packaging, and ionization prevents damaging charge from reaching devices during manufacturing and service. Standards from JEDEC and the ESDA, the IEC, and the ANSI/ESD program define how to qualify components, verify product immunity, and control facilities, giving the whole effort a common, verifiable foundation.