Electronics Guide

Triboelectric Charging

When two materials make and break contact, electrons transfer from one surface to the other according to their relative positions in the triboelectric series, leaving one surface positively charged and the other negatively charged. Insulating materials retain this separated charge because it cannot flow away, so synthetic clothing, plastic packaging, and untreated work surfaces readily accumulate high potentials. Low humidity worsens the problem because dry air provides no surface conduction to bleed charge away. A charged conductor, such as a person or a metal tool, stores energy that discharges abruptly when it nears a grounded or oppositely charged object.

Why Discharges Damage Devices

An ESD event is brief but intense. The discharge current rises in well under a nanosecond for some event types and peaks at amperes, while the voltage at the device terminals can momentarily reach hundreds or thousands of volts. Two failure mechanisms dominate. Thermal failure occurs when the discharge current concentrates in a small volume, raising its temperature enough to melt silicon or metal, producing junction shorts or open interconnects. Dielectric failure occurs when the voltage exceeds the breakdown strength of a thin gate oxide, puncturing it and creating a permanent leakage path. Because feature sizes and oxide thicknesses shrink with each process generation, the intrinsic ESD robustness of advanced devices tends to fall, increasing reliance on dedicated protection.

Human Body Model

The human body model, or HBM, represents a charged person discharging through a fingertip into a device. It is defined by a charged capacitance of 100 picofarads discharging through a series resistance of 1500 ohms, values chosen to approximate the capacitance and resistance of a human body and limb. The resulting current pulse rises in a few nanoseconds and then decays exponentially with a time constant near 150 nanoseconds, with a peak current of roughly two-thirds of an ampere per kilovolt of charging voltage; a 2 kilovolt event therefore drives about 1.3 amperes into a shorted pin. HBM is the most widely used qualification model, and device datasheets commonly cite an HBM withstand voltage.

The joint test standard sorts parts into classes by withstand voltage so that handling requirements can be matched to a component's robustness. Class 1A spans 250 to under 500 volts, class 1B spans 500 to under 1000 volts, class 1C spans 1000 to under 2000 volts, and class 2 spans 2000 to under 4000 volts, with classes 3A and 3B covering still more robust parts above 4000 and 8000 volts. Everything below 250 volts falls into the subdivided class 0 levels, which identify the most sensitive devices and call for the strictest handling. Industry council guidance recommends that new designs target roughly 500 volts HBM, a level judged safely handled inside a compliant ESD control program. As protection structures shrink and supply voltages fall, many high-speed and radio-frequency parts now carry HBM ratings well under one kilovolt, so their handling requirements cannot be relaxed.

Charged Device Model

The charged device model, or CDM, represents a device that has itself become charged, for example by sliding through a shipping tube or across an automated handler, and then discharges when one of its pins contacts a grounded surface. The discharge path has very low resistance and inductance, so the CDM current rises in well under a nanosecond and peaks at several amperes, but lasts only about a nanosecond. CDM is widely considered the most representative model for failures in modern automated assembly, because machine handling charges and discharges packaged parts far more than human contact does. Its extremely fast rise time stresses the protection differently from HBM, emphasizing the speed at which a clamp turns on and the resistance and inductance of the discharge path inside the package.

Because the stored charge scales with the capacitance of the package itself, CDM stress depends on the physical part as much as on the silicon: a large, high pin-count package charged to a given voltage delivers far more current than a small one. The joint CDM standard classifies parts in finer steps than HBM, beginning below 125 volts and stepping through 125, 250, 500, 750, and 1000 volts, and industry guidance advises designing as close to a 250 volt CDM withstand level as performance goals allow. Because the whole event is over in about a nanosecond, CDM robustness is won largely through layout: short, low-inductance paths from every pin to the local clamp, and clamps that trigger in picoseconds rather than nanoseconds.

Machine Model

The machine model, or MM, represents a discharge from a charged conductive object such as a piece of metallic handling equipment. It uses a charged capacitance of 200 picofarads discharging with essentially no series resistance, producing an oscillatory waveform with a higher peak current than HBM at the same voltage. The machine model originated to represent automated equipment, but its results correlate closely with HBM while proving hard to reproduce: nominally compliant testers have reported failure levels differing by factors of two to five for the same part, because the waveform depends heavily on parasitic inductance in the discharge path. JEDEC and the ESD Association therefore no longer recommend qualifying products to MM, leaving HBM and CDM as the two primary component models. Legacy datasheets and older automotive or military qualification plans still cite MM ratings, so the model remains worth recognizing even though new work rarely uses it.

The System-Level Model

The component models above characterize bare devices during manufacturing and handling, where the environment is controlled. A separate, more severe model characterizes a finished product in the hands of a user, where an operator may discharge directly into a connector or the chassis. This system-level model, defined by the IEC standard discussed later, specifies a faster, higher-energy pulse than the component models and is applied to the assembled product rather than to individual components. A device that passes a component HBM rating is not necessarily protected against a system-level event, so external protection at exposed ports is required for robust product immunity.

Characterizing Protection with Transmission Line Pulsing

Pass or fail qualification tells a designer only whether a part survived; it reveals nothing about how the protection behaved. Transmission line pulsing, or TLP, fills that gap. A charged transmission line discharges a rectangular current pulse, conventionally about 100 nanoseconds long, into the device under test, and the current and voltage are sampled during the flat portion of the pulse. Stepping the amplitude upward and plotting the sampled pairs traces the current-voltage curve of the protection structure, revealing its trigger voltage, holding voltage, on-state resistance, and the current at which it fails. Very fast TLP, which uses pulses only a few nanoseconds long with picosecond rise times, probes the same structure in the CDM time domain, where turn-on delay and transient overshoot dominate. TLP is a characterization and debug tool rather than a qualification method, but it is how protection circuits are actually designed, compared, and diagnosed.

The Protection Network and Clamps

A typical input pin connects to a network of diodes that steer positive transients to the positive supply rail and negative transients to ground, so the pin voltage cannot rise above the supply or fall below ground by more than a diode drop. The steered current then flows along the supply rail to a power-rail clamp, a large device placed between the supply and ground that turns on during an ESD event and shunts the current across the rails, preventing the supply itself from rising to a damaging level. This rail-based scheme means that an ESD pulse arriving at any pin finds a low-impedance path to any other pin through the steering diodes and the rail clamp.

Device Types Used On-Chip

Several device structures serve as protection elements. Diodes provide fast, well-controlled steering and are the mainstay for routing current to the rails. Grounded-gate field-effect transistors conduct through a parasitic bipolar action when the drain voltage rises, providing a compact clamp. The silicon-controlled rectifier, or SCR, offers the highest protection efficiency per unit area because, once triggered, it latches into a low-voltage, high-current conducting state, much like a crowbar, allowing it to shunt large currents with a small footprint; designers add triggering structures to fire the SCR at a controlled voltage and ensure it turns on quickly. The power-rail clamp commonly uses a large transistor switched on by a transient-detecting trigger circuit that senses the fast rising edge of an ESD event and holds the clamp on for the duration of the pulse.

The Design Window

On-chip protection must operate within a design window bounded below by the normal operating voltage and above by the breakdown voltage of the circuitry it protects. The protection must not conduct or trigger during normal operation, so its turn-on voltage sits above the maximum operating voltage. It must turn on and clamp the node below the failure threshold of the internal devices, so its clamping voltage stays under that limit. As process scaling lowers operating voltages and oxide breakdown voltages together, this window narrows, making protection design progressively more demanding and requiring careful attention to the turn-on speed, holding voltage, and current capability of each structure. Latch-up is a particular concern for SCR-based clamps, whose low holding voltage must remain above the supply so that the clamp releases after the event rather than remaining latched on the supply.

TVS Arrays for Interface Protection

A transient voltage suppressor array integrates several TVS diodes in one package, providing a fast, low-clamping discharge path for each line of a multi-pin interface such as a data port. Placed close to the connector, the array clamps an incoming discharge to a level the downstream silicon can tolerate, diverting the pulse to ground before it reaches the protected inputs. Because the array sits between the connector and the integrated circuit, board layout matters greatly: short, direct connections from the protected line to the array and from the array to ground minimize the inductance that would otherwise allow voltage to overshoot during the very fast rising edge of an ESD pulse.

Low-Capacitance Devices for High-Speed Lines

High-speed data interfaces cannot tolerate the capacitance of an ordinary clamp, which would attenuate and distort the signal. Low-capacitance ESD protection devices use a steering-diode topology in which small, fast diodes route the transient to a robust internal clamp while presenting only a fraction of a picofarad to the signal line. This preserves signal integrity on multi-gigabit interfaces while still providing a hard discharge path. Selecting a protection device for a high-speed line therefore balances clamping performance against the capacitance the line can tolerate.

Polymer and Multilayer Suppressors

Where the lowest capacitance and the smallest size are paramount, polymer ESD suppressors and multilayer varistor devices offer alternatives. A polymer suppressor places a voltage-sensitive material across a gap that remains nonconductive until an ESD voltage triggers it to conduct, then recovers; its capacitance is extremely low, suiting the fastest signal lines, though its clamping is looser than that of a diode array. These devices complement diode-based protection by addressing situations where capacitance must be minimized at the expense of a tighter clamp.

Selecting and Placing a Protection Device

Four parameters govern the choice. The reverse standoff or working voltage must exceed the highest normal signal voltage on the line so the device stays off and does not load the signal. The clamping voltage under the specified surge current must stay below what the protected input can survive. The capacitance must be small enough not to degrade the signal, which for multi-gigabit serial links means well under a picofarad per line, while a low-speed control input can tolerate tens of picofarads. Finally, the device must be rated for the system-level pulse the port will actually see, expressed as a withstand level under the IEC contact and air discharge tests rather than as a component HBM rating.

Placement then decides whether those ratings mean anything. The protection device belongs immediately at the connector, ahead of the protected circuitry, so the diverted current never travels along a trace shared with the victim. A short, wide path to a solid ground plane matters more than the clamping voltage on the datasheet, because a nanosecond-scale edge develops substantial voltage across even a short length of trace inductance. Routing the discharge current back to the connector shell or chassis ground, rather than through the signal return, keeps the transient out of the circuit's reference. These layout choices routinely make the difference between a design that passes system-level testing and one that fails with the same components fitted.

The ESD-Protected Area

An ESD-protected area, or EPA, is a defined workspace in which all conductive and dissipative items are bonded to a common ground point so that no significant voltage differences develop between objects that may contact a device. Within the EPA, work surfaces, flooring, seating, and equipment are made of static-dissipative materials and connected to ground through a controlled resistance. The grounding resistance is chosen to bleed charge away safely without creating a hazardous low-resistance path to personnel; dissipative rather than fully conductive materials limit the discharge current. The EPA is marked, access is controlled, and insulating materials that cannot be grounded are removed or kept away from sensitive devices.

Personnel Grounding

People are a primary source of charge, so personnel grounding is central. A wrist strap connects a seated operator to the common ground point through a current-limiting resistor, typically about one megohm, which safely bleeds charge from the body while protecting the wearer from electrical hazard. For operators who move about, ESD-controlled footwear used together with a dissipative floor provides a path to ground. Because a wrist strap can fail open without obvious symptoms, its integrity must be verified rather than assumed: operators test the strap and cord at a checker before each shift, or a continuous monitor watches the connection in real time and alarms the moment it opens. Footwear and flooring systems are verified the same way, by measuring the resistance from the operator to ground and, where required, the voltage that walking actually generates on the body.

Materials, Packaging, and Ionization

Devices are stored and transported in protective packaging that prevents charging and shields against external discharge. Static-shielding bags use a conductive layer that forms a barrier around the contents, while dissipative and conductive containers prevent charge accumulation during handling. For situations where insulators cannot be eliminated, such as certain plastics and process materials near the work, air ionizers neutralize the charge on those insulators by supplying balanced positive and negative ions, removing a charge source that grounding cannot address. A complete program also controls humidity where practical, since higher humidity reduces triboelectric charging.

Component Qualification: JEDEC and ANSI/ESDA

Component-level ESD testing is governed by jointly developed standards from the JEDEC Solid State Technology Association and the Electrostatic Discharge Association, or ESDA. The joint standard ANSI/ESDA/JEDEC JS-001 defines the human body model test method, specifying the discharge network, waveform, pin combinations, and pass criteria used to assign an HBM withstand rating. The companion standard ANSI/ESDA/JEDEC JS-002 defines the charged device model test method, addressing the very fast discharge from a charged package; it superseded the separate earlier JEDEC and ESDA CDM methods to give a single harmonized procedure. These methods let semiconductor manufacturers qualify parts and publish withstand ratings, and they underpin the classification levels that determine how robust a device is and therefore how carefully it must be handled. The machine model, once covered by its own method, has largely been dropped from qualification because its results track HBM and proved hard to reproduce between testers, leaving HBM and CDM as the two standardized component models.

System-Level Immunity: IEC 61000-4-2

IEC 61000-4-2 is the international standard for ESD immunity of finished equipment. It defines an ESD generator, often called an ESD gun, built around a 150 picofarad energy-storage capacitor discharging through a 330 ohm resistor, values that represent a charged person holding a metal object. The specified waveform is far harsher than HBM. The current rises from 10 to 90 percent of its first peak in about 0.8 nanoseconds, and that first peak reaches roughly 3.75 amperes per kilovolt, more than five times the HBM peak at the same charging voltage. The standard also fixes the current still flowing at 30 and 60 nanoseconds, so the shape of the whole decay is constrained, not merely its peak.

Two application methods are defined. Contact discharge, in which the electrode touches a conductive surface before the generator fires, is the preferred method because it is reproducible. Air discharge, in which the charged electrode is brought toward the equipment until an arc forms, is used where contact cannot be made, such as through a plastic enclosure or a seam, and is inherently more variable. Four test levels apply: 2, 4, 6, and 8 kilovolts for contact discharge, and 2, 4, 8, and 15 kilovolts for air discharge, with the level chosen to match the product's expected environment.

Discharges are applied to accessible points and to horizontal and vertical coupling planes near the equipment, which stress it indirectly through the resulting field. Results are judged against performance criteria that distinguish uninterrupted normal operation, temporary degradation that recovers without intervention, degradation requiring operator action, and unacceptable damage or data loss. The second edition of 2008 governed system-level testing for many years; a third edition published in 2025 cancels and replaces it, tightening generator calibration and measurement uncertainty requirements without changing the basic waveform or test levels. A related component-level method, the human metal model, applies this same harsher waveform to individual pins so that interface parts can be rated directly against system-level stress.

Facility Control: ANSI/ESD S20.20

The control of ESD in manufacturing and handling is governed by the ANSI/ESD S20.20 standard, most recently revised in 2021, which specifies the requirements for an ESD control program covering the design, establishment, implementation, and maintenance of an ESD-protected area. Its stated scope covers parts susceptible to damage at or above 100 volts HBM and 200 volts CDM; devices more sensitive than those thresholds need additional measures beyond the baseline program. The standard requires a written program plan, a training plan, and a compliance verification plan, and it addresses grounding and bonding systems, personnel grounding, the qualification and verification of ESD control items such as wrist straps and work surfaces, and the marking and packaging of sensitive devices.

S20.20 sets requirements; a family of supporting documents defines how to meet and measure them. Product qualification standards such as ANSI/ESD S1.1 for wrist straps establish how an item is proven suitable, while technical report ESD TR53 defines the periodic compliance verification measurements that confirm installed items still perform. Companion standard ANSI/ESD S541 covers packaging materials for sensitive items. Certification to S20.20 is available through accredited third-party audit, which is why the standard appears in supplier requirements throughout the electronics industry: it gives manufacturers a documented, auditable basis for protecting devices throughout production.