Electronics Guide

Gate Charge and Peak Current

The relevant figure of merit is total gate charge, specified at a stated drain voltage, gate voltage, and drain current. It is preferred over input capacitance because the gate capacitance of a power device is strongly nonlinear, changing by an order of magnitude across the transition. Charge integrates that nonlinearity into one usable number.

Gate charge spans four orders of magnitude across the devices in common use. The EPC2218A, an 80-volt enhancement-mode gallium nitride transistor rated for 60 amperes, specifies a typical total gate charge of about ten and a half nanocoulombs; a discrete 1,200-volt silicon carbide MOSFET falls in the range of tens of nanocoulombs; a large insulated-gate bipolar transistor module rated for hundreds of amperes requires several microcoulombs. The driver that suffices for the first would take milliseconds to switch the last.

Two derived quantities follow at once. The average current needed to complete a transition in a chosen time is the gate charge divided by that time; moving three microcoulombs in one hundred nanoseconds demands thirty amperes, which is why the largest module drivers carry that rating. The average power the driver must supply is the gate charge multiplied by the gate voltage swing and by the switching frequency: one microcoulomb across a twenty-volt window at twenty kilohertz consumes 0.4 watts, which sizes the isolated bias supply.

The Gate Loop as an RC Circuit

Peak current is set not by the driver's headline rating but by Ohm's law around the gate loop. The driving voltage is the difference between the driver rail and the instantaneous gate voltage; the resistance is the sum of the driver output impedance, the external gate resistor, and the internal gate resistance built into the device. That last term is frequently dominant in large modules, where a distributed gate runner and deliberately added series resistance may total several ohms.

During the Miller plateau—the part of the transition in which the drain voltage moves and the gate voltage barely changes—the whole of the available drive current flows into the gate-to-drain capacitance. The plateau voltage is set by the device transconductance and the load current, so the current available to traverse it is the difference between the drive rail and the plateau voltage divided by the loop resistance. That current sets the rate of change of drain voltage, and it is what the designer actually controls.

Output Stage and Split Outputs

Most driver output stages are complementary push-pull structures, and most are deliberately asymmetric, with a stronger sink than source: the Texas Instruments UCC21520, an isolated dual-channel driver, specifies four amperes of peak source current and six amperes of peak sink current. Turn-off must be fast and firm; turn-on usually has to be restrained.

Many drivers bring out separate high-side and low-side output pins, described as split outputs, so that different resistors can be installed in the turn-on and turn-off paths without diodes. This is among the most useful features on a modern driver, because the optimum turn-on and turn-off resistances are almost never equal.

What Faster Switching Costs

The first cost is voltage overshoot at turn-off. The commutation loop has inductance, and interrupting current in it produces a voltage equal to that inductance multiplied by the rate of change of current. Twenty nanohenries at five thousand amperes per microsecond adds one hundred volts to the DC link. Against a 1,200-volt device on an 800-volt link that is tolerable; double the speed in a layout with sloppier decoupling and it is not.

The second cost is electromagnetic interference. Fast edges have broad spectra, and the switch-node transition drives common-mode current through every parasitic capacitance to ground—motor windings to frame, heatsink to chassis, transformer primary to secondary. Common-mode current is the dominant conducted-emission mechanism in motor drives and the usual reason a converter fails a compliance test; slowing the turn-on edge is the cheapest remedy and the first one tried.

The third cost is disturbance of the opposite device in a bridge leg. The fourth is diode reverse recovery: the turn-on speed of one device sets the rate of change of current in the opposing freewheeling diode, and the recovery current appears as extra turn-on loss and as a source of ringing. Silicon carbide Schottky diodes and gallium nitride transistors have no stored charge to recover, so they remove this penalty and tolerate faster turn-on.

Why the Two Edges Differ

Turn-on is normally the slower edge. It sets diode recovery current, produces the largest common-mode current step in most topologies, and drives the overshoot that appears across the opposing device. Turn-off is made as fast as the overshoot budget allows, because a slow turn-off wastes energy and leaves the gate near the threshold for longer, increasing exposure to false turn-on. A typical silicon carbide bridge leg therefore uses a turn-on resistance several times the turn-off resistance, which a split-output driver implements with two resistors and no diode.

The Cross-Talk Mechanism

When one device in a leg turns on, the switch node moves rapidly. The opposing device sees that motion across its gate-to-drain capacitance, and the resulting displacement current flows into its gate and out through whatever impedance the driver presents. The voltage appearing at the gate is that current multiplied by the gate-loop impedance; if it exceeds the threshold voltage, the device that was supposed to stay off begins to conduct. In the mild case this is extra loss and unexplained heating; in the severe case it is shoot-through and destruction.

Every term is moving the wrong way as device technology advances. Switch-node slew rate rises, so displacement current rises. Wide-bandgap devices have lower threshold voltages than silicon insulated-gate bipolar transistors, so less induced voltage is tolerable. And threshold voltage falls with temperature in MOSFET-like devices, so the worst case sits at the hottest operating point rather than the coldest.

Negative Off-State Bias

The standard remedy is to hold the gate below the source rather than at it, so the induced pulse has further to climb. Silicon insulated-gate bipolar transistors are commonly driven at plus fifteen volts and minus eight or minus nine. Silicon carbide MOSFETs use a smaller negative rail: Wolfspeed specifies its C3M0075120K, a 1,200-volt silicon carbide MOSFET, for static operation at plus fifteen and minus four volts, with an absolute maximum transient gate window of minus eight to plus nineteen volts. The negative rail is kept modest because excessive negative bias on a silicon carbide gate oxide accelerates threshold-voltage drift. Negative bias costs a second isolated rail, or a rail split by a Zener diode, and a little extra energy per transition.

Active Miller Clamping

Active Miller clamping attacks the impedance term instead of the voltage term. The driver provides a third output pin connected directly to the device gate, bypassing the turn-off resistor. When the gate voltage falls below a threshold on its way down, the driver closes a low-impedance switch from the gate to the negative rail and holds it there through the off interval, so displacement current flows through milliohms rather than ohms and the induced gate voltage collapses. The UCC21750 specifies a clamp threshold of two to two and a half volts above the negative rail, four amperes of clamp current, and a pull-down resistance near 0.6 ohms.

The technique is most valuable where the driver sits some distance from the die and gate-loop inductance cannot be reduced further, and it is normally used alongside negative bias rather than instead of it. A capacitor from gate to source at the device terminals divides the injected charge as well, but it slows both edges and raises the required drive current.

Silicon Carbide

The silicon carbide MOSFET has a channel mobility far below that of silicon, which forces a higher gate voltage to reach the specified on-resistance. Plus fifteen volts is a common recommendation, plus eighteen to plus twenty in some families, and on-resistance rises steeply if the actual gate voltage sags below the figure. This raises the stakes on undervoltage lockout: a device driven at thirteen volts is not off, it is a resistor several times larger than the datasheet claims, and it overheats quietly. Drivers for silicon carbide accordingly set high output-side lockout thresholds; the UCC21750 uses twelve volts.

The usable gate window is simultaneously narrower. The oxide is grown on a defect-rich interface, and both positive and negative bias stress produce threshold drift that must be bounded by staying inside the manufacturer's window. The window quoted above for the C3M0075120K—minus eight to plus nineteen volts transient against minus four to plus fifteen for operation—leaves only a few volts of ringing margin, so gate-loop inductance harmless on a silicon device can push a silicon carbide gate outside its rating.

Threshold voltage is low, typically a few volts and falling with temperature, so cross-talk immunity is worse than silicon. Short-circuit withstand time is typically two to five microseconds against roughly ten for a silicon insulated-gate bipolar transistor, so protection must act faster.

Gallium Nitride

Enhancement-mode gallium nitride transistors invert several of these rules and are unforgiving in their own way. Their gate is not an oxide but a Schottky or p-type structure that conducts if driven too positive, and the absolute maximum sits close to the recommended drive. The EPC2218A carries a maximum gate-to-source rating of plus six and minus four volts with a recommended drive of five to five and a quarter volts, leaving roughly one volt of ringing margin across the entire gate loop.

Negative off-state bias, the standard remedy elsewhere, is usually avoided here. These devices have no body diode; they conduct in reverse through the channel, and the drop in that mode rises roughly one for one with the magnitude of the negative gate bias, so minus five volts during dead time adds five volts to the reverse conduction drop and can cost more than the switching improvement saves. Manufacturers recommend zero volts for the off state and rely on tight layout and short dead times instead; EPC recommends no more than about thirty nanoseconds of half-bridge dead time for the part cited above.

Cascode gallium nitride devices, which stack a depletion-mode gallium nitride transistor with a low-voltage silicon MOSFET inside one package, sidestep the gate-window problem entirely, because the driver sees an ordinary silicon MOSFET gate. The cost is an extra device in the conduction path and less direct control over the transition.

Common-Source Inductance

The most damaging parasitic is inductance shared between the power loop and the gate loop. In a three-terminal package, the source or emitter lead carries both the load current and the gate return current. Load current changing at a high rate develops a voltage across that shared inductance, and because the driver references its output to the far end of the lead, that voltage subtracts directly from the gate-to-source voltage the die actually sees.

The effect is negative feedback that opposes the transition in progress: during turn-on, rising load current develops a voltage that reduces the effective drive, slowing the edge and raising the loss, and during turn-off the mechanism runs in reverse. Ten nanohenries of shared inductance with a current slope of two thousand amperes per microsecond produces twenty volts of opposing signal, which exceeds the entire gate drive.

Kelvin-Source and Auxiliary-Emitter Connections

The remedy is to give the gate loop its own return path to the die, carrying no load current. In discrete packages this appears as a fourth terminal, as in the four-lead TO-247 variants used for fast silicon carbide MOSFETs. In modules it is the auxiliary emitter or auxiliary source terminal, provided alongside the gate terminal precisely so the driver can reference itself to the die rather than to the power terminal. Using the power terminal as the driver reference when a Kelvin connection exists is among the most common and most consequential errors in power electronics layout.

The Kelvin connection must be treated as part of a loop rather than as a convenience. Route it alongside the gate trace as a tight pair, so the gate loop encloses minimal area. Splitting the pair, or returning the gate through a ground plane shared with power current, reintroduces the problem the fourth terminal was added to solve.

Damping, Decoupling, and Measurement

The remaining gate-loop inductance forms a resonant circuit with the device input capacitance. Below the critical damping value the gate rings, and the ringing can exceed the gate rating or retrigger the device. The external gate resistor is therefore doing two jobs, setting the switching speed and damping the resonance; where the two conflict, a small ferrite bead in the gate lead provides loss at the resonant frequency without slowing the transition.

Practical rules follow directly. Place the driver as close to the device as thermal and creepage constraints permit, and its decoupling capacitors immediately at its supply pins, because the peak gate current comes from those capacitors and not from the bias supply. Keep the gate loop out of the plane of the power commutation loop, and never run a gate trace alongside the switch node.

Bootstrap Supplies

The bootstrap circuit is the cheapest solution and consists of one diode and one capacitor. The capacitor connects between the high-side driver's supply pin and the switch node; the diode connects from the low-voltage supply to that capacitor. When the low-side device conducts, the switch node is pulled to the negative rail, the diode conducts, and the capacitor charges to roughly the supply voltage less a diode drop. When the high-side device turns on and the switch node rises, the diode blocks and the capacitor supplies the high-side driver while floating at whatever potential the node reaches.

Sizing the capacitor is a charge-balance calculation. It must supply the high-side gate charge, the driver's quiescent current, the bootstrap diode's reverse leakage, and any level-shifter current for the longest interval in which the low-side device does not conduct, while drooping no further than the undervoltage lockout threshold.

The Limits of Bootstrapping

Four limits are worth stating explicitly, because each has ended a design that began with a bootstrap. The first is duty cycle: the capacitor refreshes only while the low-side device conducts, so one hundred percent duty cycle is impossible and DC operation—holding the high-side device on indefinitely, as a motor drive does at zero speed under load—is impossible. Practical designs cap the high-side duty cycle below unity or insert forced refresh pulses, which introduce their own ripple.

The second is startup: the capacitor is discharged at power-up and the high-side driver cannot operate until the low-side device has switched once, so controllers must pre-charge the rail. The third is the negative excursion of the switch node during dead time, when load current commutates into the low-side diode and parasitic inductance drives the node below the negative rail. Because the capacitor's negative plate ties to that node, the excursion reaches the driver's floating supply pins and can violate their absolute maximum ratings. The fourth is that a bootstrap rail cannot easily produce negative off-state bias, because it is defined relative to the source terminal itself.

Charge Pumps

A charge pump generates a supply above the positive rail by switching capacitors against an independent oscillator rather than against the power stage. Because that oscillator runs whatever the power stage does, a charge pump sustains one hundred percent duty cycle and true DC operation, exactly the case a bootstrap cannot serve. The cost is current capability: charge pumps deliver milliamperes, so they suit load switches and small motor drivers rather than hard-switched bridges.

Isolated Bias Supplies

High-power and high-voltage designs give each floating driver its own galvanically isolated supply, usually a small transformer driven by a push-pull or flyback stage with a rectifier and regulator on each secondary.

The parameter that matters most is not efficiency or regulation but the transformer's interwinding capacitance, the path by which the switch-node transient couples common-mode current into the control side. It must be held to a few picofarads, which requires physical separation of the windings, electrostatic shielding, and often a construction chosen for low coupling capacitance rather than for size. A supply with tens of picofarads of interwinding capacitance injects enough current into the control ground to corrupt logic and analog measurements throughout the converter, however good the signal-path isolator may be.

Optocouplers

An optocoupler transmits the signal as light across a transparent insulating gap between a light-emitting diode and a photodetector. Its weaknesses matter in fast converters: the light-emitting diode degrades with time and temperature, so the current transfer ratio falls over the product's life and must be derated at design time; propagation delay is long and varies with temperature and part-to-part, which forces larger dead time; and the geometry places conductive lead frames on both sides of a short gap, which limits rejection of a rapidly changing barrier potential.

Magnetic and Capacitive Coupling

Magnetic isolators encode the signal as pulses through a pair of on-chip planar coils separated by a thick polymer dielectric. There is no wear-out mechanism analogous to light-emitting diode degradation, propagation delay is short and consistent, and supply current is far below that of an optocoupler. Because the barrier is capacitively symmetric, a common-mode step tends to affect both ends of the receiving coil equally and is rejected differentially.

Capacitive isolators encode the signal as a modulated carrier across series capacitors built from thin-film silicon dioxide grown on the die. Silicon dioxide has an exceptionally high dielectric strength, so the barrier can be thin and the residual isolation capacitance small, which favors common-mode rejection. Modern capacitive isolators achieve the highest transient-immunity figures in the market, and makers of both magnetic and capacitive parts now publish barrier lifetime projections; Texas Instruments states a barrier life longer than forty years for the silicon dioxide barrier in the UCC21750.

Fiber Optics

At the highest voltages—medium-voltage drives, high-voltage direct-current valves, series stacks at tens or hundreds of kilovolts—no monolithic isolator provides sufficient standoff, and the gate command travels over optical fiber. Fiber offers effectively unlimited isolation voltage and immunity to the transients such equipment produces, at the cost of a transmitter, a receiver, connectors, and added delay. It carries no power, so each gate unit still needs a local supply.

Desaturation Detection and Blanking

Desaturation detection infers a fault from the device's own on-state voltage. When the gate is commanded on, a high-voltage diode connects a sensing pin to the device's drain or collector, and a small current source charges an external capacitor. If the device is properly conducting, its on-state voltage is a volt or two and the diode holds the sensing node near that value; if the device is carrying fault current it leaves saturation, the terminal voltage rises, the diode stops conducting, the capacitor charges freely, and the node crosses a threshold. The UCC21750 uses a typical threshold of nine volts with a nominal five hundred microampere charging current.

Blanking is essential and is the hardest part to get right. Immediately after turn-on the device has not yet reached its on-state voltage, so the comparator would trip every cycle if enabled at once. Drivers therefore impose a leading-edge blanking interval, part fixed inside the device and part set by the external capacitor; the UCC21750 applies two hundred nanoseconds internally before enabling the current source. The interval must be long enough to cover the worst-case turn-on at the lowest temperature and the highest current, and short enough that detection plus shutdown fits inside the device's short-circuit withstand time.

This is why porting a design from silicon to silicon carbide so often breaks the protection: withstand time falls from roughly ten microseconds to two to five, while the required blanking does not shrink proportionally. A silicon carbide device also leaves saturation more gradually, so the threshold must distinguish a genuine fault from a heavy but legitimate load. Desaturation is not the only option; the UCC5870-Q1 also offers shunt-based overcurrent and thermistor-based overtemperature detection as configurable protections.

Soft Shutdown and Two-Level Turn-Off

Once a short circuit is detected, the device must be turned off, but not at the speed used for normal switching. Fault current is many times the rated current, and interrupting it through the normal turn-off resistor would develop a voltage across the commutation-loop inductance far beyond the device rating, destroying by overvoltage the device the protection was meant to save.

Soft shutdown discharges the gate through a deliberately weak path; the UCC21750 provides four hundred milliamperes for this against ten amperes for normal turn-off. A slower shutdown limits overshoot but leaves the device dissipating fault energy for longer. Two-level turn-off refines the idea: the gate is first pulled to an intermediate voltage, low enough to cut the fault current but high enough to keep conduction controlled, held there for a programmed interval, and only then pulled fully off. Because that level and dwell time depend on the device and the loop inductance, the feature appears mainly on programmable drivers such as the UCC5870-Q1.

Undervoltage Lockout and Active Clamping

Undervoltage lockout holds the output off until the driver's rails are high enough to drive the device fully on. The output-side threshold is chosen for the device family, which is why vendors offer the same part with several options—the UCC21520 is supplied with five-volt and eight-volt thresholds.

Active clamping addresses overvoltage from any cause rather than only from a fault shutdown. A chain of transient-voltage-suppressor diodes runs from the device's drain or collector back to its gate; if the terminal voltage exceeds the chain's breakdown, current flows into the gate and partially turns the device back on, reducing the rate of change of current and therefore the inductive overshoot. The device dissipates the excess energy in its own channel rather than letting it appear as a destructive voltage. The technique is standard in high-power module drives.

Where Dead Time Comes From

Dead time is generated at three places. Motor-control and digital-power microcontrollers include dead-time insertion in the pulse-width-modulation peripheral, applied in hardware to complementary output pairs with a programmable count. Many gate drivers generate it locally, from a resistor or capacitor on a dedicated pin or from a programmed register; the UCC21520 provides a programmable dead-time pin and an interlock that prevents both outputs from being high at once regardless of the inputs. A third option is to generate it in software, which is the least reliable because it depends on interrupt latency.

Robust designs use two mechanisms rather than one: the controller inserts the nominal dead time and the driver enforces a hardware interlock as a backstop, because a controller fault or a corrupted register can produce overlapping commands and the driver is the last circuit that can refuse them. The UCC5870-Q1 adds a programmable minimum-pulse rejection filter, which discards command pulses too short to be genuine.

Sizing Dead Time

The required dead time is the worst-case turn-off delay of the outgoing device, minus the best-case turn-on delay of the incoming device, plus the worst-case propagation-delay mismatch between channels, plus margin—each term taken across temperature, supply range, and the part-to-part distribution. The distribution usually dominates, which is the practical reason isolator technology affects system performance: a driver with a thirty-three-nanosecond typical delay and tightly specified skew permits a much shorter dead time than an optocoupler whose delay varies by hundreds of nanoseconds across temperature.

Devices differ sharply. Large insulated-gate bipolar transistor modules, with long tail currents, may require one to three microseconds. Silicon carbide bridges typically use one hundred to five hundred nanoseconds. Gallium nitride half-bridges use tens of nanoseconds, with EPC recommending no more than about thirty for its 80-volt part.

What Dead Time Costs

During dead time the load current flows through the body diode of a MOSFET, the antiparallel diode of an insulated-gate bipolar transistor module, or the reverse channel of a gallium nitride transistor. Each has a higher forward drop than the channel, so dead time is a direct conduction loss. The penalty is severe for silicon carbide, whose body diode drops several volts, which is why silicon carbide drives use synchronous rectification with the shortest defensible dead time.

Dead time also distorts the output voltage. Because the conducting device during the dead interval is set by the direction of load current rather than by the command, the average output departs from the commanded value in proportion to the dead time and the switching frequency, with a sign that flips with current direction. In motor drives this produces low-order harmonics, torque ripple, and distortion near current zero crossings, corrected imperfectly by dead-time compensation in the modulator.

Parallel Devices

Paralleled devices share static current reasonably well when on-resistance has a positive temperature coefficient, as it does in MOSFETs and wide-bandgap devices: a device carrying more current heats, becomes more resistive, and sheds current to its neighbors. Dynamic sharing during the transition is harder and is a gate-drive problem. Threshold differences of a few hundred millivolts, or gate-loop delay differences of a few nanoseconds, cause one device to turn on first and carry the entire commutation current for that interval.

The countermeasures are individual gate resistors for each device rather than one shared resistor, symmetric routing so every device sees the same gate-loop impedance and power-loop inductance, and in demanding cases devices screened for threshold voltage. Individual resistors serve a second purpose: the paralleled input capacitances and the interconnect between the gates form a resonant network that can oscillate at very high frequency, and the per-device resistor damps it, with a ferrite bead added where the resistor alone is insufficient.

Series Devices and Multilevel Stacks

Series connection extends blocking voltage beyond what a single device provides and requires division of the voltage both statically and dynamically. Static division uses a resistor across each device, sized so its current dominates the worst-case leakage spread. Dynamic division is a gate-drive problem: the device that turns off first takes the whole voltage, and if the imbalance is large enough it fails, after which the survivors take more. Three techniques are used together—snubber capacitors across each device, active clamping through a transient-voltage-suppressor chain to the gate, and active gate control that adjusts turn-off timing from measured voltage division. All require tightly matched command delay, which is why series stacks distribute commands over fiber of identical length.

Multilevel topologies present a related burden: every switch sits at a different potential and needs its own floating supply and isolated command path. In a neutral-point-clamped three-level leg the four switches occupy four reference potentials, and each driver's isolation requirement depends on its position. Isolation must therefore be specified per position rather than once for the converter.

Configurable Drivers

A programmable gate driver exposes its parameters through a serial interface rather than through passive components. The UCC5870-Q1, an isolated single-channel driver for silicon carbide and insulated-gate bipolar transistors in electric-vehicle traction inverters, is representative. Texas Instruments specifies thirty amperes of peak source and sink current, gate drive strength adjustable during operation, configurable protection, programmable soft turn-off and two-level turn-off responses, an integrated four-ampere active Miller clamp, and reconfiguration, verification, supervision, and diagnosis over a serial peripheral interface. An integrated ten-bit analog-to-digital converter reports device temperature, voltage, and current back across the barrier.

The diagnostic content matters as much as the configurability. That part includes built-in self test of the protection comparators, verification of the signal path from input to transistor gate, monitoring of the transistor threshold, and internal clock monitoring, with separate fault and warning outputs. Texas Instruments states that documentation is available to support system design to ISO 26262 up to ASIL D, and the part is qualified to AEC-Q100 temperature grade 0. In a traction inverter the gate driver is a safety-relevant element, and proving that its protection still works is a requirement rather than a convenience.

Active Gate Control and Slew-Rate Profiling

Adjustable drive strength opens a design space a fixed resistor cannot reach. Because the trade between switching loss and slew rate binds only at the worst-case operating point, a driver that can change strength during operation can be aggressive where conditions permit and conservative where they do not: weaker at high load current, where overshoot is worst, stronger at light load, where switching loss dominates efficiency, and different for the two edges within one cycle.

Slew-rate profiling goes further, shaping the gate current within a single transition, on the rationale that the interval which sets diode recovery current is not the interval which sets voltage overshoot. Such multi-stage schemes apply a strong current to cross the sub-threshold region, a reduced current through the interval that sets the rate of change of current, and a strong current again to finish. Published research reports an improved loss-versus-overshoot trade against a single resistor, but commercial adoption remains limited, because the benefit must be weighed against added cost and the difficulty of validating a driver whose behavior depends on state.

The Component Standards

Two standards define the safety ratings of isolator components, split by technology. IEC 60747-5-5 covers photocouplers—optocouplers—specifying their terminology, ratings, characteristics, and safety test methods; it was first published in 2007 and reached a second edition in 2020. IEC 60747-17, first published in September 2020, does the same for magnetic and capacitive couplers and superseded the earlier publicly available specification IEC PAS 60747-17 of 2011. The German adoption of the latter is designated VDE 0884-17, and datasheets commonly cite the pair together as DIN EN IEC 60747-17 (VDE 0884-17). Separately, UL 1577 defines the North American component-recognition withstand test, in which the barrier holds a stated root-mean-square voltage for one minute.

These standards define parameters that answer different questions. The UL 1577 withstand rating is a one-minute proof test, not a continuous rating; the UCC21520 is rated at 5.7 kilovolts root mean square on it. The maximum repetitive peak isolation voltage is the level the barrier may see continuously in service and is far lower; the UCC21750 supports a working voltage of 1.5 kilovolts root mean square. The transient isolation voltage is a short-duration rating, quoted for the UCC21520 as 8,000 volts peak for reinforced insulation under IEC 60747-17. Surge immunity is tested with a standard impulse waveform, quoted by Texas Instruments as 12.8 kilovolts peak for the UCC21750.

Reinforced insulation—a single barrier qualified to the level of two independent basic barriers—is required wherever the isolation protects a person rather than merely separating two circuits, and qualifying for it involves partial-discharge and accelerated life testing of the barrier.

Creepage, Clearance, and the End Product

Component certification is necessary but not sufficient. Physical spacing across the package and across the printed circuit board must also satisfy the end-product standard, which depends on working voltage, pollution degree, the material group of the substrate, altitude, and overvoltage category. IEC 60664-1 provides the underlying insulation-coordination rules, and product standards apply them within their scopes: IEC 62368-1 for information and communication technology equipment, IEC 61800-5-1 for adjustable-speed drive systems, IEC 60601-1 for medical equipment.

These requirements shape the package. The UCC21750 ships in a wide-body sixteen-lead small-outline package with creepage and clearance distances greater than eight millimeters, a choice made for the safety requirement rather than for board area. On the board, the barrier region must be kept clear of copper, vias, and silkscreen, and slots are routinely milled through the substrate to extend the creepage path. Beyond the barrier the driver inherits the qualification regime of its equipment: AEC-Q100 and ISO 26262 evidence in automotive designs, IEC 61800-5-1 and IEC 61800-3 in industrial drives.