Electronics Guide

Fundamentals of Homomorphic Encryption

Homomorphic encryption schemes allow mathematical operations to be performed on ciphertexts such that the result, when decrypted, matches the outcome of corresponding operations on the plaintexts. This property, called homomorphism, enables a party without access to the secret key to perform useful computations while learning nothing about the data being processed. The encrypted inputs and outputs appear as random noise to anyone without the decryption key.

The concept traces back to early observations that certain encryption schemes preserved some algebraic structure. The RSA cryptosystem, for instance, is multiplicatively homomorphic: encrypting two numbers and multiplying their ciphertexts yields an encryption of their product. The Paillier cryptosystem is additively homomorphic, allowing encrypted values to be summed. However, these partial homomorphisms could not support arbitrary computation combining both operations.

The breakthrough came in 2009 when Craig Gentry demonstrated the first fully homomorphic encryption (FHE) scheme, capable of evaluating arbitrary computations on encrypted data. His construction, based on ideal lattices, began with a somewhat homomorphic scheme, then "squashed" its decryption procedure into a low-degree circuit that the scheme itself could evaluate, and finally applied a bootstrapping transformation to refresh ciphertexts indefinitely. This achievement represented the culmination of decades of cryptographic research and opened entirely new possibilities for secure computation. Subsequent developments have dramatically improved efficiency, though significant computational overhead remains compared to plaintext operations.

Modern homomorphic encryption schemes typically operate on large mathematical structures, with ciphertexts consisting of high-degree polynomials with coefficients that may be thousands of bits wide. Operations on these structures involve polynomial arithmetic, modular reductions, and other computationally intensive procedures. The sheer size of the operands and the complexity of the operations create the performance challenges that hardware acceleration addresses.

Fully Homomorphic Encryption

Fully homomorphic encryption enables arbitrary computations on encrypted data by supporting both addition and multiplication operations, which together form a complete basis for computation. Any function expressible as a circuit of addition and multiplication gates can be evaluated homomorphically, allowing encrypted data to be processed through arbitrarily complex algorithms without decryption.

The mathematical foundation of modern FHE schemes typically relies on the hardness of lattice problems, particularly the Learning With Errors (LWE) problem and its ring variant (RLWE). These problems are believed to be computationally intractable even for quantum computers, providing security guarantees that may survive the advent of large-scale quantum computing. The lattice-based construction also provides the algebraic structure necessary for homomorphic operations.

In RLWE-based schemes, messages are encoded as polynomials over specific rings. Ciphertexts live in quotient rings of the form Z_q[X]/(X^n + 1), where n is a power of two and q is the ciphertext modulus; the cyclotomic polynomial X^n + 1 is chosen because it makes reduction after multiplication a matter of negating and folding coefficients rather than performing a general polynomial division. Encryption adds carefully structured noise to these polynomial representations, and the security relies on the difficulty of distinguishing these noisy encodings from random elements. The homomorphic operations preserve the message while accumulating noise, creating the central challenge of noise management.

The noise accumulation problem fundamentally limits the depth of computation possible with basic homomorphic operations. Each operation increases the noise level in the ciphertext, and if noise grows too large, decryption fails. The technique of bootstrapping, Gentry's key insight, allows noise to be reduced by homomorphically evaluating the decryption circuit itself, essentially refreshing the ciphertext while maintaining encryption. This operation enables unlimited computation depth but at significant computational cost.

Somewhat Homomorphic Encryption Schemes

Somewhat homomorphic encryption (SHE) schemes support a limited number of operations before noise accumulation prevents further computation. While less powerful than fully homomorphic schemes, SHE provides substantially better performance for applications whose computational requirements fit within the noise budget. Many practical applications can be expressed within these constraints, making SHE an important practical tool.

The BFV (Brakerski/Fan-Vercauteren) scheme represents one of the most widely implemented SHE approaches. It encodes integers modulo a plaintext modulus t and scales them into the ciphertext space, supporting both addition and multiplication with well-characterized noise growth. Because the message occupies the high-order bits of the coefficients and the noise the low-order bits, BFV arithmetic is exact: as long as the noise budget holds, decryption returns the mathematically correct integer result. Library implementations expose parameter selection helpers that let users configure security levels and noise budgets for specific applications, trading off security margin, ciphertext size, and computational capacity.

The CKKS (Cheon-Kim-Kim-Song) scheme, also known as the approximate homomorphic encryption scheme, takes a different approach by treating noise as an acceptable approximation error rather than something to be eliminated. This perspective makes CKKS particularly well-suited for machine learning and other applications that inherently tolerate some numerical imprecision. The scheme supports efficient operations on vectors of real or complex numbers, enabling SIMD-style parallel computation on encrypted data.

The BGV (Brakerski-Gentry-Vaikuntanathan) scheme introduced the modulus switching technique that reduces noise by scaling down the ciphertext modulus after operations. This approach enables deeper computations within the somewhat homomorphic framework by managing noise growth more effectively. BGV remains influential in both theoretical development and practical implementations, with its modulus switching concept adapted by many subsequent schemes.

Choosing among SHE schemes involves understanding the specific requirements of the target application. BFV excels for exact integer arithmetic, making it suitable for applications like private set intersection or encrypted database queries. CKKS provides efficient approximate arithmetic for machine learning inference, signal processing, and scientific computing. BGV offers flexibility in parameter selection for applications requiring careful noise budget management. Hardware implementations often support multiple schemes to address diverse application requirements.

Hardware Accelerator Architectures

Hardware accelerators for homomorphic encryption address the computational bottlenecks that limit software implementations. The core operations in HE computation, primarily polynomial arithmetic and number theoretic transforms, map well to parallel hardware architectures. Purpose-built accelerators can achieve performance improvements of several orders of magnitude compared to software execution on general-purpose processors.

FPGA-based accelerators provide a flexible platform for HE acceleration, enabling rapid prototyping and customization for specific schemes and parameter sets. The reconfigurable fabric of FPGAs allows designers to implement precisely the arithmetic units and memory structures required for particular HE workloads. Many research implementations use FPGAs to explore architectural trade-offs before committing to fixed ASIC designs.

ASIC implementations offer the highest performance and energy efficiency for HE acceleration. By designing circuits specifically for HE operations, ASICs eliminate the overhead of programmable logic while enabling aggressive optimization of critical paths. Several companies and research groups have developed or announced ASIC accelerators targeting specific HE schemes, and academic design studies for architectures such as BTS, CraterLake, and ARK project throughput improvements on the order of thousands to tens of thousands of times over CPU software baselines. These figures come from simulation and physical-design estimation rather than from measurements on fabricated parts, so they are best read as architectural projections. The U.S. Defense Advanced Research Projects Agency framed the objective differently in its Data Protection in Virtual Environments (DPRIVE) program, announced in March 2021: rather than name a speedup multiple, DPRIVE set the goal of performing computation on FHE-encrypted data within one order of magnitude, roughly a factor of ten, of the time required for the equivalent computation on unencrypted data.

GPU acceleration represents an intermediate approach, leveraging the massive parallelism of graphics processors for HE computation. The SIMD architecture of GPUs maps naturally to the polynomial operations central to HE, and the existing ecosystem of GPU computing tools simplifies development. While GPUs cannot match the efficiency of purpose-built accelerators, their availability and programmability make them practical for many applications.

Memory bandwidth often emerges as the critical bottleneck in HE accelerator design. The large ciphertext sizes in HE, often measured in megabytes, stress memory systems designed for much smaller data structures, and the evaluation keys consumed by key switching are larger still. Proposed data center accelerators respond by pairing an unusually large on-chip scratchpad, tens to hundreds of megabytes of SRAM, with high-bandwidth memory stacks, so that working sets stay resident across long operation sequences. Effective architectures also minimize data movement through streaming computation that processes ciphertexts without materializing them in full, fused operator pipelines that avoid round trips to memory between stages, and careful scheduling to maximize memory access efficiency. Arithmetic throughput alone rarely determines performance; the ratio of on-chip storage to compute usually does.

Polynomial Arithmetic Units

Polynomial arithmetic forms the computational foundation of lattice-based homomorphic encryption. Addition of polynomials requires coefficient-wise addition modulo some integer, a relatively simple operation that parallelizes trivially. Multiplication of polynomials, however, involves computing the product of all coefficient pairs and combining them appropriately, a process that scales quadratically with polynomial degree if performed naively.

The Number Theoretic Transform (NTT) provides the key to efficient polynomial multiplication, analogous to how the Fast Fourier Transform enables efficient convolution of signals. NTT converts polynomials from coefficient representation to evaluation representation, where multiplication becomes element-wise rather than requiring the full convolution. The transform and its inverse each require O(n log n) operations for degree-n polynomials, enabling multiplication in O(n log n) rather than O(n^2) time.

Hardware implementations of NTT exploit the regular butterfly structure of the transform algorithm. The computation consists of log n stages, each containing n/2 butterfly operations that combine pairs of elements using addition, subtraction, and multiplication by precomputed twiddle factors. Pipelined implementations can achieve high throughput by processing multiple stages simultaneously, while parallel implementations perform multiple butterflies concurrently within each stage.

The modular arithmetic required by NTT poses additional implementation challenges. Coefficient values and twiddle factors are large integers, often 50-60 bits or more, requiring wide arithmetic units. The modular reduction after each multiplication must be efficient to avoid becoming a bottleneck. Barrett reduction and Montgomery reduction provide algorithmic approaches that replace expensive division with multiplication and shifting, and hardware implementations often use specialized reduction circuits optimized for specific moduli.

Residue Number System (RNS) representation offers another approach to managing large coefficient arithmetic. By decomposing large integers into residues modulo several smaller coprime moduli, RNS enables parallel computation on smaller values. HE accelerators often combine RNS representation with NTT, performing transforms independently for each residue channel and combining results only when necessary. This approach reduces the width of individual arithmetic units while maintaining the ability to represent large values.

Bootstrapping Acceleration

Bootstrapping, the operation that refreshes ciphertexts by homomorphically evaluating the decryption circuit, is the most computationally expensive operation in fully homomorphic encryption. A single bootstrapping operation can require billions of elementary operations and consume the majority of computation time in FHE applications. Hardware acceleration of bootstrapping is therefore essential for practical FHE deployment.

The bootstrapping procedure involves several stages, each with distinct computational characteristics. The initial step typically raises the ciphertext to a higher modulus to provide room for the noise introduced by the subsequent homomorphic computation. The core of bootstrapping then evaluates a polynomial approximation of the decryption function, followed by operations that extract and refresh the encrypted message. Each stage presents opportunities for hardware optimization.

Key switching, a component of bootstrapping that changes the encryption key associated with a ciphertext, involves substantial polynomial arithmetic. The operation decomposes the ciphertext into digits, multiplies them by elements of an evaluation key, and sums the results. Hardware accelerators for key switching focus on efficient implementation of this multiply-accumulate pattern, often using specialized memory organization to stream evaluation key elements with minimal latency. Key switching is not confined to bootstrapping. Relinearization, the special case applied after every homomorphic multiplication to collapse the enlarged three-component ciphertext back to its canonical two-component form, and the rotations that move data between the slots of a packed ciphertext both reduce to key switching. In practical CKKS and BFV workloads these operations dominate the instruction mix, which is why accelerator designs are frequently organized around key-switching throughput rather than around raw multiplication rate.

Modulus switching, another bootstrapping component, reduces the ciphertext modulus to control noise growth. The operation involves scaling polynomial coefficients and rounding to the new modulus, operations that interact carefully with the RNS representation typically used in implementations. Efficient hardware for modulus switching must handle the base conversion between different RNS decompositions while maintaining throughput.

Recent advances in bootstrapping algorithms have dramatically reduced its computational requirements. The FHEW and TFHE schemes, known in the standardization literature by their authors' initials as DM and CGGI, enable gate bootstrapping in milliseconds rather than minutes; reported single-core figures fall to roughly ten milliseconds, making FHE practical for interactive applications. These schemes build on the GSW construction and torus-based cryptography to refresh noise more efficiently per operation. A distinctive capability is programmable bootstrapping, in which the refresh step simultaneously evaluates an arbitrary lookup-table function on the encrypted value at no additional cost, turning the most expensive operation into a vehicle for nonlinear computation such as an activation function or a comparison.

The two bootstrapping styles pull hardware in opposite directions, and this split is the single most consequential architectural choice in HE accelerator design. The DM and CGGI family bootstraps a single low-precision ciphertext at low latency, so its accelerators favor small, deeply pipelined transform units, fast access to a large bootstrapping key, and efficient lookup-table evaluation. The BGV, BFV, and CKKS family bootstraps thousands of packed slots at once in an expensive amortized operation, so its accelerators favor wide datapaths, very large on-chip scratchpads, and high key-switching throughput. Designs that aim to serve both families must either provide two datapaths or accept a compromise, which is one motivation for the scheme-switching techniques that convert ciphertexts between the families so that each part of a computation runs under the representation that suits it.

Noise Management

Noise management represents the central engineering challenge in homomorphic encryption systems. Every homomorphic operation increases the noise in ciphertexts, and if noise exceeds the threshold that the scheme can tolerate, decryption produces incorrect results. Effective noise management requires understanding noise growth characteristics, selecting parameters that provide adequate noise budget, and scheduling operations to minimize noise accumulation.

Different homomorphic operations contribute noise differently. Addition typically increases noise additively and by relatively small amounts, while multiplication causes more dramatic noise growth. In most schemes, multiplication roughly squares the noise level, making multiplication depth the primary constraint on computation. Careful algorithm design that minimizes multiplicative depth can dramatically extend the computation possible within a given noise budget.

Hardware support for noise management includes mechanisms for tracking noise levels throughout computation. Some accelerators implement noise estimation units that monitor ciphertext noise without performing full decryption, enabling dynamic decisions about when refreshing operations are necessary. This capability allows systems to defer expensive bootstrapping operations until actually required, improving average-case performance.

Rescaling operations in the CKKS scheme provide a mechanism for controlling noise growth after multiplication. By scaling down the ciphertext modulus proportionally to the scale of the multiplication result, rescaling prevents noise from accumulating as rapidly as it would otherwise. Hardware implementations must perform rescaling efficiently, as it is required after essentially every multiplication in CKKS computation.

The interaction between noise management and parallelism creates interesting optimization challenges. Operations that could execute in parallel may have different effects on noise levels, and the order of operations can affect total noise accumulation. Sophisticated schedulers, potentially implemented in hardware, can optimize operation ordering to minimize noise while maximizing throughput, balancing these competing concerns for specific workloads.

Noise carries a security dimension as well as a correctness one. Li and Micciancio showed in 2021 that approximate schemes such as CKKS, although secure in the standard IND-CPA sense, leak information about the secret key through the residual approximation error in decrypted results, and are therefore broken under the stronger IND-CPA-D notion, which grants an adversary a decryption oracle for honestly evaluated ciphertexts. The accepted countermeasure is noise flooding: adding Gaussian noise of sufficient variance to a result before releasing it, so that what remains no longer depends on the secret. Later work demonstrated key-recovery attacks against implementations whose flooding parameters were derived from average-case rather than worst-case noise bounds, and mainstream libraries now derive those parameters conservatively. For hardware, the consequence is concrete: a decryption path that emits results to a relying party needs a well-specified noise source and correct flooding parameters, and the security of an approximate scheme cannot be treated as a purely software-side concern.

Parameter Selection

Parameter selection in homomorphic encryption involves balancing security, functionality, and performance. The polynomial degree, coefficient modulus, and other scheme parameters determine the security level, the depth of computation possible before noise overflow, and the size and processing time of ciphertexts. Optimal parameter selection requires understanding the specific requirements of the target application.

Security levels in HE are typically expressed in terms of equivalent symmetric key strength, with 128-bit security being a common target. Achieving this security level requires sufficiently large parameters that the best known attacks against the underlying lattice problems remain computationally infeasible. The community tables published by HomomorphicEncryption.org express the requirement as a cap on the ciphertext modulus for each ring dimension: at 128-bit classical security with a ternary secret, a ring of degree 8,192 admits a coefficient modulus of about 218 bits, and degree 16,384 admits about 438 bits. Doubling the ring dimension therefore roughly doubles the available modulus, and with it the multiplicative depth, while at least doubling the cost of every operation. Security estimates evolve as lattice cryptanalysis advances, and parameter recommendations have generally grown more conservative over time, which is an argument for hardware that can accommodate a range of parameter sets rather than one fixed choice.

The polynomial degree n directly affects both security and performance. Larger degrees provide stronger security but require more computation per operation. The degree also determines the number of plaintext values that can be packed into a single ciphertext through techniques like coefficient packing or slot encoding, creating a trade-off between single-instruction parallelism and per-operation cost.

The coefficient modulus, typically a product of several prime factors in RNS representation, determines the noise budget available for computation. Larger moduli provide more noise headroom but require wider arithmetic and increase ciphertext size. The choice of specific prime factors affects the efficiency of NTT computation, as NTT-friendly primes enable particularly efficient implementation.

Hardware accelerators often support multiple parameter sets to address different application requirements. Reconfigurable architectures can adapt their arithmetic precision, parallelism, and memory allocation to match specific parameter choices. Some systems provide automatic parameter selection based on high-level descriptions of the intended computation, simplifying deployment while ensuring appropriate security and performance characteristics.

Lattice Cryptography Foundations

Lattice cryptography provides the mathematical foundation for modern homomorphic encryption schemes. A lattice is a regular arrangement of points in n-dimensional space, generated by integer linear combinations of basis vectors. The security of lattice-based cryptography relies on the computational difficulty of problems involving these geometric structures, particularly the Shortest Vector Problem (SVP) and the Learning With Errors (LWE) problem.

The Learning With Errors problem, introduced by Oded Regev in 2005, asks to recover a secret vector given its noisy inner products with random vectors. Specifically, given samples of the form (a, b = <a, s> + e mod q), where a is random, s is the secret, and e is small error, the problem is to recover s. The hardness of LWE is related to worst-case hardness of certain lattice problems, providing strong theoretical security guarantees.

Ring-LWE (RLWE), introduced by Vadim Lyubashevsky, Chris Peikert, and Oded Regev in 2010, restricts the LWE problem to polynomial rings, dramatically improving efficiency while maintaining strong hardness guarantees rooted in worst-case ideal-lattice problems. Instead of vectors over integers, RLWE operates on polynomials, and the ring structure enables much more compact representations and efficient arithmetic. Most practical HE schemes use RLWE or closely related problems, such as the module variant (MLWE), as their security foundation.

The hardness assumptions underlying lattice cryptography are believed to resist quantum attacks, unlike the factoring and discrete logarithm problems that underpin RSA and elliptic curve cryptography. This post-quantum security is a significant advantage for HE, as investments in HE infrastructure will not be rendered obsolete by advances in quantum computing. Hardware implementations designed for lattice-based HE thus provide long-term security value.

Understanding the mathematical structure of lattice problems informs hardware design decisions. The geometric nature of lattices suggests certain algorithmic approaches, while the algebraic structure of polynomial rings enables efficient transform-based arithmetic. Hardware architects benefit from deep understanding of these mathematical foundations to make informed design choices that exploit the specific structure of HE computation.

Optimization Techniques

Optimization of homomorphic encryption implementations spans multiple levels, from algorithmic improvements that reduce the inherent complexity of operations to microarchitectural optimizations that maximize hardware utilization. Effective optimization requires attention to all these levels, as bottlenecks at any level can limit overall system performance.

Algorithmic optimizations include techniques like ciphertext packing, which encodes multiple plaintext values into a single ciphertext to amortize the cost of operations across many data items. SIMD-style operations on packed ciphertexts can process thousands of values simultaneously, dramatically improving throughput for applications with inherent data parallelism. The rotation operations that enable access to different slots within packed ciphertexts require their own optimization.

Lazy reduction strategies defer modular reduction operations until they become necessary, accumulating multiple products before performing a single reduction. This approach reduces the total number of expensive reduction operations at the cost of requiring wider intermediate storage. Hardware implementations can include accumulators with sufficient precision to support aggressive lazy reduction strategies.

Memory hierarchy optimization addresses the challenge of large ciphertext sizes. Ciphertexts in practical HE systems may be tens of megabytes, far exceeding typical cache sizes. Tiling strategies that decompose computations into cache-friendly chunks, combined with prefetching to hide memory latency, can significantly improve effective memory bandwidth. Hardware implementations may include specialized memory controllers optimized for HE access patterns.

Compiler and scheduling optimizations automatically transform high-level descriptions of HE computations into efficient operation sequences. These tools analyze data dependencies, estimate noise growth, and generate schedules that minimize total computation while respecting noise constraints. Some systems implement scheduling logic in hardware, enabling dynamic optimization based on runtime conditions.

Practical Implementations

Several hardware implementations of homomorphic encryption have demonstrated the feasibility of accelerated HE computation. These systems range from research prototypes exploring architectural concepts to commercial products targeting specific application domains. The diversity of implementations reflects the range of trade-offs possible in HE accelerator design.

Accelerator results are almost always reported against a small set of mature open-source software libraries, which serve as the field's reference baselines. Microsoft SEAL implements BFV and CKKS, OpenFHE (the successor to PALISADE) covers BGV, BFV, CKKS, and the DM and CGGI schemes together with scheme switching, HElib implements BGV and CKKS, Lattigo provides a Go implementation aimed at distributed and multi-party settings, and Zama's TFHE-rs and Concrete target programmable bootstrapping in Rust. Familiarity with these libraries matters to hardware designers because their internal data layouts, RNS conventions, and key formats effectively define the interfaces an accelerator must accept.

Intel's HEXL library provides optimized software primitives for HE computation on Intel processors, exploiting the AVX512-IFMA52 vector instructions available on recent Xeon parts to speed up the NTT and modular multiplication. Its authors reported single-threaded speedups of roughly seven times over portable C++ implementations of the NTT, and the library has been adopted as an optional backend by SEAL and OpenFHE. HEXL is not a dedicated accelerator, but it establishes an honest software baseline: comparisons against unoptimized scalar code overstate the benefit of dedicated hardware, sometimes by an order of magnitude.

FPGA implementations from academic groups have demonstrated substantial speedups for specific HE operations. Implementations on high-end FPGAs have achieved NTT throughput exceeding software implementations by factors of 100 or more, while complete HE operation implementations show order-of-magnitude improvements. FPGAs also expose the memory wall clearly: designs are typically limited by the bandwidth available to off-chip DDR or HBM rather than by their arithmetic units, which is precisely the finding that motivates the large on-chip scratchpads of proposed ASICs. These platforms serve as validation vehicles for architectural concepts before ASIC implementation.

Dedicated silicon has been pursued primarily through government-funded programs and startups. Under DARPA's DPRIVE program, Intel worked with Microsoft on an FHE accelerator and its software stack, and Duality Technologies led a separate team including SRI International; several other companies have announced accelerator chips or cards targeting specific schemes. Publicly reported performance figures should be treated with care, because they are frequently drawn from simulation, cover a single operation rather than an end-to-end workload, and are quoted against varying software baselines. As of this writing, no FHE ASIC has become a broadly available commercial product, and most deployed acceleration still runs on CPUs with vector extensions, on GPUs, or on FPGAs.

Deployment at consumer scale has nonetheless begun, using ordinary hardware and carefully chosen workloads. Apple released the open-source swift-homomorphic-encryption package in 2024, implementing BFV, and uses it for the Live Caller ID Lookup feature introduced in iOS 18. The feature performs private information retrieval: the device sends an encrypted query so that the server returns caller identification and spam information for a telephone number without learning which number was requested. The example is instructive for hardware designers because it shows what is already practical without accelerators. Private information retrieval requires only shallow, mostly additive circuits with no bootstrapping, so it fits comfortably within a somewhat homomorphic noise budget. The workloads that genuinely demand accelerators are the deep ones, such as neural network inference on encrypted inputs.

Cloud providers and specialist vendors have begun offering HE capabilities as managed services, abstracting the implementation details from users. These services may run on specialized accelerators or on optimized software implementations, providing HE functionality without requiring expertise in parameter selection or hardware configuration. The emergence of such services demonstrates growing commercial interest, though the underlying performance profile still favors applications whose circuits are shallow and whose data are naturally batched.

Integration Challenges

Integrating HE accelerators into practical systems involves challenges beyond raw computational performance. The programming model, data movement requirements, and interaction with system software all affect the usability and effectiveness of accelerated HE. Addressing these integration challenges is essential for translating hardware capability into application benefit.

Programming interfaces for HE accelerators must balance usability with the need to expose hardware capabilities effectively. High-level interfaces that hide implementation details simplify application development but may prevent applications from exploiting hardware features fully. Low-level interfaces provide control but require expertise to use effectively. Most systems provide multiple interface levels to address different user needs.

Data serialization and transfer between host systems and accelerators can become bottlenecks when ciphertext sizes are large. Efficient implementations minimize data movement through techniques like keeping ciphertexts resident on the accelerator across multiple operations and using compressed or streaming representations for transfer. Direct memory access (DMA) capabilities enable efficient bulk transfer when movement is necessary.

Key management for HE systems requires careful design to maintain security while enabling efficient computation. The public key used for encryption is modest, roughly the size of a ciphertext, but the evaluation keys are not. Relinearization keys, the sets of rotation keys needed to move data between the slots of a packed ciphertext, and the bootstrapping keys of the DM and CGGI schemes commonly total hundreds of megabytes and can reach the gigabyte range when many distinct rotation amounts must be supported. These keys must sit where the accelerator can stream them at full bandwidth, which often makes evaluation key storage, rather than ciphertext storage, the dominant memory requirement. Mitigations include generating rotation keys on demand, decomposing arbitrary rotations into a small set of power-of-two steps, and hoisting shared key-switching work across operations that reuse the same input.

Error handling in HE systems must account for the possibility of noise overflow and other failure modes. Unlike conventional computation, where errors are typically obvious, HE noise overflow produces incorrect results without any explicit error indication, and in an approximate scheme it may produce results that look plausible. Systems may implement noise tracking, verification mechanisms, or redundant computation to detect and handle such failures appropriately.

The threat model for HE accelerators differs instructively from that of conventional cryptographic hardware. A server-side evaluator holds only ciphertexts and public evaluation keys, never the secret key, so the classic side-channel concern of extracting a key from power or electromagnetic traces applies chiefly to the client-side hardware that performs key generation, encryption, and decryption. Server-side accelerators still require protection against fault injection, which can corrupt results silently, and attention to access patterns, since the sequence of operations and memory addresses can reveal the structure of a computation even when every operand is encrypted.

Standardization Efforts

Standardization of homomorphic encryption is progressing through several organizations, aiming to establish common parameter recommendations, interoperability requirements, and security guidelines. These standards will facilitate broader adoption by providing confidence in security levels and enabling software and hardware implementations from different vendors to work together.

The HomomorphicEncryption.org consortium brings together researchers and practitioners to develop community standards for HE. Its security standard, first issued in 2018 and revised since, provides tables of recommended parameters, primarily ring dimension and maximum coefficient modulus, that achieve 128-, 192-, and 256-bit security against the best known lattice attacks. These tables remain the practical reference for parameter selection while the formal standards mature. Companion work on common application programming interfaces aims to define interfaces that enable application portability across different HE implementations.

Within ISO/IEC, standardization has proceeded in stages. ISO/IEC 18033-6:2019 specifies partially homomorphic mechanisms, namely exponential ElGamal and Paillier encryption. A dedicated fully homomorphic encryption standard began in 2021 as the single-document project ISO/IEC 18033-8, but the responsible subcommittee discontinued that project in 2023 in favor of a multipart series, ISO/IEC 28033, on the grounds that one document could not carry the material. The drafts divide the field by arithmetic model: Part 1 establishes general concepts, security models, and hardness assumptions; Part 2 covers exact arithmetic on modular integers, the domain of BGV and BFV; Part 3 covers arithmetic on approximate numbers, the domain of CKKS; Part 4 covers arithmetic based on look-up table evaluation, the domain of the DM and CGGI schemes; and Part 5 covers scheme switching among these families. The parts remain in draft, so implementers continue to rely on community parameter tables in the interim.

The structure of the ISO/IEC series carries a direct message for hardware architects: the standards themselves recognize three distinct arithmetic models plus conversion among them. A design that commits to one model is standards-aligned but addresses only part of the field, and the existence of a scheme-switching part signals that mixed workloads are expected rather than exceptional.

NIST engages with homomorphic encryption through its Privacy-Enhancing Cryptography project, which tracks FHE alongside zero-knowledge proofs, multi-party computation, and threshold cryptography, and which convenes the Workshop on Privacy-Enhancing Cryptography. NIST has not opened a formal HE standardization competition comparable to its post-quantum cryptography process. The document frequently cited in this context, "Security Guidelines for Implementing Homomorphic Encryption," is a community effort by authors from academia and industry, published through the International Association for Cryptologic Research in support of the ISO/IEC work, rather than a NIST publication.

Hardware vendors participate in standardization efforts to ensure that emerging standards accommodate efficient implementation. Input from implementers helps ensure that standardized parameters and operations map well to practical hardware architectures. The interplay between standardization and implementation drives toward solutions that are both secure and efficiently realizable.

Application Domains

Homomorphic encryption hardware enables applications across multiple domains where computation on sensitive data is required. The performance improvements provided by acceleration expand the range of practically feasible applications, bringing HE capabilities to new problem areas.

Privacy-preserving machine learning represents one of the most active application areas for HE. Models can be evaluated on encrypted data, enabling prediction services without exposing the input data, and CKKS suits this work because neural network arithmetic tolerates approximation. The obstacle is nonlinearity: activation functions, comparisons, and pooling are not polynomials, so they must be replaced with polynomial approximations that consume multiplicative depth or evaluated through programmable bootstrapping under a DM or CGGI scheme. Both routes are expensive, and it is this cost, more than the linear layers, that hardware acceleration must address. Healthcare applications can analyze patient data without exposing records, and financial services can screen encrypted transactions, but inference latency for deep models remains far above plaintext equivalents even with acceleration.

Encrypted database queries allow searches and computations over encrypted data without exposing the data to the database system. Private information retrieval is the most mature case: a client retrieves a record by an encrypted key while the server, which holds the database in the clear, learns nothing about which record was requested. Because such lookups reduce to shallow, largely additive circuits, they run acceptably on general-purpose hardware today and are already deployed at consumer scale. Richer patterns, including private set intersection and encrypted analytics over sensitive business data, demand greater multiplicative depth and benefit correspondingly from acceleration.

Secure multi-party computation combines HE with other techniques to enable joint computation on data from multiple parties without any party revealing their private inputs. Applications include privacy-preserving auctions, collaborative analytics, and joint statistical analysis. The combination of techniques required for practical MPC benefits from accelerated HE as one component of the overall system.

Blockchain and cryptocurrency projects explore HE for confidential transactions and private smart contracts, in which balances and intermediate values remain encrypted while the network still processes them. Homomorphic evaluation is deterministic, so independent nodes given the same ciphertexts and evaluation keys reach identical results, which suits consensus. Homomorphic encryption alone proves nothing about whether an evaluator ran the agreed computation, however, so practical designs pair it with zero-knowledge proofs or verifiable computation, and they distribute the decryption capability through threshold key sharing so that no single party can read every value. The combined cost of these mechanisms, rather than the homomorphic arithmetic alone, currently limits deployment.

Future Directions

The field of homomorphic encryption hardware continues to evolve rapidly, driven by advances in both cryptographic theory and semiconductor technology. Several trends suggest the trajectory of future developments and the opportunities they will create.

Algorithmic improvements continue to reduce the computational requirements of HE operations. New bootstrapping techniques, more efficient encoding schemes, and better noise management strategies all contribute to narrowing the gap between HE and plaintext computation. Hardware implementations will need to adapt to exploit these algorithmic advances, potentially requiring more flexible architectures than current fixed-function designs.

Integration with other privacy-enhancing technologies creates opportunities for hybrid systems that combine the strengths of different approaches. Secure enclaves can protect HE key material and verify computation integrity, while multi-party computation protocols can distribute trust across multiple parties. Hardware platforms that support these combinations will enable more sophisticated privacy-preserving applications.

Emerging applications in edge computing and IoT create demand for compact, low-power HE acceleration. Sensor data can be encrypted at the source and processed throughout the data pipeline without exposure. Meeting the stringent size, weight, and power constraints of edge devices requires architectural innovations beyond current data center-focused designs.

The maturation of HE standardization will drive broader adoption and investment in hardware acceleration. As standards provide confidence in security levels and enable interoperability, organizations will more readily deploy HE solutions. This increased deployment will create market demand for high-performance, cost-effective accelerators, driving continued innovation in HE hardware design.

Summary

Homomorphic encryption hardware is the bridge between a cryptographic capability that has existed since 2009 and a technology that ordinary systems can afford to use. The computational requirements of HE operations create compelling demand for specialized acceleration. FPGA prototypes have measured order-of-magnitude gains on individual operations, and ASIC design studies project far larger end-to-end gains, though those projections await confirmation in fabricated silicon.

The design of effective HE accelerators requires understanding across multiple domains: the mathematical foundations of lattice cryptography, the characteristics of different HE schemes, the optimization of polynomial arithmetic and transform operations, and the system-level challenges of integration and deployment. This multidisciplinary nature makes HE hardware one of the most intellectually rich areas of computer engineering.

As applications demanding computation on encrypted data continue to multiply, from privacy-preserving machine learning to confidential cloud computing, the importance of HE hardware will only grow. Continued advances in algorithms, architectures, and integration will expand the practical applicability of homomorphic encryption, enabling new classes of applications that preserve privacy while delivering the benefits of modern computing.

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