Neuromorphic Computing
Neuromorphic computing borrows the organizing principles of biological nervous systems and builds them into silicon. Rather than separating memory from arithmetic in the manner of a conventional von Neumann machine, a neuromorphic processor distributes small blocks of memory among many simple compute elements, so that synaptic weights sit beside the neurons that use them. Communication happens through sparse, asynchronous events rather than clocked data movement. The result is an architecture tuned for energy efficiency, low-latency reaction to sensory input, and local adaptation rather than raw floating-point throughput.
The motivating comparison is stark. The human brain runs on roughly twenty watts while performing perception, motor control, and learning that remain expensive for conventional machines. Neuromorphic engineering, a field named by Carver Mead in the late 1980s, seeks to capture part of that advantage by exploiting device physics directly and by keeping data movement short. The approach does not replace general-purpose processors or dense matrix accelerators. It targets a different corner of the design space: always-on sensing, closed-loop control, and continual learning at the edge, where a power budget of milliwatts rules out a conventional accelerator. This article gives the general treatment, covering device physics, network models, hardware platforms, and large-scale research machines; the narrower question of how neuromorphic processors are selected, interfaced, and validated inside shipping embedded products is treated in embedded neuromorphic computing.
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Fundamental Principles
Three ideas separate neuromorphic hardware from conventional accelerators: computation driven by events rather than by a clock, plasticity implemented locally in the synapse, and memory placed next to the arithmetic that consumes it. Each principle has a direct hardware consequence, and each carries a cost that shapes what these machines do well.
Event-Driven Computation
In a spiking network, a neuron integrates incoming current onto a membrane state and emits a spike only when that state crosses a threshold. Between spikes the neuron does nothing, and the circuits that serve it draw only leakage current. Activity in a well-tuned spiking network is sparse, often with a small percentage of neurons active in any interval, so the energy cost tracks the information content of the input rather than the size of the network. A static scene presented to an event-based camera produces almost no traffic; a moving edge produces a burst.
Spikes travel between cores as address-event representation packets, in which a spike is encoded simply as the identity of the neuron that fired, timestamped implicitly by its moment of arrival. Because the payload is an address rather than a numeric value, the interconnect carries far less data than the activation tensors that move through a conventional accelerator. The trade-off is that timing becomes part of the representation, and the network is only as accurate as the hardware's ability to preserve spike order and latency across a large fabric.
Synaptic Plasticity and Local Learning
Learning in neuromorphic hardware is expressed as a change in synaptic weight computed from information already present at the synapse. Spike-timing-dependent plasticity, the best known rule, strengthens a connection when the presynaptic spike precedes the postsynaptic spike within a short window and weakens it when the order reverses. Because the rule depends only on locally available traces, it can run in the synapse circuit itself, with no gradient to propagate and no weight transfer to a host processor. Systems built this way adapt to drift in a sensor or a change in a workspace without a retraining cycle.
Local rules are not a complete substitute for gradient-based training. Unsupervised spike-timing-dependent plasticity discovers useful features but rarely matches the accuracy of a network trained end to end on a difficult task. Practical designs therefore combine the two: weights learned offline with gradient methods are loaded onto the chip, and on-chip plasticity handles incremental adaptation, few-shot addition of new classes, and homeostatic regulation of firing rates.
Colocated Memory and Parallelism
Moving a word from external DRAM costs orders of magnitude more energy than the multiply that consumes it, and that gap, not arithmetic, sets the power budget of most machine learning hardware. Neuromorphic architectures attack it by breaking the network into many small cores, each holding the synaptic state for its own neurons in local memory. The penalty is capacity. On-chip memory is expensive, so a single neuromorphic chip holds far fewer parameters than a GPU with attached high-bandwidth memory, and large models must be partitioned across many chips.
Hardware Implementations
Neuromorphic silicon spans a wide range, from fully digital event-driven processors that are conventional in every respect except their programming model, to analog circuits that let transistor physics stand in for neural dynamics, to emerging device arrays that store and compute in the same element.
Digital Spiking Processors
Digital designs trade some efficiency for reproducibility, testability, and access to standard design flows. IBM's TrueNorth, presented in 2014, placed one million neurons and 256 million synapses across 4,096 cores on a 28-nanometer die of 5.4 billion transistors, and drew on the order of tens of milliwatts while running real-time inference. TrueNorth fixed its weights at configuration time; it performed no on-chip learning. IBM's later NorthPole processor moved away from spiking altogether, applying the same brain-inspired emphasis on distributed on-chip memory to a 12-nanometer digital inference accelerator with 256 cores and 192 megabytes of local SRAM.
Intel's Loihi, introduced in 2017 on a 14-nanometer process, added programmable on-chip learning to the digital approach, with 128 neuromorphic cores supporting roughly 130,000 neurons and 130 million synapses. Loihi 2, announced in 2021, was fabricated on the Intel 4 process and raised capacity to as many as one million neurons and 120 million synapses per chip, while adding programmable neuron models, graded spikes that carry a small integer payload, and faster spike communication. In April 2024 Intel assembled 1,152 Loihi 2 chips into Hala Point, a research system delivered to Sandia National Laboratories that supports 1.15 billion neurons and 128 billion synapses across more than 140,000 neuromorphic cores within a chassis drawing under 2,600 watts.
The SpiNNaker machines take a software-centric route, simulating neurons on large arrays of small Arm processors connected by a packet-switched fabric built for the tiny messages that spikes produce. The first-generation machine at the University of Manchester reached roughly one million cores. SpiNNaker2, developed with TU Dresden in a 22-nanometer fully depleted silicon-on-insulator process, places 152 Arm-based processing elements on each chip together with accelerators for the dense arithmetic that hybrid networks still require, and uses adaptive body biasing and dynamic voltage and frequency scaling to operate near threshold.
Analog and Mixed-Signal Circuits
Analog neuromorphic circuits implement membrane integration and synaptic dynamics with capacitors and transistors biased in the subthreshold region, where drain current varies exponentially with gate voltage. A handful of devices can then reproduce behavior that would take many digital operations, at picojoule or lower cost per synaptic event. The Heidelberg BrainScaleS-2 system illustrates a second advantage of the analog approach: because its circuit time constants are set by small on-chip capacitors rather than by biological membranes, the system emulates network dynamics roughly a thousand times faster than real time, which makes long learning experiments practical. Digital plasticity processors on the same die handle weight updates and experiment control.
The cost of analog computation is precision. Transistor mismatch, temperature drift, and limited weight resolution mean that no two neurons behave identically, and results are not bit-reproducible from run to run. Neural networks tolerate a surprising amount of this imprecision, and calibration routines absorb much of the rest, but analog designs generally require per-chip characterization and are harder to verify than digital equivalents.
Memristive and In-Memory Arrays
Resistive devices whose conductance depends on their programming history, including resistive RAM, phase-change memory, and ferroelectric and spintronic cells, offer a compact analog synapse. Arranged in a crossbar, they perform a matrix-vector multiplication in one step: input voltages applied to the rows produce column currents that sum by Kirchhoff's current law, so the array computes the dot product physically rather than through a sequence of multiply-accumulate operations. Density is the main attraction, since a single device can replace the many transistors an SRAM cell requires.
Several obstacles keep these arrays largely in the research domain. Conductance states drift over time and vary from device to device, weight updates are nonlinear and asymmetric, write endurance is finite, and sneak-path currents complicate large arrays. The peripheral circuitry is also expensive: the digital-to-analog and analog-to-digital converters at the array edges can dominate both area and energy, which erodes the efficiency the crossbar was meant to deliver. Work continues on device engineering, on programming schemes that tolerate imperfect cells, and on integration of these arrays above conventional CMOS logic.
Programming Models and Benchmarking
Training a spiking network is harder than training a conventional one because the spike is a discontinuity, and a threshold function has no useful derivative. Two approaches dominate. Surrogate-gradient training replaces that derivative with a smooth approximation during the backward pass, allowing backpropagation through time to run over the unrolled network. Conversion methods instead train a conventional network with rate-friendly activations and map it onto spiking neurons, trading extra inference latency for accuracy that matches the original. Conversion is simpler and gives up on-chip learning; surrogate gradients are more general but cost memory proportional to the number of simulated time steps.
Software support has consolidated around a small set of frameworks. Intel's open-source Lava targets Loihi 2 and conventional processors through a process-based abstraction in which neurons exchange messages. PyNN and Nengo provide hardware-independent model description, while snnTorch, SpikingJelly, and Norse embed spiking layers in PyTorch so that standard automatic differentiation applies. None of these has the maturity of the tooling around mainstream accelerators, and portability between platforms remains limited.
Benchmarking has been a persistent weakness, because reported energy figures often exclude sensors, host processors, or data movement, and because accuracy on a task tuned to one platform says little about another. NeuroBench, a community effort published in 2025, addresses this with two tracks: an algorithm track that measures hardware-independent correctness together with model footprint and activation and connection sparsity, and a system track that measures end-to-end latency, throughput, and energy on deployed hardware. Comparable measurement is a precondition for neuromorphic hardware to be adopted on engineering grounds rather than on promise.
Applications
Neuromorphic systems earn their place where inputs are sparse and irregular, latency budgets are tight, and power is scarce. They are a poor fit for dense, batched workloads such as large language model training, which conventional accelerators handle far more efficiently.
Event-Based Vision and Always-On Sensing
Event cameras replace the global shutter of a conventional imager with pixels that report brightness changes independently and asynchronously. Each pixel emits an event carrying its address, a timestamp, and the sign of the change, giving microsecond temporal resolution, freedom from motion blur, and dynamic range above 120 decibels in commercial parts, enough to hold detail across a scene that spans deep shade and direct sun. The output is a sparse event stream that matches a spiking network directly, without the frame buffering and conversion that a conventional pipeline requires. Keyword spotting, vibration monitoring, and occupancy sensing exploit the same property in other modalities, keeping a low-power detector alive continuously and waking a larger processor only on a genuine event.
Robotics and Closed-Loop Control
Robotic platforms benefit from short and predictable reaction times rather than peak throughput. Neuromorphic controllers have been demonstrated for obstacle avoidance, optical-flow estimation, and tactile sensing, and their event-driven operation suits drones and small mobile robots where every milliwatt reduces flight time or range. On-chip plasticity adds a further advantage in these settings, letting a controller compensate for a worn actuator or a changed payload without returning to a training pipeline.
Edge Intelligence and Scientific Modeling
Battery-powered and implanted devices, including hearing aids, wearable health monitors, and neural interfaces, face power budgets that rule out conventional inference hardware. Neuromorphic processors extend useful inference into those budgets. At the other extreme of scale, large neuromorphic machines serve computational neuroscience directly, simulating cortical models fast enough to make plasticity and development studies tractable, and researchers have applied spiking formulations to constraint satisfaction, graph search, and sparse coding problems where the event-driven substrate maps naturally onto the algorithm.
Challenges and Outlook
The obstacles to wider adoption are as much practical as physical. On-chip memory limits model size. Analog devices vary and drift. Training methods for spiking networks lag those for conventional ones, and the tool chains lag further still. Published efficiency comparisons are often measured under conditions that favor the neuromorphic system, which is precisely the problem that standardized benchmarking sets out to correct. Meanwhile the conventional accelerators that neuromorphic hardware is measured against continue to improve, and aggressive quantization and structured sparsity have captured part of the efficiency advantage that spiking architectures once claimed exclusively.
The likely path forward is heterogeneous rather than wholesale replacement. Digital spiking cores supply programmability and reproducibility, analog or memristive arrays supply density and efficiency in the inner loop, and conventional processors handle everything that does not decompose into events. Progress across the subcategories listed above, from device physics through network models to system integration, determines how much of the brain's efficiency this class of hardware can ultimately capture.