Electronics Guide

Interface Architecture Elements

Every external memory interface comprises several fundamental elements that work together to enable data transfer:

Address bus: Carries memory location information from the processor to the memory device. Address bus width determines the maximum addressable memory space. Some interfaces multiplex address and data on shared pins to reduce pin count, requiring additional control signals to distinguish address from data phases.

Data bus: Transfers data between processor and memory in both directions. Data bus width affects transfer bandwidth directly; wider buses move more data per transaction but require more pins and board traces. Common widths include 8, 16, 32, and 64 bits, with some high-performance interfaces using even wider paths.

Control signals: Coordinate memory operations including read and write strobes, chip select signals, and timing references. The specific control signals vary by memory type but generally indicate operation type, timing boundaries, and which devices should respond.

Clock signals: Synchronous interfaces use clock signals to coordinate timing between processor and memory. Clock distribution requires careful attention to ensure all devices see clocks with appropriate timing relationships. Some interfaces use source-synchronous clocking where data and clock travel together, reducing timing uncertainty from clock distribution.

Synchronous Versus Asynchronous Interfaces

Memory interfaces operate in either synchronous or asynchronous modes, each with distinct characteristics and applications:

Asynchronous interfaces: Data transfers occur without a shared clock reference. The processor controls timing through control signal edges, with memory responding after specified propagation delays. Asynchronous interfaces are simpler to implement and work naturally with slower memory types. However, achieving high performance requires tight timing margins and careful analysis of worst-case delays. Static RAM and many Flash memory devices support asynchronous access.

Synchronous interfaces: A shared clock coordinates all data transfers, with operations occurring on clock edges. Synchronous operation enables higher frequencies because timing relationships are defined relative to clock edges rather than absolute propagation delays. SDRAM and modern Flash interfaces use synchronous protocols to achieve high bandwidth. The complexity shifts to clock distribution and ensuring setup and hold times are met at the memory device inputs.

Bandwidth and Latency Considerations

Memory interface performance involves both bandwidth and latency, which may require different optimization approaches:

Bandwidth: The maximum data transfer rate, typically measured in megabytes or gigabytes per second. Bandwidth depends on clock frequency, data bus width, and protocol efficiency. Burst transfers improve bandwidth by amortizing addressing overhead across multiple data words. Double data rate (DDR) techniques transfer data on both clock edges, effectively doubling bandwidth without increasing clock frequency.

Latency: The delay from initiating a memory access to receiving data. Initial access latency includes address decoding, row activation in DRAM, and signal propagation. For random access patterns, latency often matters more than peak bandwidth. Pipeline and interleaving techniques can hide latency by overlapping multiple transactions, but fundamental latency remains important for real-time applications.

Efficiency: Real-world bandwidth often falls below theoretical maximum due to protocol overhead, refresh cycles in DRAM, and access pattern effects. Efficient memory controllers optimize transaction scheduling to minimize overhead and maximize effective bandwidth for actual application access patterns.

SDRAM Architecture Overview

SDRAM organizes memory in a hierarchical structure that influences controller design:

Banks: SDRAM devices contain multiple independent banks (typically 4, 8, or 16) that can operate concurrently to some degree. Multi-bank operation enables pipelining and interleaving to improve performance. Each bank maintains its own row buffer and can be in different states simultaneously.

Rows and columns: Within each bank, memory cells are arranged in rows and columns. Accessing data requires first activating a row, which loads the entire row into sense amplifiers serving as a row buffer. Subsequent column accesses read or write data from this row buffer. Row activation consumes significant time and energy, making sequential access within a row much faster than random access across rows.

Burst operation: SDRAM transfers data in bursts of programmable length. After providing a starting column address, the memory automatically advances through consecutive locations. Burst lengths of 4, 8, or 16 transfers are common, with some devices supporting full-row bursts. Burst operation dramatically improves bandwidth for sequential access patterns.

Controller State Machine

SDRAM controllers implement state machines that sequence through required operations while respecting timing constraints:

Initialization sequence: After power-up, SDRAM requires a specific initialization sequence including stable clock provision, a delay period, precharge commands, refresh cycles, and mode register programming. The controller must execute this sequence before any data access can occur.

Command scheduling: The controller translates processor memory requests into SDRAM commands: activate (open a row), read, write, precharge (close a row), and refresh. Command scheduling must respect minimum timing intervals between commands, such as the row-to-column delay (tRCD) between activate and read or write commands.

Bank management: Effective controllers track the state of each bank (idle, active with specific row, or precharging) and schedule commands to maximize parallelism. Opening rows speculatively based on predicted access patterns can hide activation latency.

Refresh management: DRAM cells lose charge over time and require periodic refresh to maintain data. The controller must issue refresh commands at required intervals (typically every 64 ms for the entire memory) while minimizing impact on normal access. Refresh can be distributed evenly over time or burst during idle periods.

DDR SDRAM Interfaces

Double Data Rate SDRAM transfers data on both rising and falling clock edges, doubling bandwidth compared to single data rate (SDR) SDRAM at the same clock frequency. Successive DDR generations have increased performance while adding complexity:

DDR (DDR1): The original DDR standard introduced double data rate transfers with data rates from 200 to 400 MT/s (million transfers per second). DDR uses 2.5V signaling and a relatively straightforward interface compared to later generations.

DDR2: Doubled the data rate to 400-1066 MT/s by using 4-bit prefetch (reading 4 bits internally for each external transfer) and 1.8V signaling. DDR2 introduced on-die termination (ODT) to improve signal integrity at higher speeds.

DDR3: Further increased speeds to 800-2133 MT/s with 8-bit prefetch and 1.5V signaling (1.35V for DDR3L). DDR3 added features including dynamic ODT adjustment and automatic self-refresh for power management.

DDR4: Extended performance to 1600-3200 MT/s with 1.2V signaling. DDR4 introduced bank groups for finer-grained parallelism, improved power management, and error correction capabilities.

DDR5: The latest generation achieves 3200-6400 MT/s and beyond with 1.1V signaling. DDR5 features on-die ECC, two independent channels per DIMM, and enhanced power management. The increased complexity requires sophisticated controllers and careful board design.

LPDDR for Mobile Applications

Low Power DDR (LPDDR) variants target mobile and battery-powered embedded applications where power efficiency is paramount:

Power optimization features: LPDDR specifications include aggressive power-down modes, temperature-compensated self-refresh, and lower operating voltages. These features significantly reduce standby and active power consumption compared to standard DDR.

Package integration: LPDDR devices often use package-on-package (PoP) mounting where the memory stacks directly on the processor package. This approach minimizes board space and reduces interface trace lengths, improving signal integrity while saving PCB area.

LPDDR generations: LPDDR specifications have evolved through LPDDR2, LPDDR3, LPDDR4, LPDDR4X, and LPDDR5, with each generation improving bandwidth and power efficiency. LPDDR5, for example, achieves up to 6400 MT/s while including features like deep sleep mode and dynamic voltage-frequency scaling support.

Parallel NOR Flash

NOR Flash provides random-access read capability with relatively simple parallel interfaces, making it suitable for execute-in-place (XIP) applications where code runs directly from Flash:

Interface characteristics: Parallel NOR Flash interfaces resemble asynchronous SRAM, with separate address and data buses plus control signals for read, write, and chip select. Read operations complete in tens of nanoseconds, fast enough for direct code execution. Some devices support synchronous burst modes for improved sequential read performance.

Write operations: Flash programming (writing) is much slower than reading and requires specific command sequences. The controller must issue unlock commands, provide program data, and wait for the internal programming operation to complete. Page-mode programming writes multiple bytes more efficiently than byte-at-a-time operations.

Erase requirements: Flash memory requires erasing before programming, and erasure operates on large blocks (typically 64KB to 256KB) rather than individual bytes. The controller must manage erase operations, which take milliseconds to complete, without disrupting system operation. Wear leveling in higher layers distributes erase cycles to extend device life.

Serial NOR Flash (SPI Flash)

Serial Peripheral Interface (SPI) Flash trades bandwidth for simpler connectivity, requiring only a few pins for communication:

Standard SPI: Basic SPI Flash uses four signals: chip select, clock, data in, and data out. This minimal interface simplifies board design and reduces pin count requirements on the processor. Standard SPI achieves modest throughput, typically 50-100 Mbps, suitable for code storage in systems that copy code to RAM before execution.

Dual and Quad SPI: Enhanced modes use additional data lines to increase bandwidth. Dual SPI uses two bidirectional data lines, while Quad SPI (QSPI) uses four. These modes can achieve 400+ Mbps throughput, approaching parallel Flash performance while maintaining simple connectivity. Many microcontrollers include QSPI controllers with execute-in-place support.

Octal SPI: The latest serial Flash interfaces use eight data lines plus a data strobe signal, achieving throughput exceeding 400 MB/s. Octal SPI blurs the line between serial and parallel interfaces while maintaining the command-based protocol structure of SPI Flash.

NAND Flash Interfaces

NAND Flash provides high-density storage at lower cost than NOR Flash but requires different interface approaches due to its page-based access structure:

Raw NAND interface: Raw NAND Flash uses a parallel interface with multiplexed command, address, and data phases on shared pins. The controller issues command bytes, address bytes, and then transfers data. The interface is simpler than SDRAM but still requires a capable controller to handle the command protocol, status checking, and error management.

ONFI standard: The Open NAND Flash Interface specification standardizes the interface protocol, timing, and command sets across manufacturers. ONFI defines synchronous modes achieving high throughput and includes features for parameter discovery, enabling controllers to adapt to different NAND devices.

Managed NAND (eMMC): Embedded MultiMediaCard (eMMC) integrates NAND Flash with a controller that handles wear leveling, bad block management, and error correction. The external interface is a simple MMC/SD protocol, dramatically simplifying host design. eMMC is widely used in mobile devices and embedded systems where the host lacks sophisticated NAND management capabilities.

Universal Flash Storage (UFS): UFS provides higher performance than eMMC using serial interfaces derived from SCSI protocols. UFS supports command queuing and simultaneous read and write operations, achieving significantly better performance for demanding applications. UFS has become standard in smartphones and is expanding to other embedded applications.

Setup and Hold Time

Setup and hold times define the window during which data must be stable relative to a clock or strobe edge:

Setup time (tSU): Data must be stable for at least the setup time before the capturing clock edge. Insufficient setup time causes metastability or incorrect data capture. Setup time budgets must account for clock-to-out delays at the transmitter, propagation delay through traces and components, and clock skew between source and destination.

Hold time (tH): Data must remain stable for at least the hold time after the capturing clock edge. Hold time violations often result from excessive clock skew where the clock arrives early at the destination relative to data. Some systems intentionally add delay to data paths to ensure hold time compliance.

Timing margin: Practical designs require timing margin beyond minimum requirements to accommodate temperature variations, voltage fluctuations, aging effects, and manufacturing tolerances. Timing analysis tools calculate worst-case timing across process-voltage-temperature (PVT) corners to ensure operation under all conditions.

SDRAM Timing Parameters

SDRAM interfaces involve numerous timing parameters that controllers must respect:

Clock-related parameters: tCK defines the clock period, with all other parameters often specified in clock cycles. The memory speed grade indicates maximum clock frequency; for example, DDR4-2400 supports 1200 MHz clock (2400 MT/s data rate).

Row timing: tRCD (row-to-column delay) specifies the minimum time between row activation and column access. tRP (row precharge time) defines minimum precharge duration before the same bank can activate another row. tRC (row cycle time) limits how quickly the same row can be reaccessed. tRAS (row active time) specifies minimum row active duration.

Column timing: tCL or CAS latency defines clock cycles between read command and data output. tWR (write recovery time) specifies delay after write before precharge. Burst length affects how many data transfers follow each command.

Refresh timing: tREFI (refresh interval) specifies maximum time between refresh operations to any row. tRFC (refresh cycle time) defines how long refresh occupies the device. Proper refresh scheduling ensures data integrity without excessively impacting access bandwidth.

Source-Synchronous Clocking

High-speed memory interfaces use source-synchronous clocking to overcome timing challenges from clock distribution:

Concept: Rather than distributing a single clock to all devices, source-synchronous interfaces transmit clock (or strobe) signals alongside data from each source. Since clock and data traverse similar paths, timing relationships established at the source are largely preserved at the destination, reducing timing uncertainty from trace length variations.

Data strobe signals: DDR SDRAM interfaces use bidirectional data strobes (DQS) transmitted with read and write data. For writes, the controller transmits data centered on DQS edges; the memory uses DQS to capture data. For reads, the memory transmits data edge-aligned with DQS; the controller must shift DQS to center it within data valid windows before sampling.

Strobe leveling: DDR3 and later generations include training procedures to optimize strobe timing. Write leveling adjusts DQS timing for writes to compensate for routing differences. Read leveling (also called DQS gating) determines when to start capturing read data and adjusts sampling point within the data eye.

Timing Calibration and Training

Modern high-speed memory interfaces require runtime calibration to achieve reliable operation:

PVT compensation: Process, voltage, and temperature variations affect timing. Controllers include calibration circuits that adjust output drive strength, input thresholds, and delay elements to maintain timing margins across operating conditions. Periodic recalibration compensates for temperature changes during operation.

Training sequences: DDR3 and DDR4 controllers execute training sequences during initialization that write known patterns and adjust timing until reliable operation is achieved. Training determines optimal delay settings for each byte lane independently, accommodating routing length differences.

ZQ calibration: The ZQ pin on DDR devices connects to a precision resistor that serves as an impedance reference. ZQ calibration commands trigger internal calibration that adjusts output driver and termination impedances based on this reference, maintaining signal integrity as conditions change.

Transmission Line Effects

At high frequencies, PCB traces behave as transmission lines where impedance mismatches cause reflections:

Characteristic impedance: Traces have characteristic impedance determined by geometry and dielectric properties. Typical values range from 40 to 60 ohms for single-ended signals and 80 to 120 ohms differential. Memory interface specifications define target impedances that board designers must match.

Impedance discontinuities: Changes in trace width, layer transitions through vias, connector interfaces, and device pin connections create impedance discontinuities that reflect signal energy. Minimizing discontinuities and using proper via designs reduces reflections. Stub lengths at device connections should be minimized, ideally using fly-by topologies for DDR interfaces.

Propagation delay: Signals propagate through FR-4 PCB material at approximately 6 inches per nanosecond (15 cm/ns). This propagation delay creates timing differences between signals of different lengths and affects the relationship between clock and data at receiving devices. Careful length matching ensures signals arrive with proper timing relationships.

Termination Strategies

Proper termination absorbs signal energy to prevent reflections that corrupt data:

Series termination: Resistors placed near signal sources increase output impedance to match trace impedance. Series termination works well for point-to-point connections and reduces overshoot at the receiver. The termination resistor value plus driver output impedance should equal the trace characteristic impedance.

Parallel termination: Resistors at the receiving end terminate the transmission line. Parallel termination is effective for buses with multiple loads but consumes DC power through the termination resistors. Thevenin termination using pull-up and pull-down resistors can provide proper AC termination while centering the idle voltage.

On-die termination (ODT): Modern DDR devices include programmable termination resistors within the memory chips. ODT reduces component count and board complexity while providing precisely controlled termination. Controllers can dynamically adjust ODT settings based on the operation (read versus write) and system configuration.

Active termination: Some systems use active circuits that behave as resistive loads for signal termination while consuming less power than passive termination. DDR devices with ODT implement a form of active termination using controlled-impedance output drivers.

Crosstalk and Noise

Electromagnetic coupling between signals creates crosstalk that adds noise and can cause false transitions:

Capacitive crosstalk: Electric field coupling between adjacent traces creates capacitive crosstalk. This coupling is proportional to trace proximity and parallel length. Increasing spacing between critical signals and reducing parallel run length minimizes capacitive crosstalk.

Inductive crosstalk: Magnetic field coupling creates inductive crosstalk, particularly for signals with fast edges and high currents. Return path discontinuities exacerbate inductive crosstalk by forcing return currents through longer paths. Maintaining solid reference planes and avoiding slots or gaps near signal traces reduces inductive coupling.

Simultaneous switching noise: Multiple outputs switching simultaneously create large current transients that couple into power and ground networks, appearing as noise on signal references. This simultaneous switching output (SSO) noise is particularly problematic in wide buses. Adequate power supply decoupling and limiting simultaneous transitions through data encoding help manage SSO.

Power Distribution Network

High-speed memory interfaces place demanding requirements on power distribution:

Decoupling strategy: Multiple decoupling capacitor values span the frequency range from DC to hundreds of megahertz. Bulk capacitors (tens to hundreds of microfarads) handle low-frequency demands and load transients. Smaller ceramic capacitors (0.1 to 10 microfarads) address mid-frequency noise. Very small capacitors or embedded capacitance handle highest frequencies. Capacitor placement close to device power pins minimizes connection inductance.

Power plane design: Dedicated power planes provide low-impedance distribution and serve as return paths for signals referenced to those supplies. Plane size and shape affect impedance at different frequencies. Split planes may be necessary for different voltage domains but require careful design to avoid creating return path discontinuities.

Voltage regulation: Memory devices require stable voltage supplies, with DDR4 typically requiring 1.2V plus or minus 3%. Point-of-load regulation near memory devices reduces the impact of IR drop and provides fast transient response. Some designs use dedicated regulators for VDDQ (data I/O supply) separate from VDD (core supply) for better noise isolation.

PCB Layout Guidelines

Following established layout practices ensures signal integrity in memory interfaces:

Layer stackup: Memory interface signals should route on layers adjacent to continuous reference planes. Common stackups for DDR place signals on surface layers with immediate ground planes below, or on internal layers sandwiched between power and ground planes. Proper stackup maintains controlled impedance and provides low-inductance return paths.

Length matching: DDR interfaces require tight length matching within signal groups. Data signals (DQ) must match within their byte lane. Address and command signals must match relative to the clock. Strobe signals (DQS) must match their associated data groups. Length matching tolerances tighten with increasing interface speed; DDR4 typically requires matching within 10-25 mils within groups.

Fly-by topology: DDR3 and DDR4 use fly-by routing for address, command, and clock signals, where traces run sequentially past each memory device rather than branching to each. Fly-by topology eliminates stub reflections and provides cleaner signal quality but creates timing skew between devices that write leveling compensates for.

Via management: Vias add inductance and capacitance to signal paths. Minimizing via count on critical signals improves performance. When vias are necessary, using back-drilled or buried vias eliminates stub effects. Ground vias near signal vias provide return current paths.

Controller Architecture

Modern memory controllers contain several functional blocks:

Frontend interface: Receives memory requests from processors or DMA controllers through system bus protocols like AXI, AHB, or proprietary interfaces. The frontend buffers requests, reorders transactions for efficiency when permitted, and manages quality-of-service priorities.

Command scheduler: Converts logical memory requests into sequences of memory commands. Sophisticated schedulers optimize command ordering to maximize bandwidth by keeping rows open for subsequent accesses, interleaving accesses across banks, and minimizing page conflicts. Scheduler algorithms balance throughput optimization against latency and fairness requirements.

Timing engine: Ensures all timing constraints are met by tracking time since previous commands and blocking new commands until minimum intervals have elapsed. The timing engine must handle the complex interactions between different command types and multiple banks.

PHY layer: The physical layer (PHY) implements the electrical interface to memory devices. The PHY includes drivers, receivers, delay lines, calibration circuits, and training logic. Many SoCs use licensed PHY IP blocks that implement the demanding analog and mixed-signal circuits required for high-speed memory interfaces.

Address Mapping Schemes

How physical addresses map to memory rows, banks, and columns affects performance and power:

Row-bank-column (RBC): Sequential addresses access different columns within the same row and bank before advancing to the next row. This mapping optimizes for sequential access patterns, keeping rows open for burst accesses.

Bank-row-column (BRC): Sequential addresses access different banks before advancing to new rows. This mapping enables bank interleaving, hiding row activation latency by accessing other banks while one activates. BRC benefits random access patterns but may cause more row conflicts for sequential patterns.

Hybrid schemes: Some controllers use configurable or adaptive mappings that adjust based on access patterns. Understanding application memory access characteristics helps select optimal mapping for specific workloads.

Error Detection and Correction

Memory errors from noise, radiation, or device defects can corrupt data. Controllers may implement protection mechanisms:

ECC memory: Error-correcting code (ECC) memory adds extra bits to each data word, enabling detection and correction of single-bit errors and detection of multi-bit errors. ECC requires wider memory interfaces (typically 72 bits for 64-bit data) and adds latency for encoding and decoding. ECC is essential for reliable systems and required in safety-critical applications.

On-die ECC: DDR5 and some DDR4 devices include on-die ECC that corrects errors within the memory chip before data reaches the interface. On-die ECC improves reliability without requiring wider external interfaces but does not protect against errors in the interface itself.

Memory scrubbing: Background scrubbing reads and rewrites memory to detect and correct soft errors before they accumulate. Scrubbing is particularly important in systems with large memory that may not access all locations frequently enough for errors to be detected through normal operation.

Simulation and Analysis

Pre-layout simulation helps identify potential problems before fabricating boards:

Signal integrity simulation: Tools like HyperLynx, Cadence Sigrity, or Ansys simulate transmission line behavior, crosstalk, and power distribution network performance. These simulations use device IBIS models and PCB stackup parameters to predict eye diagrams, timing margins, and noise levels. Simulation identifies issues that can be addressed through routing changes before committing to fabrication.

Timing analysis: Static timing analysis verifies that all setup and hold requirements are met across process-voltage-temperature corners. Memory vendors provide timing models for their devices. Analysis must account for controller timing, PCB delays, and memory device parameters.

Thermal simulation: Memory devices generate heat that affects their timing and reliability. Thermal simulation ensures that memory temperatures remain within specifications under expected operating conditions and airflow.

Hardware Debugging

When memory interfaces fail to work correctly, systematic debugging identifies root causes:

Eye diagram measurement: Oscilloscopes with appropriate bandwidth capture eye diagrams that reveal signal quality. The eye opening indicates margin for data sampling; wider, more open eyes indicate better signal quality. Eye closure from noise, jitter, or intersymbol interference identifies problems requiring investigation.

Protocol analysis: Logic analyzers and protocol analyzers capture memory transactions, revealing command sequences and timing. Comparing captured waveforms against specifications identifies timing violations or incorrect command sequences.

Memory BIST: Built-in self-test (BIST) patterns exercise memory with specific patterns designed to stress worst-case conditions. Common patterns include walking ones/zeros that test for stuck bits and coupling faults, checkerboard patterns that create maximum simultaneous switching, and address-dependent patterns that test address decoding. Failed addresses indicate specific problems with particular devices or connections.

Margining: Intentionally degrading timing or voltage margins reveals how close the design operates to failure boundaries. Systems with minimal margin may work in the lab but fail in production or field conditions. Margining tests help ensure adequate design robustness.

Common Problems and Solutions

Certain issues frequently arise in memory interface development:

Training failures: When DDR training fails to find valid timing windows, possible causes include signal integrity problems, incorrect termination, clock jitter, or power supply noise. Examining training results and eye diagrams narrows down the cause.

Temperature sensitivity: Designs that work at room temperature but fail at temperature extremes often have marginal timing. Simulation across temperature range and testing at corners identifies temperature-sensitive designs.

Pattern sensitivity: Some bit patterns stress interfaces more than others. If certain data patterns fail consistently, crosstalk or power distribution problems may be responsible. Running diverse test patterns ensures the interface handles all data reliably.

Intermittent failures: Random, intermittent memory errors are particularly difficult to debug. Causes include marginal timing, inadequate termination, power supply noise, and even external interference. Statistical testing over extended periods with comprehensive logging helps capture and characterize intermittent failures.

High Bandwidth Memory

High Bandwidth Memory (HBM) stacks multiple DRAM dies with through-silicon vias (TSVs), achieving very high bandwidth in a compact footprint:

Architecture: HBM stacks up to 12 DRAM dies on a base logic die that provides the interface. Wide interfaces (1024 bits or more) combined with multiple channels achieve bandwidth exceeding 400 GB/s. The short, vertical connections minimize power consumption per bit transferred.

Integration: HBM connects to processors through silicon interposers or direct die-to-die bonding rather than traditional PCB traces. This integration approach suits high-performance processors and accelerators but requires advanced packaging technologies.

Compute Express Link Memory

Compute Express Link (CXL) extends PCIe to support memory coherency and expansion:

CXL.mem: The memory protocol in CXL enables processors to access remote memory pools with cache coherency. This capability supports memory expansion beyond what DIMM slots provide and enables disaggregated memory architectures.

Memory pooling: CXL allows multiple processors to share memory pools, improving utilization in data center environments. Memory can be dynamically allocated to different processors based on workload demands.

Non-Volatile Memory Interfaces

Emerging non-volatile memory technologies require new interface approaches:

Persistent memory: Technologies like Intel Optane (3D XPoint) and upcoming CXL-attached persistent memory provide byte-addressable non-volatile storage. These devices interface through DDR-like or CXL protocols, requiring controllers that understand their unique characteristics including asymmetric read/write performance and wear considerations.

Storage class memory: Memory technologies positioned between DRAM and Flash in the storage hierarchy use various interfaces depending on their performance characteristics and intended use. Interface standards continue evolving to accommodate these new memory types.