Electronics Guide

Edge AI and Machine Learning

Inference is moving from the cloud to the device. Four forces drive the move: latency budgets that a network round trip cannot meet, privacy rules that discourage shipping raw audio and video off the device, bandwidth and cellular data costs at fleet scale, and the simple requirement that a product keep working when the network does not.

Fitting a model into a microcontroller is mostly a compression problem. Post-training quantization from 32-bit floating point to 8-bit integers cuts weight storage by four and lets the model run on integer arithmetic units that most microcontrollers already have; quantization-aware training recovers much of the accuracy lost in the process, and 4-bit and binary weights are practical for some layers. Pruning removes weights that contribute little, and knowledge distillation trains a small model to imitate a large one. The result is workable: a keyword-spotting model can occupy a few tens of kilobytes and run within roughly a hundred kilobytes of RAM, and anomaly detection on vibration or current signatures is smaller still.

The tooling has consolidated around a few paths. LiteRT for Microcontrollers, which Google renamed from TensorFlow Lite for Microcontrollers when it rebranded TensorFlow Lite as LiteRT in 2024, remains the common runtime, and vendor libraries such as Arm's CMSIS-NN provide kernels tuned to the underlying core. For heavier workloads, microcontroller-class neural processing units, including the Arm Ethos-U family, execute quantized convolutional layers at a fraction of the energy a general-purpose core would need. The remaining friction is operational rather than mathematical: models drift, field data is hard to collect from devices that were deployed precisely because they do not stream data, and retraining a fleet of shipped products is a firmware-update problem as much as a machine-learning problem. See machine learning at the edge for the full treatment, and gateway and edge computing for the tier above the device.

RISC-V and Open Hardware

RISC-V is an open instruction set architecture rather than an open processor. Its structure is deliberately minimal: a small mandatory base integer set, RV32I or RV64I, is extended through ratified standard options for integer multiplication and division, atomic operations, single- and double-precision floating point, compressed 16-bit encodings, bit manipulation, cryptography, and vector processing. Designers may also add custom instructions in reserved encoding space, which is why the architecture appears so often in domain-specific accelerators.

Fragmentation is the obvious risk of that modularity, and the community answers it with profiles: fixed bundles of extensions that software can assume. RISC-V International ratified the RVA23 profile for 64-bit application processors in October 2024, making the vector and hypervisor extensions mandatory and establishing the baseline that Android's RISC-V support targets. Profiles matter more than any single extension, because a Linux distribution or a commercial compiler can support a profile but cannot support every possible combination of options.

The openness extends past the specification to open-source core implementations, GCC and LLVM back ends, debug and trace standards, and shared verification suites. The incumbent it competes with is Arm, which licenses processor intellectual property rather than selling chips, charging a license fee for a core or for the architecture itself and then a royalty on every unit shipped; that model still supplies most embedded and mobile processor cores, and the broader background appears under instruction set architecture. Two adoption patterns dominate embedded work. In the first, RISC-V replaces a proprietary core in a cost-sensitive microcontroller and removes that per-unit royalty. In the second, and quietly the larger one, RISC-V cores serve as the power-management, security, and housekeeping processors buried inside larger systems on chip, where the instruction set is invisible to the customer and the freedom to customize matters more than the ecosystem.

Neuromorphic Computing

Neuromorphic processors abandon the clocked instruction stream. In a spiking neural network, neurons communicate through discrete events, and a neuron consumes energy only when it fires or receives a spike. Because activity in most sensory streams is sparse, an event-driven fabric can idle at near-zero power between events, which suits always-on tasks such as wake-word detection, gesture recognition, and vibration monitoring. The natural sensor partner is the event-based, or dynamic, vision sensor, whose pixels report brightness changes independently with microsecond timing and very high dynamic range instead of producing whole frames at a fixed rate.

Research hardware has reached substantial scale. Intel's Loihi 2, introduced in 2021, underpins Hala Point, a research system delivered in 2024 that supports more than one billion neurons while drawing on the order of 2.6 kilowatts. IBM's NorthPole research chip, published in 2023, keeps all weights in on-chip SRAM to avoid the external-memory bottleneck that limits conventional inference accelerators. SpiNNaker2 takes a different route, using many small Arm cores with neuromorphic and machine-learning accelerators to simulate large networks in real time. Commercial edge parts, such as BrainChip's Akida, bring the approach to milliwatt-class devices.

Honest assessment matters here. Training methods for spiking networks remain less mature than backpropagation on conventional deep networks, benchmark comparisons across such different architectures are contested, and the tooling is thin compared with the tinyML ecosystem. Neuromorphic computing is a strong candidate for narrow, always-on, event-sparse workloads, and it is not yet a general replacement for a quantized network on a conventional accelerator.

Heterogeneous Computing

Modern embedded silicon rarely contains one kind of processor. A typical applications processor combines out-of-order application cores running Linux, a lockstep real-time core running a safety function, a digital signal processor filtering sensor streams, a GPU or display pipeline, a neural accelerator, and sometimes programmable logic for fixed-function pipelines. Matching each task to the engine that executes it most efficiently can improve energy per operation by an order of magnitude relative to running everything on the application cores.

The difficulty shifts from computation to orchestration. Data must move between engines without copying it three times; caches must be coherent, or software must manage coherency explicitly; and the cores must synchronize through mailboxes, interrupts, and shared memory regions. Asymmetric multiprocessing frameworks address the software side, with Linux remoteproc and RPMsg, and the OpenAMP project, providing a standard way for a rich operating system to load, start, and exchange messages with a real-time core on the same device. Above that layer, OpenCL, SYCL, and vendor software development kits let a developer target an accelerator without rewriting the application, though portability across vendors remains limited in practice. Power and thermal management becomes a system-level problem as well, because engines that are idle still leak, and engines that run simultaneously may exceed the package's sustained power budget. See heterogeneous computing and hardware acceleration for detail.

Advanced Packaging and Chiplets

Monolithic scaling has become expensive enough that partitioning is often cheaper. A chiplet design splits a system across several smaller dies, each fabricated on the process node that suits its function: logic on a leading-edge node, analog and input/output on a mature node that offers better device matching and lower mask cost, and memory on a process optimized for density. Smaller dies also yield better, because a defect scraps less silicon.

Connecting the pieces requires interconnect far denser than a printed circuit board provides. Silicon interposers and silicon bridges carry thousands of short traces between adjacent dies; fan-out wafer-level packaging offers a cheaper organic alternative; and true three-dimensional stacking uses through-silicon vias or hybrid bonding to place dies directly atop one another, shortening links to microns and cutting the energy required to move each bit. Standardization has followed. The Universal Chiplet Interconnect Express specification defines a die-to-die protocol and physical layer; UCIe 2.0 added support for three-dimensional packaging and system manageability, and UCIe 3.0, released in August 2025, raised the peak link rate to 48 and 64 gigatransfers per second.

The costs are real. Testing a die before assembly, the known-good-die problem, determines whether the yield advantage survives packaging. Stacked logic concentrates heat where it is hardest to remove, and power delivery must reach through the stack without excessive droop. For these reasons chiplets appeared first in data-center and high-performance parts, where the economics are most favorable, and reach cost-sensitive embedded devices more slowly, usually as integrated memory rather than as disaggregated logic.

Advanced Memory Technologies

Embedded NOR flash, the default firmware store for decades, becomes difficult and expensive to integrate below roughly the 28-nanometer node, which forces a change as microcontrollers move to finer processes. Magnetoresistive RAM has emerged as the leading replacement, and major foundries offer embedded MRAM at 28 and 22 nanometers. It is byte-alterable, writes far faster than flash, and tolerates orders of magnitude more write cycles, which matters for parameter storage and data logging. Resistive RAM, phase-change memory, and ferroelectric RAM occupy adjacent niches; ferroelectric RAM in particular has long been used where extremely low write energy and high endurance justify its lower density.

The system consequences are more interesting than the device physics. A memory that is both persistent and fast enough for working storage blurs the boundary between RAM and storage: a device can resume instantly from a power interruption, a property that energy-harvesting designs exploit through checkpointing. Non-volatile arrays also enable compute-in-memory schemes that perform multiply-accumulate operations within the array itself, eliminating most of the data movement that dominates inference energy, though that work remains largely at the research and early-product stage.

New memory still needs a business case, not only a favorable datasheet. Intel's Optane products, built on phase-change technology and technically capable, were discontinued in 2022 for lack of a viable market position. Density, cost per bit, retention at high temperature, and the availability of a second source govern adoption in embedded designs at least as much as raw performance. Related material appears under non-volatile storage.

Advanced Connectivity

Wireless options have stratified by the requirement they serve rather than by generation. In the wide area, 5G's ultra-reliable low-latency communication profile targets time-critical control and vehicle-to-everything links, while 3GPP's reduced-capability devices, introduced in Release 17, fill the gap between full 5G modems and narrowband technologies for mid-tier sensors, cameras, and wearables. Low-power wide-area networks occupy the opposite corner: LoRaWAN, NB-IoT, and LTE-M trade throughput for kilometer-scale range and multi-year battery life, which suits meters, asset trackers, and environmental sensors. Non-terrestrial network support in recent 3GPP releases extends the same idea to satellite links for assets that travel beyond terrestrial coverage.

In the local area, Wi-Fi 6 and Wi-Fi 6E raised efficiency in dense deployments, and Wi-Fi 7 continues the trend. The underlying amendment, IEEE 802.11be, was approved in September 2024 and published as IEEE Std 802.11be-2024 in July 2025, though the Wi-Fi Alliance began certifying products in January 2024, well ahead of publication. Its most consequential feature for embedded use is multi-link operation, which lets a device transmit and receive across bands simultaneously to reduce worst-case latency rather than merely to raise peak throughput.

Short-range standards continue to specialize as well: Bluetooth Low Energy remains the default for phone-adjacent devices, ultra-wideband provides centimeter-class ranging for access control and asset location, and Thread with the Matter application layer has consolidated much of the fragmented smart-home protocol landscape. Selecting among these is an exercise in constraints rather than capability, and the trade-offs appear in Internet of Things protocols and LPWAN technologies.

Advanced Sensors and Actuators

Sensing has widened faster than computing in some respects. MEMS fabrication has driven inertial measurement units, microphones, pressure sensors, and environmental sensors to costs and sizes that permit their inclusion almost anywhere. Millimeter-wave radar now performs presence detection and gesture sensing without a camera, which sidesteps the privacy objections that limit vision in domestic and medical settings. Single-photon avalanche diode arrays provide direct time-of-flight ranging in a package small enough for a handset. Event-based vision sensors, as noted above, report per-pixel changes with microsecond latency instead of frames.

Actuation has advanced more quietly. Piezoelectric elements deliver sub-micron positioning in optics and precision instruments, electroactive polymers offer compliant motion that suits soft robotics and haptics, and MEMS micromirrors steer beams in projection and lidar. The engineering problem in both directions is rarely the transducer alone: it is the analog front end, calibration across temperature and lifetime, and the fusion of several imperfect sensors into one usable estimate. See MEMS integration and vision and image processing.

Energy Harvesting and Ultra-Low-Power Operation

Two trends meet to make battery-free operation practical. Harvesting sources have improved, with indoor photovoltaic cells, thermoelectric generators, piezoelectric and electromagnetic vibration harvesters, and RF rectennas supplying anywhere from microwatts to a few milliwatts depending on the environment. At the same time, microcontroller standby currents have fallen to tens or hundreds of nanoamps in modes that retain RAM and a real-time clock, and analog front ends have adopted duty-cycled and subthreshold operation.

The design style that results is intermittent computing: the device sleeps, accumulates charge in a capacitor or thin-film cell, wakes to sample and transmit, and returns to sleep. Because the supply may fail mid-computation, software must checkpoint state to non-volatile memory and resume correctly, which is where fast persistent memory earns its cost. Power-management circuits handle the rest, with cold-start circuits that boot from a few hundred millivolts, or from tens of millivolts in transformer-coupled designs, and maximum-power-point tracking that extracts as much as the source will give. Batteryless NFC- and RFID-powered sensors take the approach to its limit, drawing all of their energy from the interrogating reader. Further detail appears in ultra-low power computing and low-power design techniques.

Post-Quantum Cryptography

A cryptographically relevant quantum computer running Shor's algorithm would break RSA and elliptic-curve cryptography, which together protect nearly every firmware signature and secure channel in the field today. Embedded systems feel the deadline earlier than most, because a controller installed in a vehicle, a meter, or a factory may still be running its original root of trust fifteen or twenty years from now, and because harvested ciphertext can be decrypted later even if the device itself is retired.

The standards now exist. In August 2024, NIST published FIPS 203, specifying ML-KEM for key encapsulation, and FIPS 204 and FIPS 205, specifying the ML-DSA and SLH-DSA signature schemes; these derive from the CRYSTALS-Kyber, CRYSTALS-Dilithium, and SPHINCS+ submissions respectively. Two additions are still in progress: FN-DSA, the FALCON-based signature scheme intended for FIPS 206, remains in draft, and in March 2025 NIST selected HQC as a backup key-encapsulation mechanism built on error-correcting codes rather than lattices, with a draft standard expected in 2026 and a final version in 2027. For firmware signing specifically, the stateful hash-based schemes LMS and XMSS, approved earlier in NIST SP 800-208, are already deployed, since their security rests on hash functions alone and their statefulness is manageable when a single signing authority controls the process.

The engineering burden falls on size and time rather than on algorithm choice. An ML-KEM-768 public key runs to roughly 1.2 kilobytes and its ciphertext to about 1.1 kilobytes, an ML-DSA signature to a few kilobytes, and an SLH-DSA signature from several kilobytes to tens of kilobytes. On a device whose entire boot region is measured in tens of kilobytes, those figures change the flash budget, the over-the-air update payload, and the boot time. The practical response is crypto-agility: design the boot chain and the update format so that algorithms can be replaced without replacing the hardware, and support hybrid schemes that combine a classical and a post-quantum algorithm during the transition. See quantum-resistant cryptography and cryptographic implementations.

Secure Hardware Foundations

Post-quantum algorithms are worthless without hardware to anchor them. A hardware root of trust holds an immutable public key or its hash and verifies the first stage of firmware before releasing the processor, establishing the chain that secure boot and attestation extends through the rest of the software stack. Isolated execution environments, such as Arm TrustZone partitions or a dedicated security subsystem, keep keys and sensitive computation away from application code. Physical unclonable functions derive a device-unique key from manufacturing variation, so that no secret is stored in non-volatile memory to be read out. Hardware security modules and secure elements provide the same protections as discrete parts where the main processor cannot.

Regulation has turned these from differentiators into requirements. The European Union's Cyber Resilience Act entered into force in December 2024; its vulnerability and incident reporting obligations apply from September 2026, and its main obligations from December 2027, covering products with digital elements sold in the Union. The Radio Equipment Directive's delegated cybersecurity requirements impose related duties on connected radio equipment, and sector regulators in medical devices and automotive apply their own. The practical consequence for engineering teams is that secure boot, signed and revocable firmware updates, a software bill of materials, and a documented vulnerability-handling process are now scope items on the schedule rather than optional hardening.

Model-Based Development

Model-based development raises the level of abstraction at which behavior is specified. Teams capture control laws, state machines, and data flows as executable models, simulate them against a plant model long before hardware exists, and then generate production source code from the same artifacts. The payoff is earliest-possible verification and a traceable path from requirement to executable, which safety standards reward directly. The constraints are equally concrete: code generators must be qualified for use in a certified process, generated code can be harder to review and to fit in tight memory, and the model becomes the authoritative artifact, which changes how teams review and version their work. Related material appears under system modeling and architecture.

Digital Twins and Simulation

A digital twin is a model of a physical system kept synchronized with that system through live sensor data. The value lies in comparison: when observed behavior diverges from what the model predicts, the divergence itself is the diagnostic signal, which supports predictive maintenance and fault isolation without additional instrumentation. In development, the same modeling investment supports virtual platforms, in which instruction-accurate simulators such as QEMU and Renode run real firmware against modeled peripherals, letting software teams start months before silicon arrives and reproduce failures deterministically. Hardware-in-the-loop testing closes the remaining gap by running real controllers against simulated plants at full rate. The limitation is inherent: a twin is only as good as its model and its data, and an unvalidated twin substitutes confident predictions for measurements. See also system modeling and simulation.

DevOps for Embedded Systems

Continuous integration adapts awkwardly but productively to firmware. A mature pipeline builds reproducibly with a pinned toolchain, runs unit tests for hardware-independent logic on the host, exercises the full image on an emulator, and then runs the same image on a rack of real boards, a hardware-in-the-loop farm, that provides the timing and peripheral behavior no simulator fully reproduces. Static analysis, coding-standard checks, and generation of a software bill of materials run alongside the build. Delivery closes the loop through over-the-air update: dual-bank or A/B images with automatic rollback, staged rollouts to limit the blast radius of a bad release, and signature verification anchored in the hardware root of trust. The constraints that make embedded different remain, and updating a device that controls a moving machine requires interlocks that no web deployment needs. See version control and CI/CD and testing and verification.

Rust and Memory-Safe Languages

Memory-safety defects account for a large share of the exploitable vulnerabilities found in systems software, and national security agencies have publicly urged a move toward memory-safe languages. Rust is the leading candidate for embedded work because it achieves safety without a garbage collector or a runtime. Its ownership and borrowing rules are enforced at compile time, which eliminates use-after-free, double-free, and most buffer overflows, and its type system extends the same discipline to concurrency, catching data races before the program runs.

The embedded ecosystem has matured accordingly. The no_std subset targets bare metal, the embedded-hal traits provide portable peripheral abstractions, and concurrency frameworks such as RTIC and Embassy offer interrupt-driven and asynchronous execution models suited to microcontrollers. Qualified toolchains, notably Ferrocene, have been certified against functional-safety standards including ISO 26262 and IEC 61508, removing a longstanding obstacle to use in safety-related products, and the Linux kernel has accepted Rust code since version 6.1.

Adoption remains gradual for practical reasons. Compiler support does not reach every exotic architecture that C reaches, existing codebases and certified libraries are written in C, memory-mapped register access still requires unsafe blocks that the compiler cannot check, and teams need time to absorb the borrow checker. Most organizations therefore introduce Rust incrementally, in new modules or in the parsing and networking code where memory-safety defects concentrate, while C remains under disciplined coding standards such as MISRA C.

Formal Verification

Testing shows the presence of defects; formal methods can show their absence within a stated model. Three techniques dominate practice. Abstract interpretation proves that a program is free of specific runtime errors, such as overflow or out-of-bounds access, across all executions, and tools of this class have been applied to flight-control software. Model checking exhaustively explores the state space of a protocol or state machine to establish freedom from deadlock or violation of an invariant. Theorem proving offers the strongest result and the highest cost, as demonstrated by the seL4 microkernel, whose implementation carries a machine-checked proof of functional correctness against its specification.

The economics have improved enough that formal methods now appear selectively rather than exclusively. Certification frameworks recognize them explicitly, and DO-333 defines how formal methods may substitute for certain testing objectives in airborne software developed under DO-178C. The realistic pattern is targeted application: prove the properties of a small, critical kernel, a cryptographic primitive, or an arbitration protocol, and test the remainder. Related material appears under functional safety standards.