Electronics Guide

Electrical Failure Analysis

Electrical failure analysis uses electrical measurements and characterization techniques to diagnose failures in electronic components and assemblies. Unlike physical analysis methods that may require destructive sample preparation, electrical techniques can often locate and characterize failures while preserving the sample for further investigation. This makes electrical analysis typically the first step in the failure analysis sequence.

This article explores the range of electrical failure analysis techniques, from basic parametric testing and curve tracing to advanced methods like emission microscopy and thermal imaging. Understanding these tools and their applications enables analysts to efficiently localize failures and determine the electrical nature of defects before proceeding to physical analysis.

Parametric Testing

Parametric testing measures fundamental electrical characteristics to identify deviations from specifications that indicate failure or degradation.

DC Parameter Testing

Basic DC measurements reveal many common failure modes:

  • Supply current (IDD/ICC): Elevated quiescent current may indicate gate oxide damage, latch-up, or internal shorts.
  • Leakage currents: Junction leakage, gate leakage, or insulation breakdown appear as excessive current under reverse bias or with floating inputs.
  • Input/output voltage thresholds: Shifts indicate transistor degradation or electrostatic discharge (ESD) damage.
  • Output drive capability: Reduced current drive suggests transistor damage or increased on-resistance.
  • Pin-to-pin resistance: Opens and shorts detected by resistance measurements.

Comparison to known good devices and datasheet specifications quickly identifies out-of-specification parameters.

AC Parameter Testing

Dynamic measurements characterize high-frequency behavior:

  • Propagation delay: Increased delays may indicate degraded transistors or resistive defects.
  • Rise and fall times: Slower edges suggest drive capability issues or excessive loading.
  • Setup and hold times: Timing margin degradation in sequential circuits.
  • Frequency response: Bandwidth reduction in amplifiers or filters.
  • Clock jitter: Timing instability in clock circuits.

Test System Considerations

Effective parametric testing requires:

  • Force and measure accuracy: Precision voltage and current sourcing with accurate measurement capability.
  • Kelvin connections: Four-wire sensing for accurate low-resistance measurements.
  • Guarding: Eliminating leakage paths for sensitive current measurements.
  • Temperature control: Many parameters are temperature-sensitive; consistent conditions enable meaningful comparisons.

Curve Tracing

Curve tracers apply swept voltage or current stimuli while measuring the response, displaying the characteristic I-V curve of a device or junction.

Junction Characterization

I-V curves reveal junction behavior:

  • Normal diode characteristics: Forward voltage drop, reverse breakdown voltage, and leakage current.
  • ESD damage signatures: Soft breakdown, increased leakage, or shifted characteristics indicate ESD damage to protection structures or input/output circuits.
  • Shorts: Ohmic behavior instead of rectifying characteristic.
  • Opens: No current flow regardless of voltage.
  • Resistive defects: Increased forward voltage drop or series resistance.

Transistor Curve Tracing

Family of curves with varying base/gate drive reveals transistor characteristics:

  • Gain (beta/gm): Relationship between control input and output current.
  • Breakdown voltages: Collector-emitter or drain-source breakdown.
  • Saturation characteristics: On-resistance and saturation voltage.
  • Leakage: Off-state current.

Comparison to good devices reveals degradation even when devices still function within specification limits.

Pin-Level Analysis

Systematic curve tracing of all pins identifies:

  • Pin-to-ground characteristics: ESD protection diode behavior on each pin.
  • Pin-to-supply characteristics: Upper protection diode and pull-up structures.
  • Pin-to-pin characteristics: Internal connections, multiplexed signals, or cross-coupled failures.

Functional Testing

Functional testing applies actual operating conditions to verify circuit operation.

Test Vector Application

Applying known input patterns and checking outputs:

  • Pattern matching: Comparing actual outputs to expected results identifies failing vectors.
  • Shmoo plotting: Varying supply voltage and timing to map operating margins.
  • At-speed testing: Verifying operation at intended frequencies.
  • Boundary scan: JTAG access for board-level testing.

Marginal Analysis

Stressing operating conditions reveals weaknesses:

  • Voltage margining: Reducing supply voltage reveals circuits with reduced noise margins.
  • Temperature testing: Hot and cold testing exposes temperature-sensitive failures.
  • Frequency sweeping: Finding the frequency at which failures occur identifies timing-related problems.

Fault Isolation

Narrowing down failure location through functional tests:

  • Block isolation: Testing functional blocks independently when possible.
  • Signature analysis: Comparing test signatures to identify deviating circuits.
  • Error pattern analysis: Using the pattern of failing vectors to deduce failure location.

Emission Microscopy

Emission microscopy detects photons emitted from semiconductor devices during operation, enabling non-invasive failure localization.

Light Emission Mechanisms

Semiconductors emit light through several mechanisms:

  • Forward-biased junctions: Radiative recombination in forward-biased p-n junctions, stronger in direct bandgap materials but detectable in silicon.
  • Saturated transistors: Light emission from operating transistors.
  • Hot carrier emission: High-energy carriers in strong electric fields emit photons, indicating potential reliability problems.
  • Avalanche emission: Impact ionization in breakdown regions produces bright emission.
  • Leakage paths: Anomalous emission from unexpected locations indicates defects.

Photon Emission Microscopy (PEM)

PEM systems use sensitive cameras to detect emission:

  • CCD cameras: Cooled CCD sensors for high sensitivity.
  • InGaAs detectors: Extended wavelength sensitivity for backside analysis through silicon.
  • Time-resolved detection: Gating emission detection to specific clock phases for dynamic analysis.

Backside emission microscopy through the thinned silicon substrate is essential for modern flip-chip devices where the active surface is inaccessible from the front.

Emission Analysis Applications

  • Defect localization: Identifying the location of shorts, leakage paths, or damaged junctions.
  • Gate oxide integrity: Detecting hot carrier injection sites indicating oxide stress.
  • Latch-up detection: Localizing the trigger and holding regions of latch-up.
  • Logic state verification: Confirming internal node states during operation.

Thermal Imaging and Analysis

Thermal techniques detect heat generated by current flow, enabling localization of shorts, high-resistance defects, and excessive power dissipation.

Infrared Thermography

IR cameras image thermal radiation from device surfaces:

  • Steady-state imaging: Continuous power application shows equilibrium temperature distribution.
  • Hot spot detection: Elevated temperatures indicate shorts, high current paths, or failing components.
  • Comparative analysis: Temperature differences between good and failing devices reveal problem areas.

Sensitivity is typically around 0.1 degrees Celsius with spatial resolution limited by IR wavelength (typically 3-5 or 8-12 micrometers).

Lock-In Thermography

Modulating the stimulus and synchronously detecting the thermal response improves sensitivity:

  • Improved sensitivity: Lock-in detection can achieve millikelvin temperature resolution.
  • Phase information: Phase delay between stimulus and thermal response indicates defect depth.
  • Elimination of background: DC thermal background is rejected, highlighting stimulus-correlated heating.

OBIRCH and TIVA

Laser-based thermal techniques provide high-resolution failure localization:

  • OBIRCH (Optical Beam Induced Resistance Change): A scanned laser locally heats the sample while monitoring current change. Metallic defects (voids, high-resistance contacts) show current changes when heated.
  • TIVA (Thermally Induced Voltage Alteration): Similar to OBIRCH but monitors voltage changes at constant current, effective for localizing shorts.
  • Resolution: Sub-micrometer localization possible with focused laser beams.

Laser-Based Techniques

Lasers enable several powerful failure analysis techniques beyond thermal methods.

OBIC and LIVA

Optical beam techniques using photon absorption:

  • OBIC (Optical Beam Induced Current): Photogenerated carriers in semiconductor junctions produce measurable current. Scanning while monitoring current maps junction locations and identifies damaged junctions or leakage sites.
  • LIVA (Light Induced Voltage Alteration): Monitoring voltage change at constant current when illuminating the device. Sensitive to both resistive and junction defects.

Laser Voltage Probing

Non-contact measurement of internal node voltages:

  • Principle: Laser beam reflected from silicon is modulated by the electric field at the surface, which varies with underlying circuit voltage.
  • Backside probing: Access through thinned substrate enables probing of flip-chip devices.
  • Time-resolved measurements: Stroboscopic techniques enable timing measurements with picosecond resolution.

Laser Stimulation Techniques

  • Soft defect localization (SDL): Local heating or carrier injection from a scanned laser changes the state of marginal flip-flops or memory cells, localizing sensitivity.
  • Laser-assisted device alteration (LADA): Intentional modification of device behavior for debug or analysis.

Time-Domain Reflectometry

TDR measures impedance variations along transmission paths by analyzing reflected signals from a fast pulse.

TDR Principles

  • Impedance discontinuities: Changes in impedance cause reflections that appear at specific time delays corresponding to distance.
  • Opens and shorts: Opens produce positive reflections; shorts produce negative reflections.
  • Resistive faults: Intermediate reflection amplitudes indicate resistive changes.
  • Spatial resolution: Determined by pulse rise time; sub-nanosecond edges enable millimeter resolution.

Package and Board-Level TDR

TDR applications at the assembly level:

  • Bond wire opens: Missing or broken wire bonds appear as characteristic impedance changes.
  • Solder joint failures: Open or high-resistance joints produce reflection signatures.
  • PCB trace defects: Cracks, opens, or impedance variations along traces.
  • Connector issues: Contact resistance or mechanical problems in connectors.

Magnetic Field Imaging

Current flow produces magnetic fields that can be imaged to map current paths.

SQUID Microscopy

Superconducting Quantum Interference Device sensors provide extremely sensitive magnetic field detection:

  • Current imaging: Mapping DC and AC currents in packages and PCBs.
  • Short localization: Finding the path of short circuit current.
  • Non-contact measurement: No electrical connection required.

Magneto-Optical Imaging

Faraday rotation in indicator films visualizes magnetic fields:

  • Current distribution: Visualizing current spreading in metallization.
  • Defect localization: Current crowding around defects.

Electrical Failure Analysis Workflow

Effective electrical failure analysis follows a systematic approach.

Initial Assessment

  1. Review failure information: Symptoms, conditions, and history.
  2. Visual inspection: External damage, discoloration, or contamination.
  3. Basic electrical checks: Supply current, pin-to-pin resistance, ground continuity.

Characterization Phase

  1. Parametric testing: Comprehensive DC and AC measurements.
  2. Curve tracing: I-V characteristics of all pins.
  3. Functional testing: Verify reported failure and characterize symptoms.
  4. Comparison to good device: Identify deviations from normal behavior.

Localization Phase

  1. Emission microscopy: Detect anomalous light emission.
  2. Thermal imaging: Find hot spots or abnormal heating patterns.
  3. Laser-based techniques: Localize resistive or junction defects.
  4. TDR: Identify interconnect faults.

Documentation

  • Record all measurements: Data supports conclusions and enables comparison.
  • Capture images: Emission, thermal, and optical images document findings.
  • Note conditions: Temperature, bias, timing, and other test conditions.

Case Study: Supply Current Failure

A microcontroller exhibited excessive supply current, drawing 100 mA instead of the expected 20 mA. The analysis sequence:

  1. Curve tracing: All I/O pins showed normal ESD protection diode characteristics. Supply pins showed linear (ohmic) behavior instead of expected diode characteristic, indicating an internal short.
  2. Emission microscopy: Strong localized emission from one area of the die.
  3. Lock-in thermography: Confirmed hot spot at the same location.
  4. Localization: Defect location corresponded to a transistor in the power management circuit.
  5. Physical analysis: Cross-section revealed gate oxide rupture, consistent with ESD damage or oxide defect.
  6. Root cause: ESD event during handling caused oxide breakdown, creating a resistive path from supply to ground.

Summary

Electrical failure analysis provides essential tools for diagnosing electronic failures. Beginning with basic parametric testing and curve tracing, analysts can characterize the electrical nature of failures and often narrow down the problem area. Advanced techniques including emission microscopy, thermal imaging, and laser-based methods enable precise localization of defects within integrated circuits.

The non-destructive nature of most electrical techniques makes them ideal first steps in failure analysis. Information gathered electrically guides subsequent physical analysis, ensuring that destructive sample preparation targets the correct location and preserves evidence of the failure mechanism.

Success in electrical failure analysis requires understanding both the techniques available and the physics of how defects manifest electrically. Combined with systematic methodology and thorough documentation, electrical failure analysis skills enable efficient diagnosis of even complex failures in modern electronic devices.