Electronics Guide

The Physical Mechanism

When a signal travels along a transmission line with characteristic impedance Z₀ and encounters a termination or discontinuity with impedance Z_L, the boundary conditions require continuity of voltage and current. However, the different impedances cannot simultaneously satisfy these conditions with only the incident wave. To maintain electromagnetic boundary conditions, a reflected wave is generated that travels back toward the source.

The incident wave carries energy forward with specific voltage and current relationships determined by the line impedance. At the discontinuity, the load impedance imposes different voltage-current relationships. The reflected wave adjusts the total voltage and current at the boundary to satisfy both the transmission line equations and the load impedance simultaneously.

Key concepts in reflection physics include:

• Incident wave: The original signal traveling toward the discontinuity, with voltage V_i and current I_i related by the characteristic impedance
• Reflected wave: The portion of signal energy bouncing back, with voltage V_r and current I_r
• Transmitted wave: The signal energy that continues past the discontinuity (in multi-section systems)
• Voltage superposition: The total voltage at any point equals the sum of incident and reflected wave voltages
• Current superposition: The total current equals the incident current minus the reflected current (due to opposite propagation direction)

Energy Conservation

Reflections obey energy conservation principles. The incident power must equal the sum of reflected power and absorbed power in the load. For a lossless transmission line, no energy is lost during propagation, so all incident energy either reflects back or dissipates in the load impedance.

The power relationships are expressed as:

• P_incident = (V_i)² / Z₀
• P_reflected = (V_r)² / Z₀
• P_absorbed = P_incident - P_reflected

Perfect impedance matching (Z_L = Z₀) results in zero reflected power, with all incident energy absorbed by the load. Conversely, an open circuit (Z_L = ∞) or short circuit (Z_L = 0) reflects all incident energy back with different phase relationships.

Mathematical Definition

The voltage reflection coefficient (Γ, Greek letter gamma) is defined as the ratio of reflected voltage to incident voltage at the discontinuity:

Γ = V_r / V_i = (Z_L - Z₀) / (Z_L + Z₀)

Where:

• Γ = voltage reflection coefficient (dimensionless, -1 to +1 for real impedances)
• V_r = reflected voltage wave amplitude
• V_i = incident voltage wave amplitude
• Z_L = load impedance at the discontinuity
• Z₀ = characteristic impedance of the transmission line

The current reflection coefficient has the same magnitude but opposite sign: Γ_i = -Γ. This sign difference reflects the fact that reflected current flows in the opposite direction to incident current.

Special Cases and Boundary Conditions

Several important cases illustrate reflection behavior:

• Matched load (Z_L = Z₀): Γ = 0, no reflection occurs, all energy absorbed by load
• Open circuit (Z_L = ∞): Γ = +1, voltage doubles at open end, current becomes zero
• Short circuit (Z_L = 0): Γ = -1, voltage becomes zero, current doubles at short
• Purely resistive mismatch: 0 < |Γ| < 1, partial reflection with no phase shift beyond 0° or 180°
• Reactive load (complex Z_L): Complex Γ with magnitude ≤ 1, reflection includes phase shift

For a 50-ohm transmission line terminated with various loads:

• 25-ohm load: Γ = (25-50)/(25+50) = -0.33, about 33% reflection with inverted polarity
• 75-ohm load: Γ = (75-50)/(75+50) = +0.20, about 20% reflection with same polarity
• 100-ohm load: Γ = (100-50)/(100+50) = +0.33, about 33% reflection with same polarity

Return Loss and Related Metrics

The reflection coefficient relates to several commonly used signal integrity metrics:

Return Loss (RL) expresses the reflected power as a negative decibel value:

RL = -20 × log₁₀(|Γ|) dB

Higher return loss (more negative dB) indicates better impedance matching. For example, Γ = 0.1 corresponds to RL = 20 dB, while Γ = 0.01 gives RL = 40 dB. Typical design targets range from 15 dB (moderate quality) to 30+ dB (high-performance systems).

Voltage Standing Wave Ratio (VSWR) describes the voltage variation along a mismatched line:

VSWR = (1 + |Γ|) / (1 - |Γ|)

A perfectly matched line has VSWR = 1:1, while increasing mismatch produces higher ratios like 1.5:1, 2:1, or worse. VSWR directly relates to the maximum and minimum voltage amplitudes observed along the transmission line.

Termination Mismatches

The most obvious source of reflections is improper line termination. When a transmission line ends at a component or connector whose input impedance differs from the line's characteristic impedance, reflections occur.

Common termination scenarios include:

• Unterminated lines: High-impedance CMOS inputs (megaohms) approximate open circuits, causing nearly full reflection (Γ ≈ 1)
• Capacitive loads: IC input capacitance creates frequency-dependent impedance, appearing high at low frequencies but decreasing at high frequencies
• Wrong resistor value: Using 75-ohm termination on a 50-ohm line produces 20% reflections
• Series termination at wrong end: Series resistors should be placed at the source, not the load
• Temperature-dependent resistance: Resistor tolerance and temperature coefficients cause impedance variations

Trace Geometry Changes

PCB trace geometry directly determines characteristic impedance. Any change in trace dimensions creates an impedance discontinuity and potential reflection point.

Geometric mismatch sources include:

• Width changes: Transitioning from 5-mil to 10-mil trace width alters impedance, potentially by 10-20 ohms depending on stackup
• Layer transitions: Moving from outer layer (microstrip) to inner layer (stripline) changes field distribution and impedance
• Reference plane gaps: Breaks in ground or power planes under signal traces dramatically increase local impedance
• Copper weight variation: Different copper thickness between layers affects trace cross-section
• Routing corners: Sharp 90-degree bends create local impedance changes, though effects are minor at moderate frequencies

Modern PCB design tools include impedance calculators that account for trace width, height, dielectric properties, and reference plane spacing. Maintaining consistent geometry is essential for controlled impedance routing.

Dielectric Property Variations

The dielectric constant (εr) of PCB substrate material directly affects characteristic impedance through the relationship Z₀ ∝ 1/√εr. Any spatial or frequency variation in dielectric properties causes impedance changes.

Dielectric-related mismatches include:

• Material transitions: Moving from FR-4 (εr ≈ 4.3) to Rogers 4350B (εr ≈ 3.5) changes impedance by approximately 10%
• Prepreg thickness variation: Manufacturing tolerances in dielectric thickness affect impedance
• Frequency dispersion: Dielectric constant decreases with frequency in most materials, causing impedance to rise at higher frequencies
• Moisture absorption: Humid environments increase effective dielectric constant, lowering impedance
• Temperature effects: Dielectric properties change with temperature, typically increasing εr as temperature rises

Series and Shunt Stubs

Stubs appear in two primary configurations:

Series stubs exist in-line with the signal path, such as when a trace continues past a via pad or component connection point. The continuing section of trace forms a stub that resonates at frequencies where the stub length equals quarter-wavelengths.

Shunt stubs branch off the main signal path perpendicular to signal flow. Common examples include via stubs below PCB pads, unused connector pins, and test point traces. These stubs appear as parallel elements that create reflections traveling back to the main line.

Stub resonance occurs when the electrical length equals odd multiples of quarter-wavelengths. For an open-ended stub, these resonances transform the high impedance at the end into a low impedance at the junction, creating a notch in transmission. The resonant frequencies are approximately:

f_resonant = (2n - 1) × v / (4 × L_stub)

Where n = 1, 2, 3... for successive resonances, v is propagation velocity, and L_stub is physical stub length.

Via Stubs

Vias create particularly problematic stubs in multi-layer PCBs. When a signal transitions from one layer to another, the via barrel typically extends through the entire board thickness. The unused portion of via beyond the destination layer forms a stub that radiates and reflects signals.

For a 62-mil thick PCB with εr = 4, a full via stub has electrical length corresponding to resonance near:

f = 0.25 × (12 inches/nanosecond / 2) / 0.062 inches ≈ 24 GHz

This might seem safely above typical digital signal bandwidths, but harmonics of fast edge rates extend well into the GHz range. A 1-ns rise time contains significant energy beyond 1 GHz where via stubs become problematic.

Mitigation techniques include:

• Back-drilling: Mechanically removing the unused via stub after plating, reducing stub length to just the layer transition
• Blind vias: Vias that only extend partway through the board, eliminating stubs entirely
• Buried vias: Layer-to-layer connections that don't reach outer surfaces
• Via-in-pad: Placing vias directly under BGA pads minimizes trace stubs to the via location
• Cavity-back vias: Removing copper from unused pad layers to reduce capacitive loading

Component Lead and Pad Stubs

Surface mount component pads and through-hole component leads create small but significant stubs at high frequencies. The pad area beyond the actual connection point acts as a short transmission line stub.

Consider a 50-mil long SMT resistor pad: at 10 GHz, this represents roughly 30 degrees of electrical length, enough to cause measurable reflection and phase shift. For precision high-frequency circuits, pad dimensions must be carefully controlled.

Through-hole components present even larger stub problems, as component leads extend through the board and may protrude on the opposite side. The combination of lead inductance and stub effects limits through-hole component usage in high-speed designs.

Via Barrel Impedance

The via barrel itself has characteristic impedance different from the connected traces. Via impedance depends on barrel diameter, anti-pad opening in reference planes, and the number and spacing of nearby ground vias.

A typical via structure might have:

• Barrel diameter: 10 mils (after plating)
• Anti-pad diameter: 20 mils (clearance in reference planes)
• Pad diameter: 20 mils (on signal layers)

This geometry produces via impedance often in the 40-60 ohm range, lower than typical 50-ohm or 100-ohm differential traces. The impedance mismatch creates reflections at both the entrance and exit of the via transition.

Via impedance approximation (simplified model):

Z_via ≈ (60 / √εr) × ln(D_antipad / D_barrel)

Where D_antipad is the anti-pad diameter in reference planes and D_barrel is the via barrel diameter. More accurate calculations require 3D field solvers accounting for pad geometry, nearby ground vias, and reference plane stackup.

Capacitive and Inductive Effects

Vias exhibit both capacitive and inductive parasitics that affect signal transmission:

Via capacitance arises from the pad area on each layer, acting as a parallel-plate capacitor to adjacent reference planes. Total via capacitance equals the sum of contributions from all layers:

C_via ≈ Σ (ε₀ × εr × A_pad / h)

Where A_pad is pad area, h is dielectric thickness to reference plane, and the sum includes all layers. Typical values range from 0.3 to 1.0 pF depending on layer count and pad sizes.

Via inductance results from current flowing through the via barrel. The inductance depends on via length (board thickness) and return path geometry. With nearby ground vias providing return current paths, via inductance typically ranges from 0.3 to 1.5 nH.

L_via ≈ (μ₀ / 2π) × h × ln(4h / D_barrel)

This approximation assumes a single ground return via; closer ground vias reduce inductance by providing shorter return paths.

The combination of capacitance and inductance creates resonances and complex frequency-dependent impedance behavior. At low frequencies, capacitance dominates (high impedance); at high frequencies, inductance dominates (low impedance).

Return Current Path Discontinuities

When a signal via transitions between layers, the return current must also transition between reference planes. If no dedicated ground via exists nearby, return current must flow laterally to find a distant via, creating a large current loop with high inductance.

Best practices for via return paths include:

• Ground via placement: Position ground vias within 20-30 mils of signal vias to provide low-inductance return paths
• Symmetry in differential pairs: Place ground vias symmetrically between differential pair vias to maintain impedance balance
• Via stitching: Connect adjacent reference planes with via arrays to provide multiple return current paths
• Coaxial via structures: Surround high-speed signal vias with rings of ground vias for the ultimate in return path control

Connector Impedance Characteristics

High-speed connectors are designed with target characteristic impedances matching common system impedances (50 ohms single-ended, 85-100 ohms differential). However, achieving consistent impedance through the complex 3D connector geometry presents significant challenges.

Connector impedance variations arise from:

• Pin geometry: Contact shape, plating thickness, and pin-to-pin spacing determine impedance through the connector body
• Dielectric material: Connector plastic housings have different dielectric constants than PCB substrate
• Ground structure: Ground pin placement and internal shielding affect field distribution
• PCB launch: The transition from PCB trace to connector footprint creates a localized impedance change
• Mating discontinuity: The contact point between mating connectors introduces mechanical and electrical variability

Even well-designed connectors rarely maintain impedance better than ±10% through their structure. A connector specified for 100-ohm differential impedance might vary from 90 to 110 ohms along its length, creating multiple reflection points.

Connector Stub and Crosstalk Issues

Multi-pin connectors create additional problems beyond simple impedance discontinuity:

Unused pin stubs: Connectors with more pins than actively used signals create stubs from every unused contact. These stubs couple to active signals through mutual capacitance and inductance, causing both reflections and crosstalk.

Pin-to-pin coupling: Adjacent pins in dense connectors couple electromagnetic energy between signals. This crosstalk appears as additional noise and creates reflections when coupled signals encounter mismatches.

Ground bounce: Shared ground pins carry return currents for multiple signals. Simultaneous switching creates voltage variations on ground pins, appearing as common-mode noise that reflects at mismatches.

Connector manufacturers address these issues through:

• Increased ground-to-signal pin ratios (1:1 or higher for critical applications)
• Differential pair routing optimization within the connector
• Internal shielding structures to reduce crosstalk
• Carefully controlled impedance through precision manufacturing
• Shortened connector bodies to minimize discontinuity length

Cable Connector Interfaces

When cables connect between two boards, the complete signal path includes:

• PCB trace 1 (source board)
• Connector 1 on source board
• Cable assembly with its own impedance
• Connector 2 on destination board
• PCB trace 2 (destination board)

Each transition creates potential mismatches. For example, a system might use 50-ohm PCB traces, connectors varying from 45-55 ohms, and cable impedance of 50 ±5 ohms. The accumulated reflections degrade signal quality, particularly if impedance changes occur in the same direction at multiple points.

Proper cable assembly design includes impedance matching at both ends, typically through careful PCB layout at the connector footprint. Some designs use back-terminated traces or series resistance to damp reflections from cable connector systems.

Wire Bond Transitions

Traditional wire-bonded packages use thin gold or copper wires (typically 1-2 mil diameter) to connect die pads to package leads or substrate traces. These wire bonds introduce significant inductance and impedance discontinuities.

Wire bond inductance approximates 1 nH per millimeter of length. A typical 3mm bond wire carries 3 nH inductance, creating substantial impedance at high frequencies. At 10 GHz, a 3 nH inductance presents 188 ohms of reactance, far exceeding typical system impedances.

The high inductance causes several problems:

• Reflection at the bond: The inductive impedance mismatches with both the die and package impedances
• Resonances: Bond wire inductance resonates with pad capacitances, creating frequency-dependent behavior
• Ground bounce: Shared ground bond wires carry return current for multiple signals, creating common impedance coupling
• Simultaneous switching noise: Multiple drivers switching together create voltage variations through bond wire inductance

Wire bond limitations restrict their use in applications above a few GHz. Multiple parallel bond wires reduce inductance but cannot overcome fundamental geometric constraints.

Flip-Chip and Controlled Collapse Chip Connection

Flip-chip technology directly connects die pads to package substrate through solder bumps, eliminating wire bonds. The much shorter connection length (typically 50-100 microns) dramatically reduces inductance to approximately 50-100 pH per bump.

Flip-chip advantages for signal integrity include:

• Low inductance: Short bump height provides minimal series inductance
• Controlled impedance: Bump array geometry can be designed for specific impedance characteristics
• Dense ground distribution: Ground bumps interspersed with signal bumps provide excellent return paths
• Reduced package size: Eliminates peripheral wire bond area, allowing smaller packages

However, flip-chip introduces its own discontinuities. The solder bump itself, typically 100-150 microns in diameter, creates a capacitive element. The transition from on-die metal to bump to package substrate involves multiple material and geometry changes.

Advanced packages use microbump technology with even smaller bumps (20-50 microns), further reducing parasitics for the highest-performance applications.

BGA Package-to-PCB Interface

Ball Grid Array packages connect to PCBs through solder ball arrays on the package underside. The BGA interface introduces impedance discontinuities from multiple sources:

Ball impedance: The solder ball itself has inductance (typically 50-200 pH) and forms part of the signal path. Ball diameter, height, and spacing determine these parasitics.

PCB pad geometry: The circular or square pad on the PCB has different impedance than the connecting trace. Pad diameter is typically 20-30% larger than ball diameter to accommodate placement tolerances.

Via transition: Most BGA connections require vias to escape from the dense ball array to routing layers. These vias add the discontinuities discussed earlier.

Trace fanout: Traces fanning out from the BGA footprint often change width to squeeze between balls, creating impedance variations.

High-speed BGA design requires careful attention to:

• Via-in-pad techniques to minimize stub length
• Controlled impedance trace widths accounting for via and pad discontinuities
• Ground ball placement adjacent to high-speed signals
• Escape routing that maintains differential pair symmetry
• Package substrate design coordinated with PCB design for consistent impedance through the complete path

Reflection Sequence and Timing

When a signal encounters multiple discontinuities, reflections bounce back and forth between mismatches, creating complex waveforms. Each reflection arrives at different times determined by discontinuity spacing and propagation velocity.

Consider a simple example: a source drives a line with characteristic impedance Z₀ that connects to a load Z_L, with a discontinuity of impedance Z_D midway between source and load.

The reflection sequence proceeds as:

1. Initial wave travels from source to midpoint discontinuity
2. Partial reflection at discontinuity returns to source; partial transmission continues to load
3. Transmitted wave reaches load, reflects based on load impedance
4. Load reflection travels back, encountering discontinuity again
5. Discontinuity partially reflects (toward load) and partially transmits (toward source)
6. Wave reaching source reflects based on source impedance
7. Process continues with decreasing amplitude as energy dissipates

Each reflection multiplies by the relevant reflection coefficient at each discontinuity. With typical reflection coefficients of 0.1 to 0.3, reflections decrease rapidly after several round trips.

Reflection Addition and Cancellation

Multiple reflections add vectorially at any point along the transmission line. Depending on timing and polarity, reflections can add constructively (increasing distortion) or destructively (partially canceling).

Critical scenarios include:

Resonant enhancement: When discontinuity spacing equals multiples of half-wavelength, reflections arrive in-phase with incident signals, creating standing wave patterns and voltage peaks. This occurs at frequencies f = n × v / (2 × L), where L is the spacing between discontinuities.

Null points: At odd multiples of quarter-wavelength spacing, certain reflections arrive out-of-phase, potentially canceling. However, this cancellation occurs only at specific frequencies and cannot be relied upon for broadband signals.

Overshoot accumulation: Multiple positive reflections arriving close together in time create voltage overshoot exceeding levels from any single reflection. This is particularly problematic near clock edges where timing is critical.

Ringing: Reflections bouncing between two strong discontinuities (like unterminated source and load) create oscillatory ringing that takes many bit periods to settle.

Dominant Reflection Identification

Not all discontinuities contribute equally to signal degradation. Identifying dominant reflection sources focuses mitigation efforts on the most impactful problems.

Factors determining reflection impact include:

• Reflection coefficient magnitude: Larger impedance mismatches create stronger reflections
• Distance from observation point: Nearby discontinuities affect signal quality more than distant ones due to less attenuation
• Number of reflections: A discontinuity that signals traverse multiple times (like a source termination) impacts quality more than single-pass discontinuities
• Electrical length relative to signal bandwidth: Discontinuities shorter than 1/10 wavelength have less impact than longer discontinuities

Time-domain reflectometry (TDR) measurements identify reflection locations and magnitudes, allowing designers to focus on the worst discontinuities. Simulation tools can also perform sensitivity analysis to rank discontinuity impacts.

Constructing Lattice Diagrams

A lattice diagram uses a two-dimensional graph with:

• Vertical axis: Represents distance along the transmission line, from source (bottom) to load (top)
• Horizontal axis: Represents time, advancing left to right
• Diagonal lines: Represent traveling waves, with slope determined by propagation velocity
• Annotations: Voltage amplitudes or reflection coefficients label each wave segment

Construction procedure:

1. Draw vertical lines at source and load positions
2. Calculate source and load reflection coefficients: Γ_s and Γ_L
3. Draw initial wave from source to load (diagonal line up and right)
4. At load, multiply by (1 + Γ_L) for transmitted voltage, and draw reflection returning (diagonal line down and right) with amplitude × Γ_L
5. At source, multiply returning wave by Γ_s and draw new reflection toward load
6. Continue process until reflections become negligibly small

Each reflection multiplies the previous amplitude by the reflection coefficient at the boundary. For example, with Γ_s = 0.2 and Γ_L = -0.3, the sequence might be: 1.0 (initial), -0.3 (first load reflection), -0.06 (first source reflection), 0.018 (second load reflection), etc.

Reading and Interpreting Lattice Diagrams

Lattice diagrams reveal important system behavior:

Voltage at any point and time: To find the voltage at a specific location and time, draw a vertical line at that time and note all wave segments crossing it at the desired position. Sum all contributions (incident and reflected waves) to obtain total voltage.

Settling time: The time required for reflections to decay to acceptable levels is visible as the point where diagonal lines become too small to distinguish. Systems with small reflection coefficients settle quickly; large mismatches cause prolonged ringing.

Worst-case voltage: Maximum voltage occurs when multiple reflections arrive simultaneously with the same polarity. The diagram shows when and where this occurs.

Effect of source and load impedances: The reflection coefficients Γ_s and Γ_L directly determine how rapidly reflections decay. Matched terminations (Γ = 0) eliminate that end's reflections entirely, visible as diagonal lines stopping at matched boundaries.

Complex System Lattice Diagrams

Lattice diagrams extend to multi-section transmission lines with multiple discontinuities. Each discontinuity adds a vertical line in the diagram where waves partially reflect and partially transmit according to the local reflection and transmission coefficients.

For a system with source impedance Z_s, line 1 with impedance Z₁, discontinuity impedance Z_d, line 2 with impedance Z₂, and load impedance Z_L, the diagram includes reflection coefficients at four boundaries plus two transmission coefficients at the internal discontinuity.

The complexity increases rapidly, but the fundamental principle remains: trace each wave segment, apply appropriate reflection/transmission coefficients at boundaries, and sum all contributions at the point of interest.

Modern simulation tools automate this process, but manually constructing lattice diagrams for simple cases builds intuition about reflection behavior and helps verify simulation results.

Time-Domain Reflectometry

Time-domain reflectometry (TDR) is a measurement technique that sends a fast step voltage into a transmission line and observes the reflected signal. Reflections return from impedance discontinuities at times proportional to their distance from the measurement point.

TDR operating principles:

• Step generation: A pulse generator creates a fast voltage step (typically 50-200 ps rise time) launched into the transmission line
• Reflection observation: An oscilloscope monitors voltage at the launch point, displaying incident plus reflected waves
• Distance calculation: Time delay to reflection corresponds to distance: d = (t × v) / 2, where the factor of 2 accounts for round-trip travel
• Impedance determination: Reflection amplitude indicates impedance change: Z = Z₀ × (1 + Γ) / (1 - Γ)

TDR reveals:

• Open circuits appear as positive steps in reflected voltage
• Short circuits appear as negative steps
• Capacitive loads show gradual voltage rise
• Inductive discontinuities create voltage spikes
• Distributed variations appear as sloped voltage changes

TDR is invaluable for diagnosing PCB fabrication defects, identifying connector problems, and verifying controlled impedance routing. Modern TDR instruments offer sub-mil spatial resolution for detailed discontinuity characterization.

Transient Response Analysis

Digital signals are inherently transient, consisting of edges and transitions rather than steady-state sine waves. Analyzing transient response shows how reflections affect signal quality metrics like rise time, overshoot, and ringing.

Key transient phenomena include:

Edge degradation: Reflections interfere with clean edges, causing staircase-like waveforms as each reflection adds to the transition. Severe reflections can create multiple false crossings of logic thresholds.

Overshoot and undershoot: When reflections arrive during edge transitions with the same polarity as the edge, they add to create voltage excursions beyond final values. Positive overshoot stresses receiver input protection; negative undershoot can forward-bias substrate diodes.

Ringing: Oscillatory behavior from reflections bouncing between discontinuities. Ringing frequency approximately equals v / (2 × L) where L is the round-trip distance between reflecting points. Ringing amplitude depends on reflection coefficient magnitudes.

Inter-symbol interference: In high-speed serial data, reflections from one bit period persist into subsequent bits, causing accumulated distortion. Eye diagram closure results when ISI becomes severe.

Settling Time Calculations

Settling time quantifies how long reflections take to decay to acceptable levels. This parameter determines maximum signaling rate and affects timing budget analysis.

For a transmission line of length L with source reflection coefficient Γ_s and load reflection coefficient Γ_L, each round trip reduces reflection amplitude by the product Γ_s × Γ_L. After n round trips, the reflection amplitude is:

V_n = V_initial × (Γ_s × Γ_L)^n

To settle to within a fraction ε of the final value requires:

n = ln(ε) / ln(|Γ_s × Γ_L|)

Each round trip takes time 2L/v, so total settling time is:

t_settle = (2L/v) × ln(ε) / ln(|Γ_s × Γ_L|)

For example, with L = 10 inches, v = 6 inches/ns, Γ_s = 0.2, Γ_L = -0.3, and settling to within 1% (ε = 0.01):

• Round-trip time = 2 × 10 / 6 = 3.33 ns
• Reflection product = 0.2 × 0.3 = 0.06
• Required round trips = ln(0.01) / ln(0.06) = 1.64 round trips
• Settling time = 3.33 × 1.64 = 5.5 ns

This calculation shows that even moderate mismatches require several round trips for adequate settling, imposing minimum bit period requirements in digital systems.

Impedance Matching

The most fundamental approach eliminates reflections by matching impedances throughout the signal path:

• Parallel termination: Place a resistor equal to Z₀ at the load, absorbing all incident energy (Γ_L = 0)
• Series termination: Add resistance at the source so R_source + R_series = Z₀, preventing re-reflections from the source
• Thevenin termination: Use resistor divider network at load to match impedance while controlling DC voltage levels
• AC termination: Capacitor in series with termination resistor provides AC impedance matching while minimizing DC power consumption

Controlled Impedance Design

Maintaining consistent impedance throughout the signal path prevents reflections from arising:

• Use PCB stackup calculators to design traces with target impedance
• Specify controlled impedance fabrication with testing to verify results
• Avoid unnecessary trace width changes
• Taper transitions smoothly when width changes are unavoidable
• Maintain consistent reference plane distance
• Coordinate PCB, connector, and cable impedances

Discontinuity Minimization

Design practices to reduce unavoidable discontinuities:

• Back-drill via stubs on high-speed signals
• Use blind/buried vias to eliminate through-board stubs
• Minimize connector pin count and eliminate unused pins
• Choose connectors designed for signal integrity in your frequency range
• Compensate via capacitance with series inductance or tapered trace width
• Design component footprints with minimal pad overhang