Power-Induced Jitter

Introduction

Power-induced jitter represents one of the most significant yet often underestimated sources of timing uncertainty in modern electronic systems. As supply voltages decrease and operating frequencies increase, even small variations in the power distribution network can translate into substantial timing errors. Understanding the mechanisms by which power supply noise couples into timing-critical circuits and implementing effective mitigation strategies are essential for achieving reliable, high-performance designs.

Jitter caused by power supply variations manifests across all types of timing circuits, from simple clock buffers to complex phase-locked loops and high-speed serial transceivers. The magnitude of power-induced jitter depends on circuit sensitivity, power distribution network quality, and the effectiveness of isolation and filtering techniques. In many modern systems, power-induced jitter constitutes a dominant component of total system jitter, making it a critical consideration in timing budget analysis.

Fundamental Mechanisms

Supply Noise Sensitivity

All active circuits exhibit some degree of sensitivity to supply voltage variations. The fundamental relationship between supply voltage and circuit behavior creates multiple pathways for power supply noise to induce timing errors:

Threshold Voltage Dependence: Transistor switching thresholds shift with supply voltage changes, directly affecting propagation delays
Drive Strength Modulation: Output driver strength varies with supply voltage, altering signal slew rates and transition times
Bias Point Shifts: In analog circuits, supply variations can shift operating points, affecting gain, bandwidth, and timing characteristics
Reference Voltage Coupling: Comparator and receiver threshold voltages often reference the supply, making timing decisions supply-dependent

The sensitivity of circuit delay to supply voltage is often quantified as the delay sensitivity coefficient, typically expressed in picoseconds per millivolt. This parameter varies widely across different circuit types, with some designs exhibiting sensitivities exceeding 10 ps/mV.

Propagation Delay Variation

The most direct mechanism of power-induced jitter is through modulation of gate and buffer propagation delays. When supply voltage decreases, transistors provide less drive current, resulting in slower charging and discharging of load capacitances. This relationship is approximately linear over small voltage ranges:

Δt_pd ≈ K × ΔV_DD

where K is the delay sensitivity coefficient specific to the circuit. In a chain of gates or buffers, these individual delay variations accumulate, with the total timing uncertainty growing with the number of stages. For a clock distribution network with multiple buffer stages, even modest supply noise can generate significant jitter at the endpoints.

VCO Pushing

Voltage-controlled oscillators are particularly susceptible to power supply noise, a phenomenon known as VCO pushing or supply pushing. The oscillation frequency of a VCO depends on charging currents and threshold voltages, both of which vary with supply voltage. This creates a direct path for supply noise to modulate the output frequency, resulting in phase noise and jitter.

Push Coefficient

The sensitivity of VCO frequency to supply voltage is characterized by the push coefficient or supply sensitivity, typically specified in MHz/V or as a percentage frequency deviation per volt. High-quality VCOs may achieve push coefficients below 1% per volt, while poorly designed oscillators can exhibit sensitivities exceeding 10% per volt.

Jitter Generation Mechanism

Supply noise at the VCO input translates into frequency modulation, which accumulates as phase error over time. A sinusoidal supply disturbance at frequency f_n produces deterministic jitter with amplitude:

J_DJ = (K_push × V_noise) / (f_n × f_VCO)

where K_push is the push coefficient, V_noise is the noise amplitude, and f_VCO is the VCO center frequency. This relationship shows that low-frequency supply noise creates disproportionately large jitter compared to high-frequency noise.

PLLs and Supply Sensitivity

Phase-locked loops exhibit complex behavior in response to supply noise. While the PLL feedback mechanism can suppress some power-induced jitter, the effectiveness depends on loop bandwidth and noise frequency. Supply noise within the PLL loop bandwidth is partially tracked and corrected, but noise beyond the loop bandwidth directly modulates the VCO output. Additionally, supply noise affecting the phase detector, charge pump, or dividers can introduce jitter that the loop cannot correct.

Buffer Delay Modulation

Clock and data buffers throughout a system contribute to power-induced jitter through delay modulation. When multiple buffers share a power domain, supply noise affects all buffers simultaneously, creating correlated jitter that can accumulate through the signal path.

Single-Stage Effects

A single buffer stage converts supply voltage variations directly into timing errors. The magnitude depends on the buffer's delay sensitivity and the supply noise amplitude. For typical CMOS buffers, delay sensitivity ranges from 2 to 20 ps/mV, depending on design, process, and loading conditions.

Cascaded Buffer Chains

Clock distribution networks often employ chains of buffers to maintain signal integrity while driving large loads. In such chains, power-induced jitter can accumulate in several ways:

Uncorrelated Noise: If each buffer experiences independent supply noise, jitter accumulates statistically as the square root of the number of stages
Correlated Noise: When buffers share power distribution and experience common supply variations, jitter accumulates linearly with the number of stages
Frequency-Dependent Behavior: Different accumulation mechanisms dominate at different frequencies, depending on PDN characteristics and buffer spacing

In practice, buffer chains often exhibit partially correlated behavior, with accumulation rates between the statistical and linear extremes.

Duty Cycle Distortion

Supply variations can affect rising and falling transitions differently, leading to duty cycle distortion in addition to edge-to-edge jitter. This occurs when:

NMOS and PMOS transistors exhibit different supply sensitivities
Rising and falling edges traverse different circuit paths with different supply domains
Supply noise contains frequency components that create asymmetric effects over the clock period

Jitter Amplification

Certain circuit topologies and operating conditions can amplify power-induced jitter beyond what might be expected from simple sensitivity calculations. Understanding these amplification mechanisms helps identify vulnerable circuits and motivate appropriate mitigation strategies.

Regenerative Circuits

Circuits with positive feedback, such as sense amplifiers, latches, and comparators, exhibit metastable behavior near their decision threshold. When supply noise affects the circuit during the regeneration phase, small voltage variations can significantly alter the output timing. This effect is particularly pronounced in:

High-speed receivers with decision feedback equalization
Memory sense amplifiers operating near their access time limits
Clock and data recovery circuits during edge transitions

Threshold-Dependent Circuits

Circuits that make timing decisions based on voltage thresholds are inherently sensitive to both signal amplitude variations and threshold shifts. When supply noise modulates both the signal amplitude and the decision threshold, the effects can combine to create amplified jitter. This is especially problematic in:

Single-ended signaling where the signal and reference share supply domains
Voltage-mode logic families with supply-referenced thresholds
Comparators without adequate power supply rejection

Resonant Effects

When supply noise frequencies coincide with circuit natural resonances, amplification can occur through resonant coupling. This is particularly relevant in:

LC-based oscillators where supply noise excites tank resonance
Package and PCB resonances that amplify specific noise frequencies
Clock networks with resonant distribution structures

Power Supply Rejection

Power supply rejection ratio (PSRR) quantifies a circuit's ability to reject supply voltage variations and prevent them from affecting the output. High PSRR is essential for minimizing power-induced jitter in timing-critical circuits.

PSRR Fundamentals

PSRR is typically expressed in decibels and varies with frequency. A circuit with 60 dB PSRR at a particular frequency will exhibit output variations 1000 times smaller than the supply variations at that frequency. For jitter-sensitive applications, PSRR values exceeding 40 dB across the relevant frequency range are generally desirable.

PSRR degrades with increasing frequency due to parasitic capacitances, limited circuit bandwidth, and reduced effectiveness of filtering structures. Understanding the frequency-dependent nature of PSRR is crucial for predicting power-induced jitter across the full spectrum of supply noise.

Circuit Design for High PSRR

Several circuit design techniques enhance power supply rejection:

Differential Architectures: Fully differential circuits naturally reject common-mode supply variations, providing inherently high PSRR
Cascode Structures: Cascode current sources and loads increase output impedance and improve rejection of supply noise
Regulated Bias Circuits: On-chip regulators and bandgap references provide stable bias voltages independent of supply variations
Current-Mode Logic: Logic families that operate based on current switching rather than voltage levels can achieve superior supply rejection
Feedback and Regulation: Local and global feedback mechanisms continuously correct for supply-induced variations

Measurement and Characterization

Accurate PSRR measurement requires specialized techniques to inject controlled supply disturbances while monitoring output variations. Key considerations include:

Frequency sweep across the relevant range (DC to beyond the highest jitter frequency of interest)
Separation of supply rejection from other noise sources
Accounting for measurement equipment limitations and parasitics
Correlation with jitter measurements to validate PSRR predictions

Isolation Techniques

Effective isolation prevents supply noise generated by noisy circuits from coupling into sensitive timing circuits. Multiple isolation strategies can be employed at different levels of the design hierarchy.

Physical Separation

The simplest isolation technique is physical separation of noisy and sensitive circuits, reducing coupling through substrate, package, and PCB parasitics. Effective separation requires:

Adequate spacing between noise sources and sensitive receivers
Strategic placement of guard rings and substrate contacts to shunt noise currents
Careful floorplanning to avoid routing sensitive signals near noisy power domains
Use of separate package pins and PCB regions for different power domains

Guard Rings and Substrate Isolation

In integrated circuits, guard rings provide a controlled path for substrate currents, preventing them from modulating sensitive circuit nodes. Effective guard ring implementation requires:

Complete enclosure of sensitive circuits or noise sources
Multiple parallel rings for increased isolation
Adequate guard ring width and contact density
Connection to appropriate voltage references (typically substrate or well potentials)

Power Domain Partitioning

Dividing the system into separate power domains isolates noise to specific regions. This approach requires:

Identification of noise sources and sensitive circuits
Assignment of circuits to appropriate power domains
Implementation of level shifters for signals crossing domain boundaries
Careful management of domain interfaces to prevent ground loops and coupling

Package and PCB Isolation

At the package and board level, isolation techniques include:

Separate power and ground pins for different domains
Power plane splits (with careful attention to return current paths)
Strategic via placement to create low-impedance ground connections
Ferrite beads and isolation resistors to impede AC coupling between domains

Separate Power Supplies

Providing separate, dedicated power supplies for sensitive timing circuits offers the highest level of isolation from system-wide supply noise. This approach is commonly employed for critical circuits such as PLLs, clock generators, and high-speed transceivers.

Dedicated Regulators

On-chip or on-board linear regulators can provide clean, isolated power supplies for sensitive circuits. Key design considerations include:

Regulator Bandwidth: The regulator must have sufficient bandwidth to suppress supply noise across the relevant frequency range
Load Regulation: The regulator must maintain stable output voltage despite varying load currents from the supplied circuits
Output Impedance: Low output impedance ensures that load current variations don't create voltage droop
Dropout Voltage: Adequate headroom between input and output voltages must be maintained for proper regulation
Startup Behavior: Regulator startup must be controlled to prevent disruption of sensitive circuits

LDO Regulators for Jitter-Sensitive Circuits

Low-dropout (LDO) linear regulators are particularly well-suited for powering jitter-sensitive circuits due to their excellent noise rejection and minimal output noise. Effective LDO implementation requires:

Selection of LDOs with high PSRR across the frequency range of concern
Adequate output capacitance to maintain stability and provide local energy storage
Proper layout to minimize parasitics and maintain regulator loop stability
Bypassing techniques to handle high-frequency current demands

Multiple Supply Domains

Complex systems often employ multiple separate supply domains, each optimized for its specific requirements:

Core Digital Logic: May tolerate significant supply noise and benefits from aggressive power management
Clock Generation and Distribution: Requires ultra-low noise supplies with excellent regulation
High-Speed I/O: Needs carefully controlled supply levels to maintain signal integrity and timing accuracy
Analog and Mixed-Signal Circuits: Demand quiet supplies isolated from digital switching noise

Trade-offs and Considerations

While separate supplies provide excellent isolation, they introduce complexity and cost:

Increased bill of materials and board area for additional regulators
More complex power sequencing requirements
Potential for ground loops if not carefully managed
Additional routing complexity for multiple supply domains

Filtering Strategies

Effective filtering removes or attenuates supply noise before it can affect timing-critical circuits. Multiple filtering approaches can be combined to provide broadband noise suppression.

Decoupling Capacitors

Decoupling capacitors form the foundation of most power filtering strategies, providing local energy storage and creating low-impedance paths for high-frequency currents. Effective decoupling requires:

Multiple Capacitor Values: A distribution of capacitor values provides effectiveness across a wide frequency range
Strategic Placement: Capacitors must be placed close to the circuits they support, minimizing inductance in the current path
Adequate Quantity: Sufficient total capacitance ensures low impedance at the frequencies of concern
Connection Quality: Low-inductance connections via multiple parallel vias enhance effectiveness

Ferrite Beads

Ferrite beads provide series impedance at high frequencies while maintaining low DC resistance, making them effective for isolating power domains. Key considerations include:

Impedance versus frequency characteristics matched to the noise spectrum
DC resistance minimized to avoid voltage drop
Saturation current rating adequate for the load
Placement to intercept noise currents before they reach sensitive circuits

LC Filters

LC filters provide selective attenuation of supply noise at specific frequencies. They are particularly effective when the noise spectrum is concentrated in known frequency bands. Design considerations include:

Selection of cutoff frequency below the lowest noise frequency of concern
Adequate inductor current rating and low DC resistance
Capacitor values chosen for desired roll-off characteristics
Damping to control resonant behavior and prevent peaking

Pi Filters and Multi-Stage Filtering

Pi filters (capacitor-inductor-capacitor) and cascaded filter stages provide enhanced attenuation for critical applications. These structures offer:

Improved high-frequency rejection compared to simple LC filters
Better load isolation from supply impedance variations
Flexibility to optimize different stages for different frequency ranges

Active Filtering

Active filter circuits can provide very high noise rejection with smaller passive components. Techniques include:

Op-amp-based active filters with programmable characteristics
Feedback-controlled regulators that actively cancel supply variations
Noise cancellation circuits that inject compensating currents

Measurement and Characterization

Effective management of power-induced jitter requires accurate measurement and characterization techniques to validate designs and diagnose issues.

Simultaneous Power and Timing Measurement

Understanding the relationship between supply noise and jitter requires time-correlated measurement of both domains. This typically involves:

High-bandwidth power supply probing to capture noise events
Jitter measurement synchronized with supply measurements
Statistical analysis to identify correlations between supply variations and timing errors
Frequency-domain analysis to reveal spectral relationships

Jitter Decomposition

Separating power-induced jitter from other jitter sources helps quantify the specific contribution of supply noise. Techniques include:

Comparison of jitter with and without controlled supply disturbances
Spectral analysis to identify jitter components correlating with known supply noise frequencies
Statistical fitting of jitter distributions to identify deterministic components

Sensitivity Testing

Deliberate injection of supply disturbances while monitoring timing allows direct measurement of circuit sensitivity. This approach enables:

Quantification of delay sensitivity coefficients
Validation of PSRR specifications
Identification of frequency ranges where sensitivity is highest
Comparison of different power filtering and isolation strategies

Design Guidelines and Best Practices

Minimizing power-induced jitter requires attention throughout the design process, from architecture and circuit design through layout and validation.

Architecture-Level Decisions

Identify jitter-critical circuits early in the design process
Plan power domain partitioning with jitter sensitivity in mind
Budget for dedicated supplies and regulators where justified by jitter requirements
Choose circuit topologies and logic families with good inherent PSRR

Circuit Design Guidelines

Employ differential architectures where possible for timing-critical paths
Design clock distribution networks with consistent delay sensitivity across stages
Implement local regulation for VCOs and other highly sensitive circuits
Minimize the number of stages in timing-critical paths to reduce jitter accumulation
Design for adequate PSRR across the full frequency range of potential supply noise

Layout Best Practices

Place decoupling capacitors as close as possible to sensitive circuits
Use multiple parallel vias for power and ground connections to minimize inductance
Implement guard rings and substrate isolation for jitter-critical blocks
Route sensitive signals away from noisy power domains and switching circuits
Maintain clean return current paths for high-speed signals
Verify power distribution network impedance through simulation before fabrication

Validation and Testing

Include supply noise injection capability in test fixtures for sensitivity characterization
Perform time-correlated measurements of supply voltage and jitter
Validate that actual jitter sensitivity matches predictions from simulation
Test across process, voltage, and temperature corners to ensure robust performance
Document measured PSRR and sensitivity parameters for future reference

Case Studies and Practical Examples

Clock Distribution Network

In a high-performance processor with a 10-stage clock distribution network, each buffer exhibits 5 ps/mV delay sensitivity. With 20 mV of correlated supply noise, the total accumulated jitter reaches 1000 ps (1 ns), consuming a significant fraction of the timing budget. Implementing separate supplies for the clock network and improving decoupling reduces supply noise to 2 mV, decreasing jitter to 100 ps and recovering critical timing margin.

PLL in a High-Speed Transceiver

A transceiver PLL with 5 MHz/V push coefficient experiences 50 mV supply noise at 1 MHz. This creates deterministic jitter of approximately 10 ps RMS, degrading eye opening and increasing bit error rate. Adding a dedicated LDO regulator with 60 dB PSRR at 1 MHz reduces supply noise by a factor of 1000, decreasing PLL jitter to negligible levels and restoring link performance.

Mixed-Signal IC with Digital Noise Coupling

In a mixed-signal device, digital switching generates supply noise that couples into a sensitive clock generator, causing excessive jitter. Analysis reveals that 100 MHz digital switching harmonics dominate the noise spectrum. Implementing power domain separation, strategic ferrite bead placement, and targeted decoupling at 100 MHz and harmonics reduces coupling by 30 dB, bringing jitter within specifications.

Conclusion

Power-induced jitter represents a critical challenge in modern electronics, particularly as voltage margins shrink and timing requirements tighten. Understanding the mechanisms through which supply noise couples into timing variations enables designers to implement effective mitigation strategies. Success requires a multi-faceted approach combining circuit design for high PSRR, careful power distribution network design, strategic isolation and filtering, and thorough validation through measurement and characterization.

As systems continue to push toward higher speeds and lower power, the interaction between power integrity and timing will only intensify. Designers who develop expertise in identifying, quantifying, and mitigating power-induced jitter will be well-positioned to deliver robust, high-performance systems that meet increasingly stringent requirements.