Electronics Guide

Jitter Definition and Measurement

Jitter is typically measured as the time deviation of signal edges from their ideal positions. Common metrics include:

• Period jitter: Variation in the time between successive rising (or falling) edges of a clock signal.
• Cycle-to-cycle jitter: Change in period from one cycle to the next, important for sequential logic setup and hold timing.
• Time interval error (TIE): Deviation of each edge from an ideal reference clock, showing accumulated timing error over many cycles.
• Phase jitter: Jitter expressed as phase deviation, useful for communication systems specified in degrees or radians.

Jitter measurement requires high-resolution timing instruments such as oscilloscopes with adequate bandwidth and sampling rate, or dedicated jitter analyzers that can characterize jitter distributions over millions of edges.

Peak-to-Peak vs. RMS Jitter

Jitter is characterized by both peak-to-peak and RMS (root mean square) values. RMS jitter represents the standard deviation of timing errors and is useful for random jitter components that follow Gaussian distributions. Peak-to-peak jitter captures the total observed timing range but depends on observation time since random processes occasionally produce extreme values.

For system design, the relevant peak-to-peak jitter at a given bit error rate (BER) is often calculated from RMS random jitter using statistical relationships. For example, at a BER of 10^-12, peak-to-peak jitter is approximately 14 times the RMS value for Gaussian random jitter.

Random Jitter (RJ)

Random jitter arises from fundamental physical phenomena that produce unpredictable timing variations. These include:

• Thermal noise: Random electron motion in resistors and transistors creates voltage fluctuations that translate to timing uncertainty as signals cross threshold levels.
• Shot noise: Discrete nature of electron flow creates current fluctuations, particularly significant in semiconductor devices and photodetectors.
• Flicker (1/f) noise: Low-frequency noise with power spectral density inversely proportional to frequency, contributing to long-term timing drift.

Random jitter follows a Gaussian (normal) distribution and is unbounded, meaning arbitrarily large values occur with exponentially decreasing probability. This unbounded nature means random jitter fundamentally limits the achievable bit error rate no matter how much timing margin is provided.

RJ is characterized by its RMS value (standard deviation). The peak-to-peak value at a specific BER is calculated using the Gaussian relationship with the appropriate multiplier.

Deterministic Jitter (DJ)

Deterministic jitter has identifiable causes and bounded peak-to-peak values. Unlike random jitter, deterministic jitter can often be reduced or eliminated through design improvements. Categories include:

• Periodic jitter (PJ): Timing variations that repeat at a consistent rate, often caused by power supply ripple, electromagnetic interference, or crosstalk from periodic signals. PJ appears as discrete spectral lines in jitter frequency analysis.
• Data-dependent jitter (DDJ): Timing variations that depend on the data pattern being transmitted. Caused by intersymbol interference, baseline wander, or duty cycle distortion. DDJ is bounded by the range of possible data patterns.
• Duty cycle distortion (DCD): Systematic difference between the duration of logic high and logic low states. Often caused by threshold asymmetry in drivers or receivers.
• Bounded uncorrelated jitter (BUJ): Deterministic jitter without clear periodicity or data correlation, such as crosstalk from uncorrelated digital signals.

The total deterministic jitter is the combination of all DJ components, taking into account their correlations. For completely uncorrelated components, peak-to-peak values add directly (worst case). For correlated components, more sophisticated analysis is required.

Total Jitter

Total jitter combines random and deterministic components. Since RJ is unbounded, total jitter must be specified at a particular BER. A common formula is:

TJ(BER) = DJ_pp + 2 * N(BER) * RJ_rms

Where N(BER) is the multiplier from the inverse Gaussian cumulative distribution function at the specified BER. For example, N = 7.03 at BER = 10^-12.

This dual-Dirac model assumes the DJ distribution can be approximated as two impulses separated by DJ_pp, which is reasonable for many practical cases but may underestimate jitter for complex DJ distributions.

Slope-Dependent Timing Uncertainty

When a signal with noise crosses a threshold level, the timing of the crossing depends on the noise value at that instant. The relationship is:

sigma_t = sigma_v / (dV/dt)

Where sigma_t is the timing uncertainty (RMS jitter), sigma_v is the RMS noise voltage, and dV/dt is the signal slope at the threshold crossing. This relationship shows that:

• More noise produces more jitter.
• Faster edge rates reduce noise-induced jitter.
• Jitter is worst where the signal slope is minimum.

This conversion of amplitude noise to timing jitter is a fundamental mechanism linking signal quality to timing reliability.

Power Supply Noise

Noise on power supply rails affects timing through multiple mechanisms:

• Threshold modulation: If the receiver threshold varies with supply voltage, supply noise directly modulates the sampling point.
• Driver timing: Transmitter output timing may vary with supply voltage, creating periodic jitter synchronized with supply ripple.
• PLL sensitivity: Clock generation PLLs often have supply-sensitive VCOs, converting supply noise to clock jitter.

Power integrity is thus closely linked to signal integrity and timing reliability. Clean, well-decoupled power supplies are essential for low-jitter systems.

Crosstalk-Induced Jitter

Crosstalk from adjacent signals adds noise that converts to timing jitter. This jitter may be periodic (if the aggressor is a clock), data-dependent (if from parallel data signals), or appear random (if from uncorrelated digital signals). Managing crosstalk through proper layout practices is essential for timing integrity.

Setup and Hold Time

Synchronous digital circuits require data to be stable for a minimum time before (setup time) and after (hold time) the clock edge. These requirements define a timing window within which the data signal must be valid. Jitter on either the clock or data signal effectively shrinks this window.

The available timing margin is:

Margin = T_period - T_setup - T_hold - T_{prop_max} - T_jitter

Where T_{prop_max} is the maximum propagation delay and T_jitter includes all jitter sources. Positive margin indicates reliable operation; negative margin indicates timing failures.

Eye Diagram Analysis

Eye diagrams provide visual representation of timing and amplitude margins in serial data links. By overlaying many bit periods, the eye diagram shows the distribution of timing and voltage variations. A wide, open eye indicates good margins; a closed eye indicates unreliable data recovery.

Key eye diagram parameters include:

• Eye width: Horizontal opening at the decision threshold, representing timing margin.
• Eye height: Vertical opening at the sampling instant, representing voltage margin.
• Jitter: Variation in edge positions, visible as horizontal spreading of transitions.
• Noise: Variation in voltage levels, visible as vertical spreading of the eye.

Eye diagrams at various BER contours show how margins decrease as lower error rates are required, directly linking timing analysis to system reliability requirements.

Timing Budgets

Timing budgets allocate the available timing window among all contributing factors. A typical high-speed serial link timing budget includes:

• Transmitter jitter: Clock and output stage contributions.
• Channel effects: Intersymbol interference, dispersion, and reflections.
• Crosstalk: Converted to jitter through the slope-noise relationship.
• Power supply effects: Periodic jitter from supply ripple.
• Receiver jitter: Clock recovery and sampling circuit contributions.
• Random jitter: Fundamental noise-limited contributions.

The budget must include margin for manufacturing variation, temperature effects, and aging. Statistical combination of independent jitter sources (RSS for random, direct sum for correlated deterministic) provides realistic total jitter estimates.

Oscillator and PLL Jitter

Crystal oscillators, which serve as timing references, exhibit phase noise that translates to jitter. Key characteristics include:

• Phase noise: Random phase variations specified as power spectral density versus offset frequency.
• Allan deviation: Time-domain measure of frequency stability over various averaging intervals.
• Spurious tones: Discrete spectral components from vibration sensitivity or circuit nonlinearity.

PLLs can multiply clock frequencies but also affect jitter. PLL bandwidth determines how much of the reference jitter passes through versus how much VCO jitter contributes. Optimal bandwidth balances these effects based on the relative quality of reference and VCO.

Interconnect-Induced Jitter

Signal propagation through PCB traces, cables, and connectors introduces jitter through several mechanisms:

• Intersymbol interference (ISI): Frequency-dependent loss causes pulse spreading that affects timing based on data patterns.
• Reflections: Impedance discontinuities create reflected waves that distort timing.
• Mode conversion: In differential pairs, common-mode to differential-mode conversion can create pattern-dependent jitter.

Equalization techniques at transmitter and receiver compensate for channel effects, trading complexity for reduced ISI-induced jitter.

Driver and Receiver Jitter

Transmitter and receiver circuits contribute jitter through:

• Output jitter: Variation in when the driver switches, often correlated with supply voltage or data patterns.
• Threshold uncertainty: Noise at the receiver comparator translates to timing variation.
• Clock recovery: CDR circuits have finite bandwidth and introduce jitter tracking error for rapidly varying input jitter.

Clean Clock Generation

Low-jitter clock sources include:

• High-quality crystal oscillators: TCXO, OCXO, and SC-cut crystals for demanding applications.
• Jitter attenuators: Clock buffer ICs with narrow-band PLLs that filter input jitter.
• Spread spectrum clocking: While intentionally adding jitter for EMI reduction, must be accounted for in timing budgets.

Clock distribution requires careful attention to avoid adding jitter. Balanced clock trees, proper termination, and isolation from noisy signals maintain clock quality through the system.

Power Integrity

Clean power supplies reduce periodic jitter:

• Decoupling: Multiple capacitor values provide low impedance across a wide frequency range.
• Power plane design: Solid planes with strategic splits where needed maintain low-impedance power delivery.
• Regulator selection: Low-noise LDOs for sensitive circuits; adequate filtering for switching regulators.

Signal Conditioning

Equalization compensates for channel-induced ISI:

• Pre-emphasis: Boost high-frequency content at the transmitter to compensate for channel loss.
• De-emphasis: Reduce low-frequency content while maintaining high-frequency edges.
• CTLE: Continuous-time linear equalizers at the receiver provide frequency-dependent gain.
• DFE: Decision feedback equalizers use previously detected bits to remove ISI.

Clock Data Recovery Optimization

CDR circuits in serial receivers must track incoming jitter while filtering noise. Bandwidth selection trades tracking ability against jitter amplification. Adaptive CDR circuits adjust bandwidth based on signal conditions for optimal performance.

Oscilloscope-Based Measurement

Real-time and sampling oscilloscopes measure jitter through:

• Histogram analysis: Distribution of edge positions reveals RJ and DJ components.
• Trend analysis: Time-series of period or TIE values shows long-term behavior and periodic components.
• Spectral analysis: FFT of jitter time series identifies periodic jitter frequencies.

Measurement instrument contribution must be accounted for, especially when measuring low-jitter signals approaching instrument limits.

Jitter Decomposition

Separating total jitter into RJ and DJ components enables root cause analysis and appropriate mitigation. Techniques include:

• Tail fitting: Gaussian tails in jitter histograms reveal RJ component.
• Dual-Dirac analysis: Fit observed distribution to dual-Dirac model to extract RJ and DJ.
• Spectral separation: Periodic jitter appears as spectral lines; random jitter as broadband noise floor.

Interface Specifications

Common high-speed interfaces have standardized jitter specifications:

• PCI Express: Specifies total jitter at 10^-12 BER for each generation.
• USB: Eye diagram templates and jitter limits for each speed mode.
• Ethernet: Jitter tolerance and generation specifications by rate class.
• SATA: Separate DJ and RJ specifications for transmit and receive.

Compliance testing verifies that implementations meet these specifications under defined test conditions.

Test Methodologies

Standard test methods ensure consistent, comparable measurements:

• Pattern selection: Specific test patterns (PRBS, compliance patterns) exercise worst-case conditions.
• Observation time: Statistical confidence requires adequate sample sizes.
• Calibration: Reference clock and measurement system calibration ensures accuracy.