Electronics Guide

Device Layer, Buried Oxide, and Handle

At the top sits the device layer, also called the active layer, top silicon, or SOI film. It is single-crystal silicon of device quality, and the transistors are built entirely within it. Its thickness spans an enormous range depending on the application: several micrometers for power devices and micromechanical structures, one to two hundred nanometers for earlier digital processes, and less than ten nanometers for fully depleted logic.

Beneath it lies the buried oxide, known throughout the industry as the BOX. It is amorphous silicon dioxide, the same material used for gate dielectrics and field isolation, and it electrically separates the device layer from everything below. Typical buried oxides range from roughly one to two micrometers in photonic and high-voltage applications, through the one-hundred-to-two-hundred-nanometer range common in earlier digital SOI, down to twenty-five nanometers or less in the ultrathin-body-and-BOX processes described below.

The bottom layer is the handle wafer, a conventional silicon wafer that provides mechanical support and thermal mass. It carries no devices. Its properties still matter a great deal, however, because the handle sits directly beneath the buried oxide and therefore acts as a capacitive plate and a potential path for parasitic conduction. Choosing its resistivity is one of the central design decisions in radio-frequency SOI.

How This Differs from Bulk Silicon

In a bulk complementary metal-oxide-semiconductor process, transistors are isolated from one another laterally, by shallow trench isolation and by reverse-biased well junctions, but never vertically. A conducting path always exists downward into the substrate. That path carries junction leakage, couples switching noise from one circuit block into another, supplies the base current for parasitic bipolar transistors, and collects the charge liberated by ionizing radiation anywhere in the wafer.

SOI replaces vertical junction isolation with dielectric isolation. When the shallow trench isolation is etched all the way down to the buried oxide, a condition described as full dielectric isolation or mesa isolation, each transistor sits in its own silicon island surrounded on every side by insulator. No direct current path exists between one device and another, or between any device and the handle wafer. Only capacitive coupling through the oxide remains.

This single structural change is the root of every property discussed in the rest of this article. The advantages come from removing conducting paths. The complications come from the fact that those same paths were quietly performing useful services, notably conducting heat away from the channel and holding the transistor body at a known potential.

Partially Depleted SOI

In partially depleted SOI, conventionally abbreviated PD-SOI, the silicon film is thicker than the maximum gate-induced depletion width. When the transistor is on, a depletion region extends downward from the channel but stops short of the buried oxide, leaving a quasi-neutral region of doped silicon between the depletion edge and the oxide. That region is the transistor body.

Electrically, a partially depleted SOI transistor closely resembles a bulk transistor whose body terminal has been left unconnected. The threshold voltage is set by channel doping in the usual way, the subthreshold slope obeys the familiar body-factor expression, and existing bulk design intuition largely transfers. Film thicknesses on the order of fifty to two hundred nanometers are typical. The price of this familiarity is the floating body, whose consequences occupy a section of their own below.

Partially depleted SOI carried high-performance microprocessors through the 2000s. IBM used it for server and mainframe processor lines, and AMD for desktop and server parts from the mid-2000s into the early 2010s, in both cases because the reduction in junction capacitance translated directly into clock frequency. That era has closed. The leading-edge processors that succeeded those parts use three-dimensional gates on bulk wafers, so partially depleted logic in high-performance processors is now history rather than current practice. Partially depleted films remain in use in radiation-hardened and high-temperature product lines, where dielectric isolation rather than raw speed is the reason for choosing them.

Fully Depleted SOI

In fully depleted SOI, or FD-SOI, the silicon film is thin enough that the depletion region occupies the entire film thickness even in equilibrium. No neutral body region exists. The consequences are substantial and mostly favorable.

Because the film is fully depleted, the gate controls essentially all of the charge in the channel region, and the vertical electric field terminates on the buried oxide rather than spreading into a substrate. Electrostatic control over the channel improves sharply, which suppresses short-channel effects such as drain-induced barrier lowering and threshold-voltage roll-off. The subthreshold swing approaches the thermal limit, which is 59.5 millivolts per decade at three hundred kelvin, because the body factor that degrades bulk devices is largely removed. Real fully depleted devices land a few millivolts per decade above that limit rather than on it.

A second advantage is more subtle but equally important. Because the threshold voltage of a fully depleted device is set by film thickness, gate work function, and back-gate bias rather than by channel doping, the channel can be left undoped or very lightly doped. Random dopant fluctuation, the statistical variation in the number and position of individual dopant atoms in a nanometer-scale channel, is one of the dominant sources of threshold-voltage mismatch in advanced bulk processes. Removing the dopants removes the fluctuation. The resulting improvement in transistor matching allows static random-access memory cells and analog circuits to operate reliably at lower supply voltages, which reduces dynamic power quadratically.

The cost is manufacturing difficulty. Threshold voltage depends directly on silicon film thickness, so the film must be uniform across a three-hundred-millimeter wafer to within a fraction of a nanometer. Producing such films is the central achievement of the layer-transfer processes described later. Contemporary FD-SOI logic processes use films in the neighborhood of five to ten nanometers over buried oxides of ten to twenty-five nanometers, a combination usually described as ultrathin body and BOX, or UTBB.

Back-Gate Bias Through the Buried Oxide

A thin buried oxide creates a capability that bulk silicon cannot easily match. The handle wafer beneath a UTBB device is close enough, and the oxide thin enough, that a voltage applied to the region under the BOX modulates the potential in the channel. The structure behaves as a second, weaker gate acting from below.

The effectiveness of this back gate scales with the ratio of buried-oxide capacitance to gate-oxide capacitance. For a twenty-five-nanometer BOX, a threshold shift on the order of tens of millivolts per volt of back-gate bias is typical, and the usable bias range of several volts therefore yields a total threshold adjustment of several hundred millivolts. Bulk devices can be body-biased as well, but forward bias is limited to a few hundred millivolts before the well junction begins to conduct, and each volt of bias moves the threshold less than it does through a thin buried oxide, so the usable range is considerably narrower.

Designers exploit this in two directions. Forward back bias lowers the threshold voltage, raising drive current and speed when a workload demands it. Reverse back bias raises the threshold, cutting subthreshold leakage during idle periods by orders of magnitude. Because the back gate is a separate terminal reached through the handle wafer, this adjustment can be applied per circuit block and changed at runtime, giving the power-management system a continuous knob rather than a set of fixed operating points. The same mechanism compensates for process and temperature variation, allowing slow dies to be sped up and fast, leaky dies to be calmed down after manufacture.

Thinning the buried oxide to strengthen the back gate is not free, because the same capacitance that couples the back gate to the channel also couples the source and drain diffusions to whatever sits under the oxide. Back-gate authority and parasitic capacitance to the substrate are two readings of one number, and a process chooses a buried-oxide thickness that balances them.

Realizing separate back-gate domains requires wells implanted through the buried oxide into the handle wafer, in either a conventional-well or flip-well arrangement depending on whether forward or reverse bias is the primary intent. This adds mask steps, but far fewer than the lithographic complexity of a comparable three-dimensional transistor process.

Where the Capacitance Goes

In a bulk transistor, the source and drain diffusions form reverse-biased p-n junctions with the well. Each junction contributes a depletion capacitance proportional to its area, plus a sidewall component along its perimeter. This junction capacitance loads every switching node, and it is nonlinear, varying with the voltage across the junction.

In an SOI transistor whose diffusions extend down to the buried oxide, the bottom of each diffusion faces oxide rather than silicon. The area component of junction capacitance is replaced by an oxide capacitance to the handle wafer. Per unit area, the replacement is smaller than the junction capacitance it replaces by the ratio of the depletion width to the buried-oxide thickness, multiplied by the permittivity ratio of silicon dioxide to silicon, which is about one-third. It also sits in series with the impedance of the substrate itself. Only the sidewall junctions to the remaining body silicon persist, and in a fully depleted device even those are minimal because the film is only nanometers thick.

How large the saving is therefore depends on the buried oxide. Over the thick buried oxide of a partially depleted process the area term nearly vanishes, and what remains of the source and drain capacitance is dominated by sidewall and overlap terms that SOI does not change. Over a twenty-five-nanometer oxide the replacement capacitance is comparable to the junction capacitance it replaced, and against a wide depletion region it can exceed it. This is the same trade-off that governs back-gate strength, seen from the other side.

What holds in every case is that the substituted capacitance is a linear oxide capacitance rather than a voltage-dependent depletion capacitance. The load becomes more predictable, which simplifies timing analysis and improves the linearity of analog nodes.

Speed, Dynamic Power, and Leakage

Lower node capacitance translates directly into shorter delays at a given drive current, or equivalently into the same delay at lower current and lower supply voltage. IBM, which put SOI into volume microprocessor production in 1998, claimed a twenty-five to thirty-five percent performance gain over bulk at the same node. That was a vendor figure for its own process on its own circuits, and it is best read as a ceiling rather than as a typical result. What a particular design realizes depends on how much of its load is junction capacitance rather than gate and wire capacitance, so the benefit is largest in dense, junction-dominated circuits such as memory arrays and dynamic logic, and close to negligible in a path dominated by long interconnect.

Static leakage improves for a different reason. Junction leakage in a bulk device scales with diffusion area, and it grows roughly exponentially with temperature. Removing the area component of the junction removes most of that leakage path, which is why SOI is attractive both for battery-powered devices and for circuits that must operate far above the commercial temperature range.

The Kink Effect

At high drain voltage, carriers accelerated in the pinch-off region gain enough energy to create electron-hole pairs by impact ionization. In an n-channel device, the electrons flow to the drain and the holes flow into the body. In a bulk transistor those holes leave through the body contact as substrate current. In a floating-body SOI transistor they have nowhere to go, so they accumulate and raise the body potential.

A raised body potential forward-biases the source-body junction, which lowers the threshold voltage, which increases drain current, which increases impact ionization further. The output characteristic accordingly shows a pronounced upward step, the kink, where the drain current rises abruptly in what should be the saturation region. The effect degrades output resistance, distorts analog gain stages, and produces a positive feedback loop that in extreme cases triggers the parasitic lateral bipolar transistor formed by the source, body, and drain, causing a premature breakdown known as single-transistor latch.

The kink effect is strongly suppressed in fully depleted devices. There is no neutral region in which the generated holes can collect, so they are swept out through the source rather than stored, and the body potential cannot rise far enough to forward-bias the source junction appreciably. Impact ionization itself is not eliminated; it is driven by the lateral field in the pinch-off region, which is set by drain bias and channel length rather than by film thickness. What thin-film operation removes is the storage that converts generated charge into a threshold shift. It is one of the clearest physical arguments for the thin-film route.

History Effect

Even below the impact-ionization threshold, the floating body creates a subtler problem. The body potential settles to a value determined by the balance of leakage currents and capacitive coupling, and that balance depends on how the transistor has been switched in the recent past. A device that has been idle for a long time and one that has just completed a series of transitions start their next switching event from different body potentials, and therefore from different threshold voltages.

The consequence is that propagation delay depends on switching history. For a synchronous design closing timing at a high clock frequency, pattern-dependent delay variation that the timing tools do not model is a serious matter. It must be bounded by simulating both first-switch and steady-state conditions and carrying the difference as timing margin. Historically, this required specialized transistor models and additional characterization work, and it was a genuine barrier to the adoption of partially depleted SOI by design teams accustomed to bulk libraries.

Related effects appear in specific circuit styles. Pass-gate and dynamic logic are particularly sensitive, because a floating body can shift the threshold of a device that is supposed to be firmly off, degrading the retention of a dynamic node. Sense amplifiers and other matched pairs suffer because two nominally identical devices may have different switching histories and therefore different effective thresholds.

Body Contacts and Their Cost

Floating-body effects can be eliminated by tying the body to a fixed potential with a body contact, most often an implanted region of opposite type reaching the body from the side. Circuit designers use body ties selectively, on the devices where the effect is intolerable, such as analog current sources, sense amplifiers, and input-output structures.

The remedy is not free. A body tie enlarges the transistor layout, adds resistance in series with the body, which limits how quickly the body potential can be corrected, and reintroduces part of the parasitic capacitance that SOI was meant to remove. Body ties also become progressively less effective as devices shrink, because the resistance of the thin body region rises. In practice, partially depleted design is an exercise in deciding which transistors deserve the expense.

One line of research inverted the problem and treated the floating body as a feature. Because the body stores charge that modulates the threshold voltage, a single transistor can in principle serve as a memory cell without a separate capacitor, an idea explored as the floating-body cell or capacitor-less dynamic memory. The concept demonstrated working arrays but did not displace conventional memory, largely because retention time degraded as devices scaled.

Thermal Resistance of the Buried Oxide

Power dissipated in the channel of an SOI transistor must escape either laterally through the thin silicon film and its contacts, or vertically through the buried oxide into the handle wafer. Both paths are constricted. The film is thin, so its lateral thermal conductance is small, and the thin film is worse than its cross-section alone suggests: once a silicon layer thins toward the phonon mean free path, boundary scattering drives its thermal conductivity well below the bulk value. The oxide is a poor conductor, so the vertical path is resistive. The device therefore runs at a junction temperature noticeably above that of an equivalent bulk transistor at the same power density, and the rise scales with buried-oxide thickness.

Thin-BOX processes are helped considerably here: a twenty-five-nanometer buried oxide presents far less thermal resistance than a one-hundred-fifty-nanometer one, so ultrathin-body-and-BOX technologies suffer less self-heating than the thick-BOX partially depleted processes that preceded them. Devices with thick buried oxides, such as high-voltage and photonic structures, suffer most.

Consequences for Characterization and Design

Self-heating produces a distinctive measurement artifact. Carrier mobility falls with temperature, so as an SOI transistor heats under increasing drain bias its drain current can actually decrease, giving a region of negative output conductance in a slowly swept direct-current measurement. The same device measured with short pulses, before the channel has time to heat, shows no such behavior. Accurate characterization of SOI therefore requires pulsed current-voltage measurement, and compact models must include a thermal network so that simulated device temperature tracks dissipated power.

For design, self-heating matters most for devices that carry sustained current: output drivers, electrostatic-discharge protection, power switches, and analog bias circuits. It also interacts with reliability physics, because the dominant wear-out mechanisms in silicon, including electromigration in the local interconnect and bias-temperature instability in the gate stack, are strongly temperature-activated. A modest steady-state temperature rise can consume a meaningful fraction of a device's projected lifetime.

Eliminating the Parasitic Thyristor

Bulk complementary metal-oxide-semiconductor circuits contain an unavoidable parasitic four-layer structure. The p-channel source, n-well, p-substrate, and n-channel source form a pnpn path equivalent to a pair of cross-coupled bipolar transistors, that is, a thyristor. If enough current is injected into a well or the substrate to forward-bias one of the base-emitter junctions, the pair can trigger into a self-sustaining low-impedance state that shorts supply to ground. This is latch-up, and it usually destroys the die unless power is removed at once.

The parasitic thyristor requires a continuous silicon path from one device to the other. In a fully dielectrically isolated SOI process, that path does not exist: the buried oxide breaks the vertical route and trench isolation to the BOX breaks the lateral one. SOI circuits are consequently immune to conventional latch-up. This removes an entire class of layout rules, including the well-tie spacing and guard-ring requirements that consume area in bulk designs, and it is one reason SOI is favored where transient overvoltage on external pins is expected.

Single-Event Effects

When an energetic ion passes through silicon it leaves a dense track of electron-hole pairs. In a bulk device, charge is collected from a large volume, both by drift in the depletion region and by a funneling process that briefly extends the collecting field deep into the substrate, followed by slower diffusion from farther away. The total collected charge can easily exceed the critical charge that flips a memory cell.

In SOI, the sensitive volume is limited to the thin device layer. An ion traversing a hundred-nanometer film liberates far less charge within the collecting region than one traversing several micrometers of bulk silicon, and the buried oxide blocks diffusion of charge generated in the handle wafer from ever reaching the device. Collected charge falls by roughly the ratio of the film thickness to the bulk collection depth, and single-event upset rates improve accordingly. Single-event latch-up is eliminated outright, along with the destructive failures it causes.

The improvement is not unconditional. In a floating-body partially depleted device, the charge deposited in the body raises the body potential and can turn on the parasitic lateral bipolar transistor, which then amplifies the initial charge. This bipolar amplification can multiply the effective collected charge severalfold and partially offsets the volume advantage. Radiation-hardened SOI designs therefore use body ties on critical nodes, together with circuit-level hardening such as redundant storage nodes and resistive decoupling, rather than relying on the substrate alone.

Total Ionizing Dose and the Buried Oxide

Cumulative dose acts differently. Ionizing radiation generates electron-hole pairs in oxides as well as in silicon; electrons are mobile and escape quickly, while holes move slowly and are trapped at defect sites. Trapped positive charge accumulates. In the gate oxide this shifts threshold voltage, an effect that has become far less severe as gate dielectrics have thinned, since thin oxides both trap less charge and permit tunneling that neutralizes it.

The buried oxide, however, is thick and remains so. Positive charge trapped in the BOX acts as an unintended back-gate bias, and in an n-channel device it can invert the back interface of the silicon film, opening a leakage path along the bottom of the body that the front gate cannot turn off. This back-channel leakage is the characteristic total-dose failure mode of SOI, and it means that SOI is not automatically more dose-tolerant than bulk; without countermeasures it can be worse. Hardened processes address it with buried oxides engineered for low trap density, with body ties that hold the film potential, and with layout techniques such as enclosed-geometry transistors that deny the leakage path a route from source to drain.

High-Resistivity Substrates and Trap-Rich Layers

A radio-frequency signal on a metal line above the die couples capacitively through the buried oxide into the handle wafer. If the handle is ordinary, moderately doped silicon, that coupling drives current through a lossy, conductive medium: energy is dissipated, the quality factor of on-chip inductors and transmission lines falls, and the nonlinearity of the semiconducting substrate generates harmonics and intermodulation products. Standard bulk silicon is a poor host for high-linearity radio-frequency circuits for exactly this reason.

SOI allows the handle wafer to be chosen independently of the devices, because it carries none. Replacing it with high-resistivity silicon, typically above one kilohm-centimeter and often several kilohm-centimeters, reduces substrate loss dramatically. However, resistivity alone is insufficient. Fixed charge in the buried oxide attracts carriers to the underside of the BOX and forms a thin, conductive, and strongly nonlinear inversion or accumulation layer known as the parasitic surface conduction layer. It pulls the effective resistivity seen by the signal far below the nominal resistivity of the handle, and it is a potent generator of harmonic distortion.

The solution is a trap-rich layer, usually polycrystalline or otherwise defect-rich silicon deposited between the buried oxide and the high-resistivity handle. Its grain boundaries provide a high density of traps with very short carrier lifetimes, which pin the Fermi level, prevent a continuous inversion layer from forming, and preserve the substrate's effective resistivity under bias. A trap-rich substrate therefore holds its effective resistivity near the nominal value of the handle across frequency and bias, and sharply reduces second- and third-harmonic generation relative to an untreated high-resistivity wafer. This engineered substrate, rather than the transistor, is the enabling element of modern RF SOI.

Switches, Stacking, and Figures of Merit

The canonical RF SOI product is the antenna switch. Its quality is captured by the product of on-state resistance and off-state capacitance, the R_onC_off figure of merit, expressed in femtoseconds: on-resistance sets insertion loss, off-capacitance sets isolation, and the product is largely independent of device width, so it characterizes the technology rather than a particular layout. Lower is better. Modern RF SOI switch processes reach the neighborhood of one hundred femtoseconds and below, where published comparisons put gallium arsenide pHEMT switches at roughly twice that. Silicon overtook the compound-semiconductor switch on its own figure of merit, rather than merely approaching it.

Handling transmit power is the other requirement. A power amplifier output may swing tens of volts peak-to-peak, far beyond the breakdown voltage of a single thin-oxide transistor. Designers stack many transistors in series, distributing the voltage across the stack so that each device sees a tolerable fraction. Stacking works well on SOI precisely because dielectric isolation removes the body-to-substrate junction that would otherwise clamp the intermediate nodes, allowing each device in the stack to float to its share of the signal. Achieving that on bulk silicon is far harder, and stacking, as much as the figure of merit, is why SOI displaced compound semiconductors in handset switching.

The same properties benefit low-noise amplifiers, antenna tuners, digitally tunable capacitors, and phase shifters, and they permit the control logic to be integrated on the same die as the radio-frequency path, since dielectric isolation greatly suppresses noise coupling between the two.

Separation by Implantation of Oxygen

The SIMOX process, an acronym for separation by implantation of oxygen, forms the buried oxide inside a conventional wafer. A very high dose of oxygen ions, on the order of 10¹⁷ to 10¹⁸ per square centimeter, is implanted to a controlled depth. A high-temperature anneal, above thirteen hundred degrees Celsius, then drives the oxygen to precipitate and coalesce into a continuous buried silicon dioxide layer, while the implantation damage in the surface silicon anneals out and the crystal recovers.

SIMOX has the elegance of requiring only one wafer. Its limitations are the extreme implant dose, which makes throughput poor and cost high, residual defects in the top film, and limited flexibility in choosing film and oxide thicknesses independently. It was historically important and is still used in niches, but it has been largely superseded.

Wafer Bonding and Layer Transfer

The dominant approach builds the wafer from two. A donor wafer is oxidized to form what will become the buried oxide, then bonded to a handle wafer. Bonding of clean, flat, hydrophilic silicon and oxide surfaces occurs spontaneously at room temperature through hydrogen bonding and van der Waals forces, and an anneal converts the bond into covalent silicon-oxygen-silicon links of full strength. The donor wafer must then be thinned to leave only the desired device layer.

Early bonded techniques thinned the donor by grinding and polishing, sometimes using an etch-stop layer, which limited thickness uniformity. The decisive advance was the Smart Cut process, invented at the French research institute CEA-Leti in the early 1990s and commercialized by its spin-out Soitec, which built the merchant SOI wafer industry on it. Hydrogen is implanted into the oxidized donor wafer to a precise depth, creating a buried plane of microscopic hydrogen-filled platelets. After bonding, a moderate anneal causes those platelets to grow and coalesce until the donor splits cleanly along the implanted plane, transferring a thin silicon layer to the handle and leaving the remainder of the donor available for reuse.

Smart Cut has three properties that made it the industry standard. Film thickness is determined by implant energy, an inherently well-controlled parameter, rather than by mechanical removal, so uniformity is excellent. Device layer and buried oxide thicknesses are chosen independently, since one comes from the implant and the other from the oxidation. And the donor wafer is recycled through many cycles, which brings cost within reach of volume production. Subsequent smoothing anneals and controlled oxidation-and-strip sequences reduce the transferred film to the few-nanometer thicknesses that fully depleted logic requires, with the uniformity that its threshold voltage demands.

Related Substrates

Silicon-on-sapphire predates modern SOI and follows a different route: silicon is grown heteroepitaxially on a sapphire wafer, which is an insulator throughout rather than only in a buried layer. The lattice mismatch leaves defects near the interface, historically limiting performance, though improved processing produced commercially successful radio-frequency products. Sapphire's complete absence of substrate conduction gives excellent isolation and linearity, at higher substrate cost. Its thermal behavior is easily misstated. Sapphire conducts heat far better than silicon dioxide does, by more than an order of magnitude, so silicon on sapphire suffers less self-heating than a thick buried oxide imposes, even though sapphire remains well below crystalline silicon.

Layer transfer also produces substrates that are not silicon-on-oxide at all. The same bonding and splitting techniques yield engineered wafers of many kinds, and the photonics industry relies on a particular SOI recipe, commonly a silicon film of about two hundred twenty nanometers on a buried oxide of two micrometers, in which the large refractive-index contrast between silicon and oxide confines light tightly enough to guide it around micrometer-scale bends. Micromechanical fabrication uses SOI for a purely dimensional reason: the buried oxide is an ideal etch stop, so the thickness of a released mechanical structure is set by the wafer specification rather than by etch timing.